KR100942820B1 - Manufacturing method of printed circuit board using electrolytic plating lead - Google Patents

Abstract

Disclosed is a first to third process of manufacturing a substrate on which a copper plating layer is formed on a front surface of a dynamic layer plate, filling the inside of the conductive hole with an epoxy-based ink, and planarizing the plurality of conductive holes in the dynamic layer plate by a drill process. A fourth step of forming a copper circuit by an etching process after first photosensitive printing on the planarized substrate with a first dry film, exposing and developing the first dry film, and then first peeling the first dry film; A second step of photosensitive printing on the substrate using a gold plated masking dry film, followed by exposure and development to form a gold plated masking, forming an electrolytic nickel / gold plated layer using gold plated masking, and then the gold plated masking dry film. In the sixth step of second peeling, a third photosensitive print is performed on the substrate using a second dry film, and the light is exposed and developed. After forming the li / nickel-gold plating circuit 23a, a third step of peeling the second dry film is performed, and a solder resist is applied to a predetermined portion of the nickel-gold plated substrate, and exposed, developed, and dried. A semiconductor package substrate manufacturing method without a plating lead wire formed in an eighth step.

Plating lead wire, semiconductor package substrate, circuit pattern, nickel and gold plating process

Description

Manufacturing method of printed circuit board using electrolytic plating lead

The present invention relates to a method for manufacturing a semiconductor package substrate without a plating lead wire, so that copper of the lower surface of the substrate can serve as an electrical conductor without using an additional conductive layer, and the upper and lower surfaces of the substrate The present invention relates to a method for manufacturing a semiconductor package substrate which minimizes the reduction of copper by forming a pattern on a bottom surface of gold plating.

1 is an overall configuration diagram showing a conventional method for manufacturing a semiconductor package substrate.

Conventionally, a semiconductor package substrate without a plating lead wire was manufactured by forming patterns of upper and lower surfaces, connecting the NET of a circuit through an additional conductive layer, gold plating, and then removing the conductive layer.

However, as shown in FIG. 1, the prior art is formed between the gold plating mask, which is the second masking mask, and the mask for the first etching, in the process of laminating and removing the conductive layer for gold plating by etching. There was a problem that one copper plating layer was excessively reduced.

The present invention has been invented to solve the above problems of the prior art, the object of which is to form a pattern on the upper surface of the substrate, the copper of the lower surface of the substrate (Copper) serves as an electrical conductor without using an additional conductive layer It is possible to do the gold plating of the upper and lower surfaces of the substrate, and by forming a pattern on the lower surface of the substrate to minimize the reduction of the copper (Copper), there is no plating lead wire to solve the problems of the prior art It is an object of the present invention to provide a method for manufacturing a semiconductor package substrate.

In order to solve the above problems, the present invention, the first step of forming a plurality of through-holes using a drill on a dynamic layer plate is formed on both sides of the prepreg, copper foil layer; A second step of manufacturing a substrate on which a copper plating layer is formed by performing electroless chemical copper plating on the full plane of the conductive layer plate in which the through hole is processed; A third step of filling the through hole with an epoxy-based ink and planarizing the substrate; First photosensitive printing on the planarized substrate with a first dry film, exposure and development to form a copper circuit masking, and then a part of the copper foil layer and copper plating layer is removed by an etching process to remove copper as a primary circuit pattern. A fourth step of first peeling the first dry film after forming a circuit and a copper plating layer; A fifth step of forming a gold plating mask on the substrate on which the first circuit pattern is formed by a second photosensitive print using a gold plating masking dry film, and exposing and developing the solder ball pad and a wire bonding pad to open a position region of the solder ball pad; A sixth step of performing an electrolytic nickel / gold plating process on the substrate on which the gold plating masking is formed to form an electrolytic nickel / gold plating layer, and second peeling of the dry film for gold plating masking; After the third photosensitive printing on the substrate on which the electrolytic nickel / gold plated layer was formed with a second dry film, exposure and development to form a nickel-gold plated circuit masking, the copper foil layer and a part of the copper plating layer were removed by an etching process. A seventh step of forming a copper / nickel-gold plating circuit as a difference circuit pattern on the other surface of the substrate and third peeling off of the second dry film; The above-mentioned problem is solved by using a method of manufacturing a semiconductor package substrate without a plating lead wire, which comprises an eighth step of applying a solder resist to a predetermined portion of the substrate on which the secondary circuit pattern is formed, exposing, developing and drying.
The copper foil layer formed on the lower surface of the prepreg is characterized in that it serves as a conductor.
The copper circuit, which is the primary circuit pattern formed in the fourth step, is formed by stacking a copper foil layer and a copper plating layer, and forms a pattern on only one surface of the substrate and masks the entire other surface of the substrate.
The copper / nickel / gold plating circuit, which is the secondary circuit pattern formed in the seventh step, is formed by sequentially stacking a copper foil layer, a copper plating layer, and a nickel / gold plating layer, and the nickel / gold plating layer forms a pattern only on the other side of the substrate. Forming and masking the entire copper circuit formed on one surface of the substrate is characterized in that the form.

The present invention made of the configuration as described above is a copper formed on the lower surface without the use of an additional conductive layer after forming a pattern of the upper surface (Copper) serves as an electrical conductor, the upper surface and the lower surface gold-plated After the pattern is formed on the lower surface it can minimize the copper (Copper) reduction, and since the conductive layer is not used, the process is simplified to reduce the manufacturing cost.

In addition, the problem that the pattern width (thickness) and the thickness (thickness) is non-uniform due to the excessive etching of a specific portion, there is an effect that can improve the reliability and quality of the product.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2A to 2I are cross-sectional views of manufacturing substrates for each process illustrated to explain a method of manufacturing a semiconductor package substrate without a plating lead wire according to the present invention, and FIG. 3 is a manufacturing of a semiconductor package substrate without a plating lead wire according to the present invention. Process flow chart.
As shown in FIGS. 2A to 2I and 3, in the method of manufacturing a semiconductor package substrate without a plating lead wire according to the present invention, a first step of forming a through hole 14 on a dynamic layer plate 10 (S10) is performed. FIG. 2A is a second step (S20; FIG. 2B) of manufacturing a substrate on which a copper plating layer 13 is laminated on a full plane of the dynamic layer plate 10, and an epoxy-based ink 15 in a through hole 14; ), And a third step (S30; FIG. 2C) to fill and planarize, a fourth step (S40; FIG. 2D) to form a copper circuit 23 as a primary circuit pattern on one surface of the substrate, 5th step S50 (FIG. 2E) which forms the gold plating masking 17b, 6th step S60 (FIG. 2F) which forms the electrolytic nickel-gold plating layer 18 using the said gold plating masking 17b, electrolytic nickel A seventh step (S70; Fig. 2G, Fig. 2H) of forming a copper / nickel-gold plating circuit 23a as a secondary circuit pattern on the substrate on which the gold plating layer 18 is formed, and drying by applying a solder resist 19; Step 8; may be made of a (S80 Fig. 2i).

First, as illustrated in FIG. 2A, in the first step S10, a plurality of conductions are conducted by using a drill on the dynamic layer plate 10 in which the copper foil layer 12 is formed on both upper and lower surfaces of the prepreg 11. The hole 14 is formed (S10), and in the second step (S20), electroless chemical copper plating is performed on the full plane of the dynamic layer plate 10 processed by the drilling process, as shown in FIG. 2B. A substrate on which the copper plating layer 13 is formed is manufactured (S20). Subsequently, in the third step S30, the inside of the through hole 14 is filled with the epoxy-based ink 15 as shown in FIG. 2C, and the substrate is planarized (S30). The copper foil layer 12 formed on the lower surface can serve as a conductor.

Next, in the fourth step S40, as shown in FIG. 2D, the first photosensitive printing is performed on the copper plating layer 13 of the substrate using the first dry film 16a, followed by exposure and development. After the copper circuit masking is formed, the copper foil layer 12 and the copper plating layer 13 on the upper surface of the substrate are removed by an etching process to form a copper circuit 23 as a primary circuit pattern, and then the first dry film 16a. The first peeled off. (S40)

In this case, the copper circuit 23 as the primary circuit pattern is formed by sequentially stacking the copper foil layer 12 and the copper plating layer 13, and is formed only on the upper surface of the substrate as shown in FIG. 2D. A pattern is not formed in the bottom surface, and a full plane of the lower surface is covered by the copper foil layer 12 and the copper plating layer 13.

Subsequently, in a fifth step S50, as shown in FIG. 2E, second photosensitive printing is performed on the substrate on which the primary circuit pattern is formed by a dry film 17 for gold plating masking, and the exposure and It is developed to form a gold plating masking 17b which opens the position areas of the solder ball pad and the wire bonding pad.
Next, in the sixth step S60, as shown in FIG. 2F, an electrolytic nickel / gold plating process is performed on the substrate on which the gold plating masking 17b is formed, thereby electrolytic nickel in the open region 17a of the gold plating masking 17b. A gold plated layer 18 is formed. Thereafter, the gold plating masking dry film 17 is secondarily peeled off.

Subsequently, in the seventh step S70, as shown in FIGS. 2G and 2H, the second dry film 16b is formed on the substrate on which the electrolytic nickel-gold plating layer 18 is formed and then the gold plating masking dry film 17 is peeled off. ) Third photosensitive printing. In this case, the electrolytic nickel / gold plating layer 18 formed in the open region 17a of the gold plating masking 17b is covered by the second dry film 16b. Subsequently, the lower surface of the third photosensitive printed substrate is exposed and developed to form nickel and gold plated circuit masking, and then a part of the copper foil layer 12 and the copper plated layer 13 is removed by an etching process, thereby forming copper as a secondary circuit pattern. The nickel-gold plating circuit 23a is formed on the other surface of the substrate. Thereafter, the second dry film 16b is thirdly peeled off. The copper / nickel-gold plating circuit 23a, which is a secondary circuit pattern formed at this time, is formed by sequentially stacking a copper foil layer 12, a copper plating layer 13, and a nickel-gold plating layer 18. The electrolytic nickel / gold plating The layer 18 is formed to form a pattern only on the other side of the substrate and mask the entire copper circuit 23 formed on one side of the substrate.

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After the third peeling, and finally, in the eighth step S80, as shown in FIG. 2I, a predetermined portion of the substrate on which the secondary circuit pattern is formed, that is, a wire bonding pad and a solder ball of a nickel-gold plated substrate. The semiconductor package substrate without a plating lead wire is applied by applying a solder resist 19 to a portion except for the nickel-gold plated portion of the s), exposing with ultraviolet rays, and then treating and drying the remaining residue on the substrate through development. It is possible to complete the manufacture of.

In addition, in the above process, the copper foil layer 12 formed on the lower surface of the dynamic layer plate serves as an electrical conductor without using an additional conductive layer.

As described above, preferred embodiments of the present invention have been described, but the present invention is not limited to the above-described embodiments, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Anyone with knowledge of the present invention will have the methodology of the present invention to the extent that various modifications can be made.

1 is an overall configuration diagram showing a conventional method for manufacturing a semiconductor package substrate.

2A to 2I are cross-sectional views of manufacturing substrates for each process illustrated to explain a method for manufacturing a semiconductor package substrate without a plating lead wire according to the present invention.

3 is a flowchart illustrating a manufacturing process of a semiconductor package substrate without a plating lead wire according to the present invention.

** SIGNS FOR MAIN PARTS OF THE DRAWINGS **

10 Dynamic layer 11 Prepreg 12 Copper foil layer

13 copper plating layer 14 through hole 15 epoxy ink

16a, 16b: dry film 17: gold-plated masking dry film

17a: Gold-plated masking open area 17b: Gold-plated masking

18 electrolytic nickel-plated layer 19 solder resist
23: copper circuit 23a: copper / nickel-gold plating circuit

Claims (4)

A first step of forming a plurality of conductive holes 14 on a dynamic layer plate 10 having copper foil layers 12 formed on both upper and lower surfaces of the prepreg 11 by using a drill; A second step of manufacturing a substrate on which the copper plating layer 13 is formed by performing electroless chemical copper plating on the full plane of the dynamic layer plate 10 in which the through hole 14 is processed; A third step of filling the conductive hole 14 with an epoxy-based ink 15 and planarizing the substrate; First photosensitive printing on the planarized substrate using a first dry film 16a, exposure and development to form a copper circuit masking, and then an copper foil layer 12 and a copper plating layer 13 by an etching process. A fourth step of first removing the first dry film 16a by forming a copper plating layer with a copper circuit 23 as a primary circuit pattern by removing a part of the first circuit pattern; Gold-plated masking (17b) in which the secondary photosensitive printing is performed on the substrate on which the primary circuit pattern is formed with a gold-plated masking dry film 17, and the exposure and development are performed to open the position areas of the solder ball pad and the wire bonding pad. Forming a fifth step; A sixth step of performing an electrolytic nickel / gold plating process on the substrate on which the gold plating masking (17b) is formed to form an electrolytic nickel / gold plating layer (18), and then secondly peeling off the gold film masking dry film (17); The third photosensitive printing is performed on the substrate on which the electrolytic nickel / gold plating layer 18 is formed by the second dry film 16b, and is exposed and developed to form a nickel-gold plating circuit masking, followed by an etching process. A part of removing the copper foil layer 12 and a part of the copper plating layer 13 to form a copper / nickel-gold plating circuit 23a, which is a secondary circuit pattern, on the substrate and to third peel the second dry film 16b. Step 7; An eighth step of applying, exposing, developing and drying a solder resist 19 on a predetermined portion of the substrate on which the secondary circuit pattern is formed; A semiconductor package substrate manufacturing method without a plating lead wire. The method of claim 1, The copper foil layer (12) formed on the lower surface of the prepreg (11) acts as a conductor, characterized in that the semiconductor package substrate manufacturing method without a plating lead wire. The method of claim 1, The copper circuit 23, which is the primary circuit pattern formed in the fourth step, is formed by stacking the copper foil layer 12 and the copper plating layer 13, and forms a pattern on only one surface of the substrate and masks the entire other surface of the substrate. Method of manufacturing a semiconductor package substrate without a plating lead wire, characterized in that formed in the form. The method of claim 1, The copper / nickel-gold plating circuit 23a, which is a secondary circuit pattern formed in the seventh step, is formed by sequentially stacking a copper foil layer 12, a copper plating layer 13, and a nickel / gold plating layer 18. The nickel-gold plating layer (18) is a pattern for manufacturing a semiconductor package substrate without a plating lead wire, characterized in that to form a pattern only on the other side of the substrate and mask the entire copper circuit (23) formed on one side of the substrate.

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