KR100941656B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the wafer supporting means may be formed by stacking and attaching the surfaces of the wafers with bonding pads in advance, and forming through-silicon vias on the respective wafer back surfaces in the stacked state. It is to provide a semiconductor device and a method of manufacturing the same, which are very advantageous for handling without using and do not require a separate chip stacking process during packaging as chips are stacked in advance in a wafer state, and can realize more input / output terminals. .

To this end, the present invention and the first and second wafer is laminated to each other with the bonding pad of each chip; A cavity formed on each back surface of the first and second wafers; A vertical hole penetrated from the bottom surface of the cavity to each chip bonding pad of the first and second wafers; A conductive metal embedded in the cavity and the vertical hole to be electrically connected to a bonding pad of each chip; It provides a semiconductor device characterized in that the configuration.

Semiconductor Device, Wafer, Lamination, Semiconductor Chip, Cavity, Conductive Metal, Vertical Hole

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor chip for a laminated chip package, a semiconductor device having a structure in which the semiconductor chip is easily laminated, and a manufacturing method thereof.

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. This is a stacked package, which is commonly referred to as a stacked chip package.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while lacking wiring space for the electrical connection inside the package due to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate, so that the bonding pads of the chips and the conductive circuit patterns of the substrate are electrically connected to each other by wire, so that the wire bonding is possible. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

In view of this, a structure using through silicon vias (TSV) has been proposed as an example of a stack package. After forming through silicon vias in each chip at the wafer stage, the through silicon vias are perpendicular to each other. As a structure to allow physical and electrical connection between the chips, the conventional manufacturing process is briefly described as follows.

4 is a cross-sectional view illustrating a process of forming a conventional through silicon via.

First, a vertical hole 102 is formed in a portion adjacent to a bonding pad of each chip 100 at a wafer level, and an insulating film (not shown) is formed on the surface of the vertical hole 102.

In the state in which the seed metal film is formed on the insulating layer, a through silicon via 106 is formed by filling an electrolytic material, that is, a conductive metal 104, through the electroplating process in the vertical hole 102.

Next, the backside of the wafer is back ground to expose the conductive metal 104 embedded in the through silicon vias 106.

Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are vertically stacked on the substrate vertically so as to be signal exchanged through the conductive metal of the through-silicon vias, and then the substrate upper surface including the stacked chips is molded, and the substrate The solder ball is mounted on the bottom surface to complete the stack package.

In various prior processes for implementing such a chip stack package, since the wafer is very thin, a separate wafer support system (WSS) is used to support the wafer during its handling. In one embodiment, glass or a silicon block body is used.

Accordingly, in the state where the wafer is supported and bonded to the glass or the silicon block body, a process of performing back grinding or thinning through silicon vias for thinning the wafer is performed, and thus, workability and productivity are deteriorated.

Thus, the process of forming through-silicon vias on each chip of the wafer, stacking chips with through-silicon vias, and handling wafers between the processes, without using a separate wafer support means, results in more separation from the bonding pads of each chip. There is a demand for a chip structure having a signal input / output terminal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above. As a result, the surfaces having the bonding pads of the wafers are laminated in advance, and through silicon vias are formed on each wafer back surface in the stacked state, so that no separate wafer support means is used. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which are very advantageous for handling a furnace and do not require a separate chip stacking process during packaging as chips are stacked in a wafer state in advance.

The present invention for achieving the above object comprises: a first wafer and a second wafer are laminated with the bonding pads of each chip; A cavity formed toward the bonding pad of each chip from the back surfaces of the first and second wafers; A vertical hole penetrated from the bottom surface of the cavity to each chip bonding pad of the first and second wafers; A conductive metal embedded in the cavity and the vertical hole to be electrically connected to a bonding pad of each chip; It provides a semiconductor device characterized in that the configuration.

In a preferred embodiment, the third to n wafers are electrically connected to each other through the conductive metal and further stacked on the first and second wafers stacked on each other.

In another preferred embodiment, the cavity corresponding to the bonding pad adjacent to the sawing line among the bonding pads of the chip is characterized in that the outer surface thereof is open and the conductive metal is laterally exposed to the open portion.

In particular, the laterally exposed conductive metals are electrically connected to each other, so that the semiconductor chips can be laminated laterally.

The present invention for achieving the above object comprises the steps of: having a plurality of chips having first and second wafers of the same size partitioned in the horizontal and vertical directions; Stacking and attaching the first and second wafers to each other with the bonding pads of each chip; Forming a cavity in the back surface of the first and second wafers; Forming a vertical hole from a bottom surface of the cavity of the first and second wafers to a bonding pad of each chip; Embedding a conductive metal electrically connected to a bonding pad in the cavity and the vertical hole; It provides a semiconductor device manufacturing method comprising a.

In a preferred embodiment, the step of further stacking while electrically connecting the 3 to n wafers through the conductive metal embedded in the cavity on the first and second wafers stacked on each other.

In another preferred embodiment, after the sawing step of the chips constituting the first to n wafers, the cavity corresponding to the bonding pad adjacent to the sawing line is opened at its outer side and the conductive metal side is opened to the opened portion. Characterized in that it is exposed in the direction.

In particular, the step of laminating the sawed semiconductor chip in the lateral direction while electrically connecting the laterally exposed conductive metals is further characterized.

Through the above problem solving means, the present invention can provide the following effects.

The wafer bonding pads are bonded to each other in advance, and through silicon vias are formed on the back surface of each wafer in the stacked state to prevent the shaking phenomenon when handling the wafer without using a separate wafer support means due to the increase in thickness. At the same time, warpage can be reduced.

In addition, since the chip is stacked in advance in the wafer state, there is an advantage that a separate chip stacking process is not required during packaging.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is to provide a chip stack structure and a method of stacking the plurality of wafers in advance at the wafer level, and then through-via vias are formed in the bonding pads of each chip so that the chips of each wafer are electrically connected. .

First embodiment

First and second wafers 10 and 12 have completed wafer backgrinding.

A plurality of semiconductor chips are arranged in the horizontal and vertical directions on the first and second wafers 10 and 12, and the boundary lines between the chips are formed as sawing lines that are later separated into individual chips.

The first and second wafers 10 and 12 provided as described above are stacked and attached, and the bonding pads of the first chip 14 constituting the first wafer and the second chip 16 constituting the second wafer are provided. Laminating and attaching to each other, of course, the back surface of the first and second wafers 10 and 12 are exposed to each other up and down.

Next, the cavity 20 is formed on the back surfaces of the first and second wafers 10 and 12, and the cavity 20 is formed in the same number as the bonding pads 18 of the respective chips 14 and 16. do.

Subsequently, vertical holes 22 are formed through the bottom surface of the cavity 20 to the bonding pads 18 of the chips 14 and 16 of the first and second wafers 10 and 12.

At this time, the cavity 20 and the vertical hole 22 can be easily formed by a conventional method such as chemical etching, laser processing.

Next, in the cavity 20 and the vertical hole 22, a conductive metal 24 electrically connected to the bonding pads 18 of the chips 14 and 16 is embedded. The embedding method may be buried in a conventional printing method, or may be buried in a plating method, and any other buried method may be used.

Accordingly, the bonding pads 18 of the chips 14 and 16 of the first and second wafers 10 and 12 are buried through the through silicon vias 30, that is, the cavity 20 and the vertical hole 22. In the state of being electrically connected with the conductive metal 24, the semiconductor chips stacked in advance in the wafer stage may be sawed and applied to the manufacture of the laminated chip package.

Meanwhile, the third to n wafers 32 are contacted with the conductive metals 24 embedded in the cavities 20 of the chips 14 and 26 on the first and second wafers 10 and 12 stacked on each other. 34 can be further electrically laminated.

That is, as shown in the last drawing of FIG. 1, the conductive metal 24 embedded in the cavity 20 of each second chip 16 of the second wafer 12 is formed of the third wafer 32. The desired number of semiconductor chips can be stacked while electrically contacting the conductive metals 24 embedded in the cavities 20 of the third chips 26, and then the first to nth wafers 10, 12, When 32, 34 are sawed at once, the first to nth chips 14, 16, 26, 28 are stacked on top of each other from the bottom to the top.

Second embodiment

Unlike the first embodiment in which chips are stacked in the vertical direction, the semiconductor device according to the second embodiment of the present invention has a main point in that the chips can be stacked and arranged in the vertical and horizontal directions.

First, the first and second wafers 10 and 12 having wafer backgrinding are completed, and a plurality of semiconductor chips are arranged in the first and second wafers 10 and 12 in the horizontal and vertical directions. The boundary line between each chip is formed by a sawing line which is later separated into individual chips.

The first and second wafers 10 and 12 provided as described above are stacked and attached, but the first chip 14 constituting the first wafer 10 and the second chip 16 constituting the second wafer 12 are provided. Surfaces with bonding pads are laminated to each other, and the back surfaces of the first and second wafers 10 and 12 are, respectively, exposed up and down.

Next, the cavity 20 is formed on the back surfaces of the first and second wafers 10 and 12, and each of the first chips 14 and the second wafers 12 of the first wafer 10 is formed. Cavities 20 are formed in the same number as the bonding pads 18 of the two chips 16, and in particular, the cavities 20 matching the bonding pads 18 at the edge regions of the chips 14 and 16 Form in a wide size.

That is, the cavity 20 corresponding to the bonding pads 18 arranged on the edges of the first and second chips 14 and 16 is opened to the upper side or the lower side, but is formed in a lateral structure. .

In other words, of the bonding pads of the first chip 14 of each of the first wafers 10 and the second chip 16 of each of the second wafers 12, the bonding pads 18 adjacent to the sawing line The cavity 20 corresponding to the bonding pads arranged on the edge side is formed in a structure in which the lower side thereof is opened as well as the outer side thereof.

Next, the vertical hole 22 penetrates from the bottom surface of the cavity 20 to the bonding pads 18 of the first and second chips 14 and 16 of the first and second wafers 10 and 12. do.

At this time, the cavity 20 and the vertical hole 22 can be easily formed by a conventional method such as chemical etching, laser processing.

Subsequently, the conductive metal 24, which is electrically connected to the bonding pads 18 of the chips 14 and 16, is embedded in the cavity 20 and the vertical hole 22, and the conductive metal 24 is embedded. The method may be buried in a conventional printing method as in the first embodiment, or may be buried in a plating method, and any other buried method may be used.

Accordingly, the bonding pads 18 of the chips 14 and 16 of the first and second wafers 10 and 12 may be formed of conductive metals embedded through through silicon vias, that is, through the cavity 20 and the vertical hole 22. 24), the semiconductor chips stacked in advance in the wafer stage can be sawed and applied to the manufacture of the laminated chip package.

At this time, after the sawing step of the first and second wafers 10 and 12, the cavity 20 coinciding with the edge bonding pads 18 of the first and second chips 14 and 16 is also open in the lateral direction. In this state, the conductive metal 24 embedded in the cavity 20 is also exposed in the lateral direction.

Accordingly, as shown in the last drawing of FIG. 2, the first and second chips 14 and 16 are stacked up and down, and the first and second conductive metals 24 are exposed in contact with each other. The third and n-th chips 26 and 28 stacked on each other in the same manner as the second chip may be stacked in the left and right directions.

Third embodiment

The third embodiment of the present invention is characterized in that the first and second wafers are laminated in the last step without being laminated in advance.

First, the first and second wafers 10 and 12 are back ground, respectively, and then coincident with the bonding pads 18 of the chips 14 and 16 on the back surfaces of the first and second wafers 10 and 12, respectively. The cavity 20 is formed as much as possible, and vertical holes 22 are successively formed from each cavity 20 to the bonding pads 18 of the chips 14 and 16.

Next, the conductive metal 24 is embedded in the cavity 20 and the vertical hole 22 so that the conductive metal 24 and the bonding pads 18 of the chips 14 and 16 are electrically connected.

Subsequently, the first and second wafers 10 and 12 are laminated and bonded to each other, and bonding of the first chips 14 of the first wafer 10 and the second chips 16 of the second wafer 12 is performed. The surfaces on which the pads 18 are formed are laminated together.

The semiconductor device of this third embodiment differs only in the step of stacking and attaching a wafer to the first and second embodiments, and the structure thereof can be manufactured in the same manner.

1 is a partial cross-sectional perspective view showing an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention;

2 is a partial cross-sectional perspective view showing another embodiment of a semiconductor device and a method of manufacturing the same according to the present invention;

3 is a partial cross-sectional perspective view showing still another embodiment of a semiconductor device and a method for manufacturing the same according to the present invention;

4 is a cross-sectional view illustrating a process of forming a conventional through silicon via.

<Explanation of symbols for the main parts of the drawings>

10: first wafer 12: second wafer

14: first chip 16: second chip

18: bonding pad 20: cavity

22: vertical hole 24: conductive metal

26: third chip 28: n-th chip

30: through silicon via 32: third wafer

34: n-wafer

Claims (8)

First and second wafers laminated with the bonding pads of each chip; A cavity formed toward the bonding pad of each chip from the back surfaces of the first and second wafers; A vertical hole penetrated from the bottom surface of the cavity to each chip bonding pad of the first and second wafers; A conductive metal embedded in the cavity and the vertical hole to be electrically connected to a bonding pad of each chip; A semiconductor device, characterized in that consisting of. The semiconductor device of claim 1, wherein the third to n wafers are electrically connected to each other through the conductive metal on the first and second wafers stacked on each other and further stacked. The semiconductor device according to claim 1, wherein a cavity corresponding to a bonding pad adjacent to a sawing line among the bonding pads of the chip is open at an outer side thereof, and the conductive metal is laterally exposed to the open portion. . The semiconductor device according to claim 3, wherein the laterally exposed conductive metals are electrically connected to each other so that the semiconductor chips can be stacked laterally. A plurality of chips having first and second wafers of equal size partitioned in the horizontal and vertical directions; Stacking and attaching the first and second wafers, and stacking the surfaces of each chip with bonding pads; Forming a cavity in the back surface of the first and second wafers; Forming a vertical hole from a bottom surface of the cavity of the first and second wafers to a bonding pad of each chip; Embedding a conductive metal electrically connected to a bonding pad in the cavity and the vertical hole; A semiconductor device manufacturing method comprising a. The semiconductor device manufacturing as claimed in claim 5, wherein the stacking process is further performed while electrically connecting the 3 to n wafers through the conductive metal embedded in the cavity on the first and second wafers stacked on each other. Way. The method of claim 5, wherein after the sawing step of the chips constituting the first to n wafers, the cavity corresponding to the bonding pad adjacent to the sawing line is open at its outer side, and the conductive metal is laterally directed to the opened portion. A semiconductor device manufacturing method characterized in that the exposure to. The method of manufacturing a semiconductor device according to claim 7, further comprising laterally stacking the sawed semiconductor chip while electrically connecting the laterally exposed conductive metals.

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