KR100884192B1 - Manufacturing method of semiconductor package - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor package, the technical problem to be solved by attaching a film-type underfill or semi-hardened underfill together to the backgrinding film used in the backgrinding of the semiconductor die, to easily perform the subsequent underfill process without defect To do.

To this end, the present invention provides a wafer preparation step of preparing a semiconductor die by forming a passivation layer on the outer periphery of the bond pad and the bond pad, a wafer bumping step of forming a conductive bump to be electrically connected to the bond pad of the semiconductor die, and a semiconductor A wafer taping step of attaching a tape having a semi-hardened underfill or film underfill and a backgrinding film to the die and the conductive bump, and a backgrinding step and a wafer taping step of grinding the opposite side of the surface where the bond pads of the semiconductor die are formed. Disclosed is a method of manufacturing a semiconductor package comprising a wafer detapping step of removing a backgrinding film from a tape.

Semiconductor Package, Flip Chip, Underfill, Flux, Film

Description

Manufacturing method of semiconductor package {MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE}

The present invention relates to a method for manufacturing a semiconductor package, and more particularly, by attaching a film type underfill or a semi-cured underfill together to a backgrinding film used for backgrinding of a semiconductor die, the subsequent underfill process can be easily performed without defects. The present invention relates to a method for manufacturing a semiconductor package.

In general, semiconductor packages have an insertion method such as dual in-line package (DIP) and pin grid array (PGA), quad flat package (QFP), plastic leaded chip array (PLCC), and ceramic leaded (CLCC), depending on the mounting method. It is classified into a surface mount technology (SMT) method such as a chip carrier and a ball grid array (BGA).

In particular, surface mount packages are more widely used than insert packages because they are advantageous for miniaturization of electronic devices. In such a surface-mount package, a method of connecting a semiconductor chip and a circuit board is mainly used to manufacture a flip chip package in order to accommodate all of the increased number of terminals on a limited circuit board due to high performance of the semiconductor chip.

In such a flip chip package manufacturing process, underfill is generally provided in the space between the semiconductor chip and the circuit board. The underfill serves to protect the package structure from external influences such as mechanical shock and corrosion of the joint, and to improve the reliability of the packaged product by minimizing the stress caused by the difference in thermal expansion coefficient between the chip and the substrate.

However, since the underfill is a separate process of injecting between the semiconductor chip and the circuit board using a dispenser in a liquid state, the working yield is reduced. As the semiconductor package is miniaturized, the semiconductor chip size gradually decreases, thereby reducing the size of the conductive bumps and shortening the distance between the conductive bumps. That is, the distance between the conductive bumps becomes fine pitch. As such, when the distance between the conductive bumps becomes fine pitch, when the underfill is injected between the semiconductor chip and the circuit board with a dispenser, the filler in the liquid underfill is larger than the distance between the conductive bumps and thus the distance between the conductive bumps. It can get caught or fixed, or cause a defect such as void. Due to this phenomenon, underfill is not formed to a certain thickness, thereby protecting the package structure from external influences such as mechanical shock and corrosion of the joint, and minimizing stress due to thermal expansion coefficient difference between the semiconductor chip and the circuit board. You will not be able to play the role of an underfill to improve your performance.

SUMMARY OF THE INVENTION The present invention is to overcome the above-mentioned conventional problems, and an object of the present invention is to manufacture a semiconductor package capable of preventing filler settling or voiding by using a film type underfill or a semi-cured underfill. To provide a method.

In addition, another object of the present invention is to attach the film-type underfill or semi-cured underfill to the semiconductor die when attaching the backgrinding film, it is possible to omit the step of separately filling the liquid underfill to increase the productivity and work yield It is to provide a method of manufacturing a package.

In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention includes a wafer preparation step of preparing a semiconductor die by forming a passivation layer on a bond pad and an outer circumference of the bond pad; A wafer bumping step of forming a conductive bump so as to be connected to the wafer, a tape taping step of attaching a tape including a semi-hardened underfill and a backgrinding film to the semiconductor die and the conductive bump, and an opposite side of the semiconductor die on which a bond pad is formed It may include a back grinding step of grinding the surface and a wafer detapping step of removing the back grinding film of the tape attached in the wafer taping step.

After the wafer detapping step, it may further comprise a wafer sawing step of sawing the semiconductor die and the semi-cured underfill to separate from the wafer into individual semiconductor chips.

After the wafer sawing step may include a semiconductor chip attach step of bonding the semiconductor chip to the circuit board.

The circuit board has a first flat surface and a second flat surface as an opposite surface of the first surface, at least one first wiring pattern is formed on the first surface, and at least one first surface on the second surface. It may be formed of an insulating layer having a two-wire pattern formed thereon.

The first wiring pattern and the second wiring pattern of the circuit board may be electrically connected to conductive vias formed in the insulating layer.

A first solder mask and a second solder mask may be formed on the outer periphery of the first wiring pattern and the second wiring pattern of the circuit board, respectively.

After the semiconductor chip attach step, the semiconductor chip and the circuit board may be heat-treated to further include a reflow step of electrically connecting the conductive bumps of the semiconductor chip to the circuit board.

In the reflow step, the conductive bumps of the semiconductor chip and the wiring patterns formed on the circuit board may be electrically connected.

In the reflow step, the semi-cured underfill may be completely cured, and the conductive bumps of the semiconductor chip may be deposited on the wiring pattern formed on the circuit board.

The tape attached to the semiconductor die and the conductive bump in the wafer taping step may include the semi-cured underfill and the backgrinding film, and the semi-cured underfill and the backgrinding film may be adhered with an adhesive.

The adhesive formed between the semi-cured underfill and the backgrinding film may have stronger adhesive force with the semi-cured underfill than with the semi-cured underfill.

In the wafer detapping step, the adhesive may be removed from the backgrinding film and the adhesive together with the semi-hardened underfill attached to the adhesive.

The tape attached to the semiconductor die and the conductive bump in the wafer taping step may include the semi-cured underfill and the backgrinding film, and a flux may be interposed between the semi-cured underfill and the backgrinding film.

An adhesive may be interposed between the flux and the backgrinding film in the wafer taping step.

The adhesion between the backgrinding film and the adhesive may be stronger than the adhesion between the adhesive and the flux.

In the wafer detapping step, the adhesive may be separated from the portion bonded to the flux so that the backgrinding film and the adhesive agent may be removed together.

After the wafer detapping step, the semiconductor die, the semi-cured underfill and the flux may be sawed to further separate the wafer from the wafer into individual semiconductor chips.

After the wafer sawing step may include a semiconductor chip attach step of bonding the semiconductor chip to the circuit board.

After the semiconductor chip attach step, the semiconductor chip and the circuit board may be heat-treated to further include a reflow step of electrically connecting the conductive bumps of the semiconductor chip to the circuit board.

In the reflow step, the semi-cured underfill is completely cured, and at the same time, the flux is removed, and conductive bumps of the semiconductor die may be deposited on a circuit board.

As described above, in the method of manufacturing a semiconductor package according to the present invention, as the conductive bumps of the semiconductor chip become fine pitches, filler fixing and voiding are performed by using a film type underfill or a semi-cured underfill. It is possible to prevent defects such as).

In addition, as described above, the method for manufacturing a semiconductor package according to the present invention attaches a film type underfill or a semi-cured underfill to a semiconductor die when attaching a backgrinding film, thereby eliminating the process of separately filling a liquid underfill, thereby improving productivity and Work yield is improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

Referring to FIG. 1, a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention is shown.

As shown in FIG. 1, the method of manufacturing a semiconductor package according to the present invention includes a wafer preparation step S1, a wafer bumping step S2, a wafer tapping step S3, and back grinding. A step S4, a wafer detaping step S5, a wafer saw step S6, a semiconductor chip attach step S7, and a reflow step S8. .

2A through 2H are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 1.

As shown in FIG. 2A, in the wafer preparation step S1, a first surface 111 that is substantially flat or completely flat, and a second surface 112 that is substantially flat or completely flat as an opposite surface of the first surface 111. At least one bond pad 115 is formed on the first surface 111, and a semiconductor die 110 having a passivation layer 116 having a predetermined thickness formed on an outer circumference of the bond pad 115. The wafer 100a is prepared. The passivation layer 116 may be formed of any one selected from conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide, nitride, and equivalents thereof. It does not limit the material. Of course, the nitride film or the oxide film may be formed by flowing silicon gas, nitrogen, silicon gas and oxygen, and the polyimide and epoxy may be formed by coating or spraying.

As illustrated in FIG. 2B, in the wafer bumping step S2, the conductive bumps 120 are formed on the bond pads 115 of the semiconductor die 110. The conductive bumps 120 are electrically connected to the bond pads 115. The conductive bumps 120 may be formed using any one of conventional ball drop, screen printing, electroplating, vacuum deposition, plating, and the like. It does not limit the method. The conductive bumps 120 may be formed using any one selected from metal materials such as tin / lead (Pb / Sn) and leadless tin, and equivalents thereof, but the material is not limited thereto. .

As shown in FIG. 2C, in the wafer taping step S3, the tape 130 is attached to the passivation layer 116 and the conductive bump 120 of the semiconductor die 110. The tape 130 includes a semi-cured underfill 131, an adhesive 132, and a backgrinding film 133. The tape 130 is attached to the first surface 111 to grind the second surface 112 of the semiconductor die 110 in the wafer backgrinding step S4 to be described later, and the outer circumference of the tape 130. A ring may be formed in the tape 130, and the tape 130 protects the first surface of the semiconductor die 110 in a backgrinding step S4. Indeed, if the ring is formed on the outer periphery of the tape 130 here, the handling of the wafer 100 is facilitated. The semi-cured underfill 131 may be formed using any one selected from an underfill member in the form of a semi-cured film including a flux component and an equivalent thereof. The semi-cured underfill 131 is attached to the passivation layer 116 and the conductive bump 120 of the semiconductor die 110 in the form of a semi-cured film through heat treatment. When the conductive bumps 120 are welded through the reflow apparatus, they may be completely cured. The tape 130 is typically supplied with the tape 130 on the wafer (100a) and then the adhesive can be adhered by pushing the tape 130 with a roller, but the method is not limited thereto.

As shown in FIG. 2D, in the back grinding step S4, the second surface 112 of the semiconductor die 110 is ground by a predetermined thickness to remove unnecessary portions. Such a backgrinding process can be carried out using, for example, a diamond grinder and its equivalents, but is not limited thereto. In the back grinding step S4, the back grinding film 133 may prevent the interlayer insulating layer, the metal wire, etc. constituting the active layer formed on the first surface 111 of the semiconductor die 110 from being damaged. It plays a role.

As shown in FIG. 2E, in the wafer detaping step S5, the first surface 111 of the semiconductor die 110 and the conductive bump 120 are formed in the wafer tapping step S3. The backgrinding film 133 is removed from the tape 130 attached to the tape 130. Of course, the tape 130 includes a semi-cured underfill 131, an adhesive 132, and a backgrinding film 133, and the adhesive 132 includes the semi-cured underfill 131 and the backgrinding film 133. It is formed between. In addition, the adhesive 132 may be more strongly bonded to the backgrinding film 133 than the portion bonded to the semi-cured underfill 131 to remove the backgrinding film 133 from the semi-cured underfill 131. The adhesive part is separated and the adhesive 132 and the backgrinding film 133 are removed together. Therefore, only the semi-cured underfill 131 remains on the first surface 111 and the conductive bump 120 of the semiconductor die 110. Thus, after the semiconductor chip and the circuit board are electrically connected, the package structure is protected from external influences such as mechanical shock and corrosion of the joint, and the stress due to the difference in thermal expansion coefficient between the semiconductor chip and the circuit board is minimized. A separate process for forming the underfill which serves to improve the reliability should be carried out, but in the present invention, since the underfill is already formed through the wafer taping step S3 and the wafer detapping step S5, the process time is shortened. There is an advantage of increased productivity and yield.

As shown in FIG. 2F, the sawing step S6 is sawing from the wafer 100a to the individual semiconductor chips 100 using a sawing tool 140 such as a diamond wheel or a laser beam. )do. For example, the sawing tool 140 sweeps all of a predetermined region of the semiconductor die 110 and the semi-cured underfill 131 to be separated from the wafer 100a into individual semiconductor chips 100.

As shown in FIG. 2G, in the semiconductor die attach step S7, the circuit board 200 may be transferred to the semiconductor chip 100 formed in the wafer sawing step S6 using a transfer member 300. Transfer to. In this case, the circuit board 200 has a flat first surface 220 and a flat second surface 230 as an opposite surface of the first surface 220, and at least one on the first surface 220. The first wiring pattern 221 may be formed, and the second surface 230 may be formed of an insulating layer 210 having at least one second wiring pattern 231 formed thereon. The first wiring pattern 221 and the second wiring pattern 231 may be electrically connected to each other by the conductive via 240 formed in the insulating layer 210. A first solder mask 222 may be formed on an outer circumference of the first wiring pattern 221, and a second solder mask 232 may be formed on an outer circumference of the second wiring pattern 231. The semiconductor chip (eg, the transfer member 300) contacts the conductive bumps 120 of the semiconductor chip 100 to a region corresponding to the first wiring pattern 221 formed on the first surface 220 of the circuit board 200. 100 is transferred and seated on the circuit board 200. The transfer member 300 may be in close contact with the second surface 112 of the semiconductor chip 100 to absorb and transfer the semiconductor chip 100, but the method is not limited thereto. In addition, although the printed circuit board is a hard printed circuit board as an example, a flexible printed circuit board or a lead frame may be used.

As shown in FIG. 2H, in the reflow step S8, the conductive bumps 120 of the semiconductor chip 100 seated on the first wiring pattern 221 of the circuit board 200 are fixed. The conductive bumps 120 are welded and electrically connected to the first wiring patterns 221 of the circuit board 200 through a reflow device having a temperature (150 to 250 ° C.), and the semi-cured underfill 131 is also provided. It is melted and evenly distributed in the space between the semiconductor chip 100 and the circuit board 200 and then completely cured to adhere to the semiconductor chip 100 and the circuit board 200. The semi-cured underfill 131 is cured hard enough to withstand the forces due to different thermal expansion coefficients of the semiconductor chip 100 and the circuit board 200. The reflow may be based on an infrared reflow, hot air reflow, infrared + hot air reflow, latent heat of vaporization of an inert solvent, and an equivalent method thereof according to a heating source, but the present invention is not limited thereto.

In the method of manufacturing the semiconductor package 1000, the backgrinding film and the semi-cured underfill attached together to protect the first surface of the semiconductor die are attached to the semiconductor die together to remove the backgrinding film after the backgrinding process. Only the semi-hardened underfill remains. Since it is possible to omit a separate liquid underfill filling process to be carried out in the future it is simplified compared to the conventional semiconductor package process to increase the productivity and work yield. In addition, since the semi-hardened underfill is attached to the film, the filler of the underfill is larger than the distance of the conductive bump when the conventional liquid underfill is injected. It can be removed, forming underfill of a certain thickness, protecting the package structure from external influences such as mechanical shock and corrosion of the joint, and minimizing the stress caused by thermal expansion coefficient difference between semiconductor chip and circuit board Serves to improve

3A through 3H, another cross-sectional view illustrating a method of manufacturing the semiconductor package illustrated in FIG. 1 is illustrated.

As shown in FIG. 3A, in the wafer preparation step S1, the first surface 111 that is approximately flat or completely flat, and the second surface 112 that is approximately flat or completely flat as an opposite surface of the first surface 111. At least one bond pad 115 is formed on the first surface 111, and a semiconductor die 110 having a passivation layer 116 having a predetermined thickness formed on an outer circumference of the bond pad 115. The wafer 100a is prepared. The passivation layer 116 may be formed of any one selected from conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide, nitride, and equivalents thereof. It does not limit the material. Of course, the nitride film or the oxide film may be formed by flowing silicon gas, nitrogen, silicon gas and oxygen, and the polyimide and epoxy may be formed by coating or spraying.

As shown in FIG. 3B, in the wafer bumping step S2, the conductive bumps 120 are formed on the bond pads 115 of the semiconductor die 110. The conductive bumps 120 are electrically connected to the bond pads 115. The conductive bumps 120 may be formed using any one of conventional ball drop, screen printing, electroplating, vacuum deposition, plating, and the like, and the method may be used. It is not limited. The conductive bumps 120 may be formed using any one selected from metal materials such as tin / lead (Pb / Sn) and leadless tin, and equivalents thereof, but the material is not limited thereto. .

As shown in FIG. 3C, in the wafer taping step S3, the tape 130 is attached to the passivation layer 116 and the conductive bump 120 of the semiconductor die 110. The tape 130 includes a semi-cured underfill 131, an adhesive 132, a backgrinding film 133, and a flux 134. The tape 130 is formed of a semi-cured underfill 131, a flux 134, an adhesive 132, and a backgrinding film 133, and the tape 130 is formed on the first die of the semiconductor die 110. The semi-cured underfill 131 is attached to the surface 111. The tape 130 is attached to the first surface 111 to grind the second surface 112 of the semiconductor die 110 in the wafer backgrinding step S4 to be described later, and the outer periphery of the tape 130. A ring may be formed in the tape 130, and the tape 130 protects the first surface of the semiconductor die 110 in the backgrinding step S4. Here, when the ring is formed, handling of the wafer 100 is facilitated. The semi-cured underfill 131 may be formed using any one selected from the underfill member and its equivalent in the form of a semi-cured film. In addition, the semi-cured underfill 131 is attached to the passivation layer 116 and the conductive bump 120 of the semiconductor die 110 in a semi-cured film form through heat treatment. In the case of welding the conductive bumps 120 through the reflow device can be completely cured. Here, the flux 134 cleans the surface of the conductive bump 120 during the process, prevents reoxidation, lowers the surface tension, and the like. The tape 130 is typically supplied with the tape 130 on the wafer (100a) and then the adhesive can be adhered by pushing the tape 130 with a roller, but the method is not limited thereto.

As shown in FIG. 3D, in the back grinding step S4, the second surface 112 of the semiconductor die 110 is ground by a predetermined thickness to remove unnecessary portions. Such a backgrinding process can be carried out using, for example, a diamond grinder and its equivalents, but is not limited thereto. In addition, in the back grinding step S4, the back grinding film 133 may prevent the interlayer insulating film, metal wire, etc. constituting the active layer formed on the first surface 111 of the semiconductor die 110 from being damaged. Play a role.

As shown in FIG. 3E, in the wafer detaping step S5, the first surface 111 of the semiconductor die 110 and the conductive bump 120 are formed in the wafer tapping step S3. The backgrinding film 133 is removed from the tape 130 attached to the tape 130. Of course, the tape 130 includes a semi-cured underfill 131, a flux 134, an adhesive 132, and a backgrinding film 133, and the adhesive 132 includes the flux 134 and the backgrinding. It is formed between the films (133). The adhesive 132 is more strongly bonded to the backgrinding film 133 than the portion bonded to the flux 134 so that the portion bonded to the flux 134 is removed when the backgrinding film 133 is removed. The adhesive 132 and the backgrinding film 133 are removed together. Therefore, only the semi-hardened underfill 131 and the flux 134 remain on the first surface 111 and the conductive bump 120 of the semiconductor die 110. Thus, after the semiconductor chip and the circuit board are electrically connected, the package structure is protected from external influences such as mechanical shock and corrosion of the joint, and the stress caused by the difference in thermal expansion coefficient difference between the semiconductor chip and the circuit board is minimized. A separate process for forming the underfill and the flux, which serves to improve the reliability, should be carried out, but in the present invention, since the underfill and the flux are already formed through the wafer taping step S3 and the wafer detapping step S5, the process There is an advantage in that the time and productivity are increased by shortening the time.

As shown in FIG. 3F, in the wafer sawing step S6, sawing from the wafer 100a to the individual semiconductor chips 100 is performed using a sawing tool 140 such as a diamond wheel or a laser beam. )do. For example, the sawing tool 140 is used to saw all of a predetermined area of the semiconductor die 110, the semi-cured underfill 131, and the flux 134, thereby separating the semiconductor chip 100 from the wafer 100a into individual semiconductor chips 100. Be sure to

As shown in FIG. 3G, in the semiconductor die attach step S7, the circuit board 200 may be transferred to the semiconductor chip 100 formed in the wafer sawing step S6 using a transfer member 300. Transfer to. In this case, the circuit board 200 has a flat first surface 220 and a flat second surface 230 as an opposite surface of the first surface 220, and at least one on the first surface 220. The first wiring pattern 221 may be formed, and the second surface 230 may be formed of an insulating layer 210 having at least one second wiring pattern 231 formed thereon. The first wiring pattern 221 and the second wiring pattern 231 may be electrically connected to conductive vias 240 formed in the insulating layer 210. A first solder mask 222 may be formed on an outer circumference of the first wiring pattern 221, and a second solder mask 232 may be formed on an outer circumference of the second wiring pattern 231. The semiconductor chip (eg, the transfer member 300) contacts the conductive bumps 120 of the semiconductor chip 100 to a region corresponding to the first wiring pattern 221 formed on the first surface 220 of the circuit board 200. 100 is transferred and seated on the circuit board 200. The transfer member 300 may be in close contact with the second surface 112 of the semiconductor chip 100 to absorb and transfer the semiconductor chip 100, but the method is not limited thereto. In addition, although the printed circuit board 200 is a hard printed circuit board as an example, a flexible printed circuit board or a lead frame may also be used.

As shown in FIG. 3H, in the reflow step S8, the conductive bumps 120 of the semiconductor chip 100 seated on the first wiring pattern 221 of the circuit board 200 are fixed. The conductive bumps 120 are welded and electrically connected to the first wiring patterns 221 of the circuit board 200 through the reflow apparatus having a temperature, and the semi-cured underfill 131 is also melted to form the semiconductor chip 100. ) And evenly distributed in the space between the circuit board 200 and the circuit board 200, and then completely cured to adhere to the semiconductor chip 100 and the circuit board 200. Of course, at this time, the flux 134 is volatilized and removed by the heat treatment of the reflow apparatus. Here, the flux 134 cleans the surface of the conductive bump 120 during the process, prevents reoxidation, lowers the surface tension, and the like. The semi-cured underfill 131 is cured hard enough to withstand the forces due to different thermal expansion coefficients of the semiconductor chip 100 and the circuit board 200. The reflow may be based on an infrared reflow, hot air reflow, infrared + hot air reflow, a latent heat of vaporization of an inert solvent, and an equivalent method thereof, but the present invention is not limited thereto.

The method of manufacturing the semiconductor package 2000 includes attaching a backgrinding film, a semi-cured underfill, and a flux to the semiconductor die together to protect the first surface of the semiconductor die during backgrinding, thereby removing the backgrinding film after the backgrinding process. Only the semi-hardened underfill and flux remain. Since it is possible to omit a separate liquid underfill filling process to be carried out in the future it is simplified compared to the conventional semiconductor package process to increase the productivity and work yield. In addition, since the semi-hardened underfill is attached to the film, the filler of the underfill is larger than the distance of the conductive bump when the conventional liquid underfill is injected, thereby preventing defects such as setting or voids. It can be removed, forming underfill of a certain thickness, protecting the package structure from external influences such as mechanical shock and corrosion of the joint, and minimizing the stress caused by thermal expansion coefficient difference between semiconductor chip and circuit board Serves to improve

What has been described above is just one embodiment for carrying out the method of manufacturing a semiconductor package according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

1 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

2A to 2H are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 1.

3A to 3H are still other cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 1.

<Description of Symbols for Main Parts of Drawings>

100a; Wafer 100; Semiconductor chip

110; Semiconductor die 120; Conductive bump

130; Tape 131; Semi-hardened underfill

132; Adhesive 133; Backgrinding Film

134; Flux 140; Sawing tool

200; Circuit board 300; Conveying member

1000; Semiconductor package

Claims (20)

A wafer preparation step of preparing a semiconductor die by forming a passivation layer on a bond pad and an outer circumference of the bond pad; A wafer bumping step of forming a conductive bump to be electrically connected to a bond pad of the semiconductor die; Attaching a tape including a semi-cured underfill and a backgrinding film to the semiconductor die and the conductive bumps; Grinding the opposite side of the semiconductor die on which the bond pad of the semiconductor die is formed; And And a wafer detapping step of removing the backgrinding film from the tape attached in the wafer taping step. The method of claim 1, wherein after the wafer detapping step And a sawing step of sawing the semiconductor die and the semi-cured underfill and separating the wafers into individual semiconductor chips. The method of claim 2, wherein after the wafer sawing step And a semiconductor chip attach step of attaching the semiconductor chip to a circuit board. The method of claim 3, wherein The circuit board has a first flat surface and a second flat surface opposite to the first surface, at least one first wiring pattern is formed on the first surface, and at least one first surface on the second surface. A method of manufacturing a semiconductor package, comprising an insulating layer having a double wiring pattern formed thereon. The method of claim 4, wherein And a first wiring pattern and a second wiring pattern of the circuit board are electrically connected to conductive vias formed in the insulating layer. The method of claim 4, wherein A first solder mask and a second solder mask are formed on the outer circumferences of the first wiring pattern and the second wiring pattern of the circuit board, respectively. The method of claim 3, wherein the semiconductor chip attach step is performed. And heat-treating the semiconductor chip and the circuit board to electrically connect conductive bumps of the semiconductor chip to the circuit board. The method of claim 7, wherein And in the reflowing step, the conductive bumps of the semiconductor chip and the wiring patterns formed on the circuit board are electrically connected to each other. The method of claim 7, wherein And in the reflow step, conductive bumps of the semiconductor chip are deposited on the wiring pattern formed on the circuit board, and the semi-cured underfill is completely cured. The method of claim 1, The tape attached to the semiconductor die and the conductive bump in the wafer taping step includes the semi-cured underfill and the backgrinding film, wherein the semi-cured underfill and the backgrinding film are bonded with an adhesive. Way. The method of claim 10, And the adhesive formed between the semi-cured underfill and the backgrinding film has a stronger adhesive force with the back-grinding film than with the semi-cured underfill. The method of claim 10, And the back grinding film and the adhesive are removed together with the adhesive in the wafer detapping step, wherein the adhesive portion is separated from the semi-cured underfill. The method of claim 1, The tape attached to the semiconductor die and the conductive bump in the wafer taping step includes the semi-cured underfill and the backgrinding film, and a flux is interposed between the semi-cured underfill and the backgrinding film. Method of manufacturing a semiconductor package. The method of claim 13, A method of manufacturing a semiconductor package, wherein an adhesive is interposed between the flux and the backgrinding film in the wafer taping step. The method of claim 14, Wherein the adhesion between the backgrinding film and the adhesive is stronger than the adhesion between the adhesive and the flux. The method of claim 14, And in the wafer detapping step, the adhesive adheres to the flux so that the backgrinding film and the adhesive are removed together. 17. The method of claim 16, wherein after the wafer detapping step And a sawing step of sawing the semiconductor die, the semi-cured underfill, and the flux and separating the semiconductor die into individual semiconductor chips from the wafer. 18. The method of claim 17, wherein after the wafer sawing step And a semiconductor chip attach step of attaching the semiconductor chip to a circuit board. 19. The method of claim 18, wherein after the semiconductor chip attach step And heat-treating the semiconductor chip and the circuit board to electrically connect conductive bumps of the semiconductor chip to the circuit board. The method of claim 19, And the flux is removed in the reflow step, the conductive bumps of the semiconductor die are deposited on a circuit board, and the semi-cured underfill is completely cured.

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