JP2013115336A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the bonding strength of a bump in a semiconductor device.SOLUTION: In bump bonding of a WPP (Wafer Process Package) 5, by forming a projection 1j projecting in a horizontal direction on each of columnar electrodes 1i to which bumps 6 are bonded, respectively, the bonding strength of the bumps 6 can be improved. Further, in assembly of the WPP 5, by arranging a resin 7 on an insulation film 1m so as to cover surfaces of the bumps 6 and grinding the resin 7 after curing the resin 7 to expose portions of the bumps 6, moisture-absorption resistance can be improved because the insulation film 1m composed of polyimide, for example, is covered with the resin 7.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having bump bonding.

  In a chip size package type semiconductor device, an insulating layer disposed on a flip chip connection surface of a semiconductor element, an element electrode covered at least in part by the insulating layer, and a locking means formed on the element electrode For example, Japanese Patent Laying-Open No. 2006-59917 (Patent Document 1) discloses a structure including a core bump provided with an external circuit connection bump that covers the core bump.

JP 2006-59917 A

  With the miniaturization of semiconductor devices, the external dimensions (for example, the size of the main surface) of the semiconductor chip tend to decrease. Therefore, for example, in a semiconductor device mounted via bumps (bump electrodes), the external dimensions of pads (surface electrodes, element electrodes) on which bumps are formed are also reduced. As a result, the bonding strength between the bump and the pad is lowered, and the bump is easily peeled (broken) from the pad.

  Note that, as in Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-59917), columnar electrodes (core bumps, conductors) having protrusions (locking means) protruding from the side surfaces are provided on the surface of the pads (element electrodes). By forming this, it is possible to give a bump anchor effect by the protruding portion of this electrode, but depending on the structure of the base of this electrode, the problem that the bonding strength of the bump cannot be sufficiently improved It became clear.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the bonding strength of bumps in a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment includes a semiconductor element formed on a main surface and a base material having a pad electrically connected to the semiconductor element, and electrically connected to the pad and made of copper. A first wiring, a second wiring formed on the first wiring, a second insulating film formed on the second wiring so that a first region of the second wiring is exposed, and the second wiring And a columnar electrode formed in the first region of the wiring. Further, a bump made of a tin-based material that is bonded to the surface of the electrode and the surface exposed from the electrode in the first region of the second wiring, and a part of the bump are exposed. A third insulating film formed on the second insulating film, and the first region of the second wiring is disposed at a position not overlapping the pad in plan view.

  Also, a method of manufacturing a semiconductor device according to a representative embodiment includes a semiconductor element formed on a main surface, a pad electrically connected to the semiconductor element, and formed on the main surface so that the pad is exposed. Preparing a base material having a first insulating film, forming a first wiring made of copper electrically connected to a pad on the first insulating film, and forming a second wiring having a first region in the first A step of forming on one wiring, and a step of forming a columnar electrode in the first region of the second wiring. Furthermore, a step of forming a second insulating film on the second wiring so that a part of the first region of the second wiring is exposed, the surface of the electrode, and the first region of the second wiring Forming a first bump made of a tin-based material so as to be bonded to the part; forming a third insulating film on the second insulating film so as to cover a surface of the first bump; The method includes a step of exposing a part of one bump, and the first region of the second wiring is arranged at a position that does not overlap the pad in plan view.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The bonding strength between the bump and the pad of the semiconductor device can be improved.

  In addition, the moisture absorption resistance of the semiconductor device can be improved.

It is a top view which permeate | transmits resin and shows an example of the wiring routing by the side of the main surface of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. FIG. 2 is a back view showing an example of the structure of the semiconductor device of FIG. 1. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary sectional view which shows an example of the grinding method in the terminal exposure grinding process of the assembly of the semiconductor device of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the mounting structure of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the shear test of the semiconductor device of Embodiment 1 of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 1 of Embodiment 1 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is a fragmentary sectional view which shows an example of the grinding method in the terminal exposure grinding process of the assembly of the semiconductor device of Embodiment 2 of this invention. It is the fragmentary sectional view and manufacturing flow figure which show an example of the main processes in the assembly of the semiconductor device of Embodiment 2 of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 1 of Embodiment 2 of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 2 of Embodiment 2 of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 2 of embodiment of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 3 of embodiment of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 4 of embodiment of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 5 of embodiment of this invention. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification 6 of embodiment of this invention.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing an example of wiring routing on the main surface side of the semiconductor device according to the first embodiment of the present invention through a resin, and FIG. 2 is an example of a structure cut along line AA in FIG. FIG. 3 is a back view showing an example of the structure of the semiconductor device of FIG.

  The semiconductor device according to the first embodiment shown in FIGS. 1 to 3 is a chip-sized semiconductor package called a WPP (Wafer Process Package) 5. The WPP 5 is also called a wafer level CSP (Chip Size Package) or the like, and is assembled by a manufacturing technique in which a wafer process and a package process are integrated.

  The configuration of the WPP 5 shown in FIGS. 1 to 3 will be described. Main surface (circuit forming surface) 1a, semiconductor element (semiconductor integrated circuit) 1n formed on main surface 1a, and pad electrically connected to semiconductor element 1n 1c and a semiconductor chip (base material, semiconductor substrate) 1 having a back surface 1b opposite to the main surface 1a, and the main surface 1a of the semiconductor chip 1 so that the surface of the pad 1c is exposed as shown in FIG. The formed insulating film (first insulating film, insulating layer) 1d, and rewiring (first wiring, lead-out) formed on the insulating film 1d and electrically connected to the pad 1c and made of copper (Cu) Wiring) 1f and upper layer wiring (second wiring) 1g formed on the rewiring 1f. The insulating film 1d is made of, for example, silicon nitride (SiN).

  Further, an insulating film (second insulating film, insulating layer) 1m formed on the upper layer wiring 1g so that the bump land (first region) 1h of FIG. 2 which is a bump forming region of the upper layer wiring 1g is exposed; Columnar electrodes (conductor, metal film, mushroom-type electrode) 1i formed on the bump land 1h of the upper layer wiring 1g, the surface of the electrode 1i, and the surface exposed from the electrode 1i of the bump land 1h of the upper layer wiring 1g. A bump (bump electrode) 6 made of a tin-based material and a resin (insulating layer, third insulating film) 7 formed on the insulating film 1m so that a part of the bump 6 is exposed are formed. Have. The insulating film 1m is made of polyimide, for example.

  Here, as shown in FIG. 2, the bump 6 includes a bump (first bump) 6a bonded to the columnar electrode 1i and a bump (second bump) 6b stacked on the bump 6a. Of these, the portion exposed to the outside from the resin (hereinafter also referred to as NCF) 7 is mainly the bump 6b. However, in the bump 6 provided as the external terminal of the WPP 5, when a sufficient amount of the bump 6a exposed from the NCF 7 is obtained, the bump 6b does not have to be stacked on the bump 6a. It is constituted only by the bump 6a.

  In addition, the rewiring 1f is a wiring that replaces the arrangement of each of the plurality of pads 1c with bump lands 1h, for example. Are placed in positions that do not overlap.

  Further, the semiconductor chip 1 of the WPP 5 has a peripheral pad arrangement in which a plurality of pads 1c are arranged along the outer peripheral portion as shown in FIG. 1, and each of the plurality of pads 1c is drawn inward by a rewiring 1f. Thus, a plurality of bumps 6 are provided in a matrix (for example, 3 columns × 4 rows) in an arrangement different from the arrangement of the plurality of pads 1c.

  As shown in FIG. 5, the upper layer wiring 1g is formed as a barrier layer on the rewiring 1f, and is a wiring layer made of, for example, nickel (Ni). Therefore, the columnar electrode (conductor) 1i shown in FIG. 6 formed on the bump land 1h of the upper layer wiring 1g is also made of the same nickel (Ni) as the upper layer wiring 1g.

  As shown in FIG. 2, the columnar electrode 1i has a protruding portion 1j (protruding portion, eaves) protruding (protruding) from the side surface of the electrode 1i in the horizontal direction (surface direction parallel to the surface of the electrode 1i). (In the first embodiment, the cross-sectional shape of the columnar electrode 1i is substantially T-shaped).

  The bumps 6 (bumps 6a and 6b) provided on the bump land 1h as external terminals are formed of a tin (Sn) -based solder material. In the first embodiment, for example, tin (Sn) and silver ( A so-called lead-free solder material made of an alloy of Ag) and copper (Cu) is used. The lead-free solder material means a lead (Pb) content of 1000 ppm (0.1 wt%) or less based on the RoHS (Restriction of Hazardous Substances) directive. In the case where a solder material containing tin (Sn) is used, since copper (Cu) is likely to diffuse, the first embodiment is not limited to the lead-free solder material, but lead (Pb). The present invention can also be applied when the contained solder material is used.

  NCF 7 is obtained by thermosetting a film-like (tape-like) resin, such as an epoxy resin.

  The semiconductor chip 1 is made of, for example, silicon, and the plurality of pads 1c formed on the main surface 1a are made of, for example, aluminum.

  As shown in FIG. 3, a mark 8 is attached to the back surface of the WPP 5 (the back surface 1b of the semiconductor chip 1). The mark 8 is, for example, an INDEX mark, a product name, a lot number, a management number, or a manufacturing country, but when the package size (chip size) does not have a size that allows the mark 8 to be attached. The mark 8 may not be attached.

  Next, assembly of the semiconductor device (WPP 5) according to the first embodiment shown in FIGS. 4 to 10 will be described.

  4 to 8 and FIG. 10 are a partial cross-sectional view and a manufacturing flow diagram showing an example of main steps in assembling the semiconductor device according to the first embodiment of the present invention, and FIG. 9 is a flowchart of the first embodiment according to the present invention. It is a fragmentary sectional view which shows an example of the grinding method in the terminal exposure grinding process of the assembly of a semiconductor device.

  First, “preparation of a preprocess wafer” shown in step S1 of FIG. 4 is performed. Here, main surface 1a, semiconductor element 1n formed on main surface 1a, pad 1c electrically connected to semiconductor element 1n, and insulating film (insulating layer) formed on main surface 1a so that pad 1c is exposed , A first insulating film) 1d and a wafer (semiconductor wafer, base material) 2 having a back surface 1b opposite to the main surface 1a are prepared. In the present embodiment, the insulating film 1d is made of, for example, silicon nitride (SiN).

  Thereafter, “seed layer formation” shown in step S2 is performed. That is, the seed layer 1e is formed on the entire surface by sputtering. This seed layer 1e is for use in a plating process to be described later.

  Thereafter, “resist (coating / exposure)” shown in step S3 is performed. Here, first, a resist film 4a is formed on the entire main surface 1a of the wafer 2 (specifically, on the seed layer 1e formed on the main surface 1a). Then, a predetermined portion (a portion where a wiring pattern is not formed) in the formed resist film 4a is covered with a mask 3. Thereafter, a portion not exposed by the mask 3 (a portion exposed from the opening of the mask 3) is exposed 3a.

  Thereafter, “resist formation (development)” shown in step S4 is performed. That is, by removing the exposed region 3a of the resist film 4a, the opening 4c of the resist film 4a from which the seed layer 1e is exposed is formed.

  Thereafter, “CuNi rewiring plating” shown in step S5 of FIG. 5 is performed. Here, first, the subsequent rewiring (wiring pattern, plating film) 1f is formed by electrolytic plating on the seed layer 1e exposed from the opening 4c of the resist film 4a formed in the previous step. Thereafter, an upper layer wiring (plating film) 1g which becomes a barrier layer of the rewiring 1f is formed on the rewiring 1f by an electrolytic plating method. In the present embodiment, the rewiring 1f is made of, for example, copper (Cu) or a metal containing copper (Cu) as a main component. On the other hand, the upper wiring 1g is made of nickel (Ni), for example. Further, the rewiring 1f has a bump land (rearrangement pad) 1h on which a bump (bump electrode) 6a is disposed (bonded) in a later step. In the present embodiment, the bump land 1h is arranged at a position that does not overlap the pad (original pad) 1c in plan view. That is, the rewiring 1 f is a wiring for replacing each arrangement (position) of the plurality of pads 1 c of the semiconductor chip 1 with another position. In the present embodiment, the case where the upper layer wiring 1g is formed on the entire upper surface of the rewiring 1f has been described. However, at least the rewiring 1f (exposed from the opening of the insulating film 1m formed in a later step) It may be formed in the area of the bump land 1h). However, when the rewiring 1f is made of copper (Cu) and the insulating film 1m disposed on the rewiring 1f is made of polyimide, the adhesion between the rewiring 1f and the insulating film 1m is made of nickel. In order to improve the reliability of the semiconductor device, the upper layer wiring 1g is formed on the entire upper surface of the rewiring 1f as in the present embodiment, since it is lower than the case where the upper layer wiring 1g is interposed. It is preferable to keep it.

  Thereafter, “resist removal” shown in step S6 is performed. That is, the resist film 4a remaining on the seed layer 1e is removed.

  Thereafter, “resist formation” shown in step S7 is performed. Here, a new resist film 4b is formed on the main surface 1a of the wafer 2 so that the bump land 1h in the rewiring 1f is exposed. Thereby, as shown in step S7 of FIG. 5, only the upper layer wiring 1g formed on the bump land 1h is exposed from the opening 4d of the resist film 4b.

  Thereafter, “electrolytic Ni post plating (mushroom type electrode)” shown in step S8 of FIG. 6 is performed. That is, an electrode (columnar electrode, mushroom electrode) 1i having a substantially T-shaped cross section is formed on the upper wiring 1g formed on the bump land 1h by an electrolytic plating method. In the present embodiment, the columnar electrode 1i is made of, for example, nickel (Ni). That is, in order to form a plating film made of the same metal as the upper layer wiring 1g, the formed electrode 1i and the upper layer wiring 1g are almost integrated, and the upper layer wiring 1g formed on the bump land 1h of the electrode 1i. It is possible to improve the adhesive strength against. In addition, the columnar electrode 1i in the present embodiment is formed by depositing a plating film on the upper wiring 1g exposed from the opening 4d of the resist film 4b. More specifically, a part of the electrode 1i is perpendicular to the opening 4d (see FIG. 5) of the resist film 4b formed on the rewiring 1f (specifically, on the upper layer wiring 1g formed on the rewiring 1f). A plating film is deposited (plating growth) until it protrudes (in the thickness direction of the wafer 2). Further, by depositing a plating film, the plating film overflowing from the opening 4d of the resist film 4b is plated and grown not only in the vertical direction but also in the horizontal direction (direction parallel to the main surface 1a of the wafer 2). . That is, in the present embodiment, the plating film is formed up to the place over the wall of the resist film 4b in the opening 4d.

  Thereafter, “resist / seed layer removal” shown in step S9 is performed. That is, the resist film 4b and the seed layer 1e are removed. Thereby, in a cross-sectional view, from the portion (side surface) located on the distal end surface (surface) side of the side surface of the columnar electrode 1i in the thickness direction of the electrode 1i, the horizontal direction (parallel to the surface of the electrode 1i). A columnar electrode 1i having a projecting portion 1j that protrudes (projects) in the surface direction) is formed.

  Thereafter, “insulating layer / electroless Au plating” shown in step S10 is performed. Here, first, the insulating film 1m is formed on the rewiring 1f (specifically, the upper layer wiring 1g formed on the rewiring 1f) so that a part of the bump land 1h (peripheral edge in plan view) is exposed. To do. That is, the insulating film 1m is formed so that the columnar electrode 1i and its periphery are exposed. In the present embodiment, the insulating film 1m is made of polyimide, for example. Then, after forming the insulating film 1m, a plating film 1k is further formed on the surface (including the tip and side surfaces) of the electrode 1i by electroless plating. In the present embodiment, the plating film 1k is made of, for example, gold (Au). By forming the plating film 1k in this manner, the wettability (solderability with the electrode) of the solder constituting the later bump can be improved. In addition to gold (Au), the plating film 1k may use palladium (Pd) or an alloy of palladium (Pd) and gold (Au).

  Thereafter, “solder material printing (ball mounting)” shown in step S11 of FIG. 7 is performed. Here, the solder material is bonded so as to be bonded to the surface (including the tip and side surfaces) of the electrode 1i and a part of the upper layer wiring 1g formed on the bump land 1h (location exposed from the insulating film 1m) by a printing method. 6c is supplied. Note that the solder material in the present embodiment has a lead (Pb) content based on a so-called lead-free solder material (RoHS (Restriction of Hazardous Substances) directive) that does not substantially contain, for example, tin (Sn). 1000 ppm (0.1 wt% or less), but is not limited thereto, and tin (Sn) or an alloy mainly composed of tin (Sn) may be used. At this time, as shown in step S11 of FIG. 7, the solder material 6c is also wound around the lower portion of the protruding portion 1j of the electrode 1i.

  Thereafter, “reflow bump formation / cleaning” shown in step S12 is performed. Here, the solder material 6c is melted by conveying the workpiece (structure) supplied with the solder material 6c to a reflow furnace. Thereafter, the molten solder material 6c is deformed into a substantially spherical shape due to the influence of the surface tension. Then, the temperature of the solder material 6c is lowered and solidified again, and the bump 6a is formed on the bump land 1h. Thereafter, the flux material remaining in the vicinity of the bump 6a or the bump 6a is cleaned using a cleaning liquid.

  After that, “insulating material (NCF etc.) formation” shown in step S13 of FIG. 8 is performed. Here, a case where an insulating and film-like (tape-like) resin 7 containing no conductive particles called NCF (Non Conductive Film) is used will be described. First, the resin 7 is disposed on the insulating film 1m so as to cover the bumps 6a.

  Thereafter, “curing baking”, that is, baking processing shown in step S14 is performed. In this step, the resin 7 is heated and melted. The molten resin 7 adheres to the surfaces of the insulating film 1m and the bumps 6a. Thereafter, the melted resin 7 is cured to form the resin (resin layer) 7 on the insulating film 1m so as to cover the surface of the bump 6a (the surface exposed from the insulating film 1m).

  Thereafter, “terminal exposure grinding” shown in step S15 is performed, and a part (tip portion) of the bump 6a is exposed from the resin 7. In this grinding step, as shown in FIG. 9, a part of the resin 7 and a part of the bump 6a are ground (bite grinding) using a cutting tool 9, and one bump 6a is formed from the resin (resin layer) 7. Expose the part. Here, as other grinding means, there is polishing by chemical and mechanical action, so-called CMP (Chemical Mechanical Polishing), but in this step S15, two types of insulating material and metal, in other words, insulating material or Since only one type of metal is not polished, it is preferable to employ a bite grinding using a bite 9. Thereby, the mounting surface of WPP5 can be planarized. In the above-described bite grinding, it is preferable to perform grinding so that the film of the bump 6a remains on the electrode 1i as shown in step S15 of FIG. Thereby, it is not necessary to manage the state of the surface (metal surface) of the electrode 1i, and the management of the state of the surface (metal surface) of the electrode 1i can be omitted. However, it goes without saying that the surface of the electrode 1i may be exposed. Furthermore, after grinding, a reflow process may be further performed so that the bumps 6 a protrude from the surface of the resin 7.

  Through the above steps, the main manufacturing process of the semiconductor device having bumps is completed. However, as described above, in this embodiment, since a part of the solder material constituting the bump 6a is removed, when the amount of solder necessary for mounting the semiconductor device cannot be secured, The bump addition process shown in FIG. 10 may be performed after the step “terminal exposure grinding”. Thereby, it is possible to improve the connection height of solder. This step S16 will be described below.

  First, the bump 6b made of the same material as the material of the bump 6a is disposed on the exposed part (surface) of the bump 6a from the insulating film 1m by bite grinding. At this time, the bump 6b is disposed on the exposed surface of the bump 6a through the flux (adhesive) 10.

  Thereafter, “reflow bump formation / cleaning” shown in step S17 is performed. Here, the bump (6a) and the bump (6b) are melted by conveying the work (structure) supplied with the bump (6b) to a reflow furnace. Thereby, the melted bump 6a and the bump 6b are integrated. Then, the integrated bump tends to be deformed into a substantially spherical shape due to the influence of surface tension. However, in this embodiment, since the opening diameter of the resin 7 is smaller than the diameter of the bump 6a, the process proceeds to step S17 in FIG. As shown, it becomes a gourd. And the temperature of the solder material 6c falls, it solidifies again, and the bump 6 which protruded from the surface of the resin 7 is formed. Thereafter, the flux material remaining in the vicinity of the bump 6 or the bump 6 is cleaned using a cleaning liquid.

  Thus, by stacking the bumps 6b on the bumps 6a, the solder amount of the bumps 6 that are external terminals of the WPP 5 can be sufficiently increased, and the connection strength (mounting strength) in solder connection can be improved.

  In “flux supply / ball mounting” shown in step S16, solder may be supplied by a paste printing method.

  Thereafter, the wafer 2 is separated into individual packages by dicing, and the assembly of the WPP 5 is completed. Thereafter, the WPP 5 is transported to another process for testing and further shipping.

  In the WPP 5 (semiconductor device) of the first embodiment, in the bump bonding, the protrusion 1j that protrudes in the horizontal direction is formed on the columnar electrode 1i to which the bump 6 is bonded (mushroom type electrode). 6 can have an anchor effect, and the bonding strength of the bump 6 can be improved.

  In WPP5, an upper layer wiring 1g made of nickel (Ni) is formed as a barrier layer on the rewiring 1f made of copper (Cu), and the columnar electrode 1i connected to the bump land 1h of the upper layer wiring 1g is also nickel. By comprising, the area | region where a solder directly touches copper (Cu) can be eliminated.

  In other words, when copper and solder are in direct contact with each other, there is a problem that when copper is applied with heat, copper moves into the solder and the copper itself breaks down. However, as with WPP 5 in the first embodiment, By eliminating the area where the solder directly contacts copper (Cu), copper erosion can be prevented or reduced.

  Further, a resin 7 is disposed on the insulating film 1m so as to cover the surface of the bump 6a, and after the resin 7 is cured, the resin 7 is ground to expose the bump 6a, thereby, for example, an insulating film made of polyimide. 1 m can be covered with the resin 7, and moisture intrusion (penetration) can be suppressed. That is, the moisture absorption resistance of WPP5 can be improved.

  Next, the thinning (downsizing) of WPP 5 will be described. When the WPP 5 is thinned, the back side of the wafer (base material) 2 is ground in the wafer state before the singulation process for the package.

  That is, after the formation of the rewiring 1f in step S5 in FIG. 5, after the “terminal exposure grinding” in step S15 in FIG. 8 and before the “flux supply / ball mounting process” in step S16 in FIG. After the “reflow bump formation / cleaning step” in step S17, the back surface of the wafer 2 can be ground (back grind (BG)) to make the WPP 5 thinner.

  In addition, when the thickness of the semiconductor chip 1 (wafer 2) is reduced by the above-described BG process, a problem of warping of the semiconductor chip 1 occurs. That is, the semiconductor chip 1 is thinned by the BG, and as a result, the rigidity of the semiconductor chip 1 is lowered, so that warpage is likely to occur.

  Therefore, the warp of the semiconductor chip 1 (wafer 2) can be reduced by reducing the thickness of the copper (Cu) rewiring 1f of the WPP 5 of the first embodiment as a countermeasure against the warp of the semiconductor chip 1. .

  That is, by thinning the rewiring 1f made of copper (Cu) in the WPP 5 as much as possible, the balance of rigidity in the WPP 5 body can be maintained even when the thickness of the semiconductor chip 1 is reduced in the BG process. Thus, the warpage of the semiconductor chip 1 can be reduced.

  Further, in the transportation and shipment of the WPP 5 after assembly, vibration and impact may be applied to the WPP 5, but in the WPP 5 of the first embodiment, in the bump bonding, the columnar electrode 1 i to which the bump 6 is bonded, By forming the protruding portion 1j that protrudes in the horizontal direction (mushroom-type electrode), the bump 6 has an anchor effect to improve the bonding strength of the bump 6, so even if vibration or impact is applied. The occurrence of defective bonding of the bumps 6 can be prevented or reduced.

  Next, FIGS. 11 and 12 will be described. FIG. 11 is a cross-sectional view showing an example of the mounting structure of the semiconductor device according to the first embodiment of the present invention, and FIG. 12 is a cross-sectional view showing an example of the shear test of the semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 11, the assembled WPP 5 is solder-mounted on a mounting board such as a mother board 11, for example. At this time, each bump 6 of the WPP 5 is soldered to the corresponding terminal 11a of the mother board 11. At that time, since the reflow process is performed through a reflow furnace, thermal stress is also applied to the bump bonding portion by heating. In the WPP 5 of the first embodiment, the columnar electrode 1i bonded to the bump 6 is horizontally aligned Since the protruding portion 1j protruding in the direction is formed and the anchoring effect is given to the bump 6 to improve the bonding strength of the bump 6, it is possible to prevent the bonding failure of the bump 6 from occurring. That is, even when stress concentrates on the bump bonding portion due to expansion / contraction due to heat, the columnar electrode 1i has the protruding portion 1j in the horizontal direction, thereby preventing peeling at the interface of the bump 6. be able to.

  In the WPP 5 of the first embodiment, since the resin (resin layer) 7 is formed on the insulating film 1m, the main surface (circuit forming surface) 1a of the semiconductor chip 1 can be protected from mechanical shock. Intrusion of light into the main surface 1a can also be suppressed.

  FIG. 12 illustrates a method of a shear strength test, and the assembled WPP 5 is inspected by sampling. That is, a load is applied to the bump 6 from the pressing member 12 in the direction P along the main surface 1a of the semiconductor chip 1 to the bump 6 of the WPP 5 to inspect the shear strength of the bump 6.

  In the WPP 5 according to the first embodiment, as described above, the columnar electrode 1i joined to the bump 6 is formed with the protruding portion 1j that protrudes in the horizontal direction. Therefore, even in the shear strength test of the bump 6, the number of occurrences of the bonding failure of the bump 6 can be reduced, and the result that the bonding failure is difficult can be obtained.

  In the first embodiment, the method of arranging the solder material 6c in the bump land 1h (bump formation region) in step S11 of FIG. The solder placement method may be a ball supply method using a flux material or a ball supply method by laser melting. In the printing method, since the columnar electrode 1i (conductor) has the protruding portion 1j, it is easy to place solder in the lower portion of the protruding portion 1j (more reliably, the solder can wrap around the lower portion of the protruding portion 1j). However, the ball supply method is preferable in that the amount of the solder material 6c constituting each bump 6 is made uniform.

  In the first embodiment, the case where NCF is adopted as the insulating film formed on the insulating film 1m on the rewiring 1f of the WPP 5 has been described. However, the insulating film on the insulating film 1m is made of NCP (Non Conductive). Paste, paste-like resin, mold type) or a liquid material by spin coating may be used, and even when NCP or spin coating material is employed, the same effect as in the case of resin can be obtained.

  NCP is, for example, a liquid epoxy resin. On the other hand, the spin coat material is, for example, a flux resin that reacts with an epoxy resin or the like, a polyimide resin, or an epoxy resin.

  Next, a modification of the first embodiment will be described.

  FIG. 13 is a partial cross-sectional view showing the structure of the semiconductor device of Modification 1 of Embodiment 1 of the present invention.

  In the WPP 5, when the thickness of the semiconductor chip 1 (particularly, the base material (semiconductor substrate)) is relatively large (thick), it is not necessary to form the upper layer wiring 1g that is a barrier layer on the rewiring 1f. . However, when the upper layer wiring 1g (barrier layer) is not formed, the thickness Q of the rewiring 1f made of copper (Cu) and the thickness R of the protruding portion 1j of the columnar electrode 1i are implemented in order to withstand copper erosion. Must be larger than the first form (WPP 5 shown in FIGS. 8 and 10). Therefore, when considering the thinning of the WPP 5, it is preferable to form a barrier layer (upper layer wiring 1g) as in the first embodiment, for example.

  In addition, in WPP5 of the modification 1 of FIG. 13, the columnar electrode (conductor) 1i is formed with copper. Copper (Cu) has a lower electrical resistance than nickel (Ni).

  Therefore, in the WPP 5 of FIG. 13, since the electrode 1i is made of copper, the electric resistance can be made smaller than in the case of being made of nickel, and the electrical characteristics of the WPP 5 can be improved.

(Embodiment 2)
14 to 18 and FIG. 20 are a partial cross-sectional view and a manufacturing flow diagram showing an example of main steps in the assembly of the semiconductor device of the second embodiment of the present invention, respectively, and FIG. 19 is a diagram of the second embodiment of the present invention. It is a fragmentary sectional view which shows an example of the grinding method in the terminal exposure grinding process of the assembly of a semiconductor device.

  In the second embodiment, the assembly of the WPP 5 will be described. The difference between the WPP 5 in the second embodiment and the WPP 5 in the first embodiment is that the redistribution line 1f is different in the WPP 5 in the second embodiment. The upper layer wiring 1g as in the first embodiment is not formed above. Instead of the upper layer wiring 1g, a UBM (Under Bump) is provided immediately below the columnar electrode (conductor, metal film, mushroom type electrode) 1i. Metal) 1p is formed as a barrier layer (second wiring). That is, in the second embodiment, the UBM 1p is formed in place of the upper wiring 1g of the first embodiment as a barrier layer against the erosion of the rewiring 1f made of copper.

  In the WPP 5 of the second embodiment, a case where the columnar electrode 1i is mainly made of copper (Cu) will be described.

  UBM1p is formed by sputtering + plating or sputtering alone. When formed by sputtering, for example, Ti / Cu, TiN / Ti / Cu, W / Cu, Cr / Cu, etc. are formed by plating. For example, Cu, Ni / Au, Cu / Ni / Au, Cu / Ni / Pd / Au, etc. In the case of forming only by sputtering, for example, Cu / Ni / Au, Cu / Ni / Pd / Au, or the like.

  Next, assembly of the WPP 5 of the second embodiment will be described.

  First, “preparation of a preprocess wafer” shown in step S21 of FIG. 14 is performed. Here, main surface 1a, semiconductor element 1n formed on main surface 1a, pad 1c electrically connected to semiconductor element 1n, and insulating film (insulating layer) formed on main surface 1a so that pad 1c is exposed , A first insulating film) 1d and a wafer (semiconductor wafer, base material) 2 having a back surface 1b opposite to the main surface 1a are prepared. In the present embodiment, the insulating film 1d is made of, for example, silicon nitride (SiN).

  Thereafter, “seed layer formation” shown in step S22 is performed. That is, the seed layer 1e is formed on the entire surface by sputtering. This seed layer 1e is for use in a plating process to be described later.

  Thereafter, “resist (coating / exposure)” shown in step S23 is performed. Here, first, a resist film 4a is formed on the entire main surface 1a of the wafer 2 (specifically, on the seed layer 1e formed on the main surface 1a). Then, a predetermined portion (a portion where a wiring pattern is not formed) in the formed resist film 4a is covered with a mask 3. Thereafter, a portion not exposed by the mask 3 (a portion exposed from the opening of the mask 3) is exposed 3a.

  Thereafter, “resist formation (development)” shown in step S24 is performed. That is, by removing the exposed region 3a of the resist film 4a, the opening 4c of the resist film 4a from which the seed layer 1e is exposed is formed.

  Thereafter, “Cu rewiring plating” shown in step S25 of FIG. 15 is performed. Here, first, the subsequent rewiring (wiring pattern, plating film) 1f is formed by electrolytic plating on the seed layer 1e exposed from the opening 4c of the resist film 4a formed in the previous step. In the present embodiment, the rewiring 1f is made of, for example, copper (Cu) or a metal containing copper (Cu) as a main component.

  Thereafter, "resist / seed layer removal" shown in step S26 is performed. That is, the seed layer 1e around the rewiring 1f and the resist film 4a remaining on the seed layer 1e are removed.

  Thereafter, “insulating layer / seed layer formation” shown in step S27 is performed. Here, first, an insulating film (insulating layer, second insulating film) 1m is formed on the rewiring 1f with an area corresponding to the bump land 1h as an opening 4d, and after the insulating film 1m is formed, on the insulating film 1m, A seed layer 1q is formed on the rewiring 1f exposed in the opening 4d. In the present embodiment, the insulating film 1m is made of polyimide, for example.

  Note that the seed layer 1q formed on the rewiring 1f of the opening 4d becomes the UBM 1p in FIG. That is, the seed layer 1q has a UBM 1p that becomes a bump land 1h on which the bump 6a (see FIG. 17) is arranged. The bump land 1h (UBM1p) is in a plan view with the pad (original pad) 1c. It is arranged in a position that does not overlap. That is, the rewiring 1 f is a wiring for replacing each arrangement (position) of the plurality of pads 1 c of the semiconductor chip 1 with another position.

  Thereafter, “resist formation” shown in step S28 of FIG. 16 is performed. Here, a new resist film 4b is formed so that only the region of UBM 1p in seed layer 1q is exposed to opening 4d.

  Thereafter, “Cu post plating (mushroom type electrode)” shown in step S29 is performed. That is, an electrode (columnar electrode, mushroom electrode) 1i having a substantially T-shaped cross section is formed on the UBM 1p by copper (Cu) plating. The columnar electrode 1i in the present embodiment is formed by depositing copper plating on the UBM 1p exposed from the opening 4d of the resist film 4b. More specifically, a copper plating film is deposited (plating growth) until a part of the electrode 1i protrudes in the vertical direction (thickness direction of the wafer 2) from the opening 4d of the resist film 4b formed on the seed layer 1q. Let Further, by depositing a copper plating film, the plating film overflowing from the opening 4d of the resist film 4b is grown not only in the vertical direction but also in the horizontal direction (direction parallel to the main surface 1a of the wafer 2). To do. That is, in the present embodiment, the copper plating film is formed up to the place over the wall of the resist film 4b in the opening 4d.

  Thereafter, “resist / seed layer removal” shown in step S30 is performed. That is, the resist film 4b and the seed layer 1q on the insulating film 1m are removed. Thereby, in a cross-sectional view, from the portion (side surface) located on the distal end surface (surface) side of the side surface of the columnar electrode 1i in the thickness direction of the electrode 1i, the horizontal direction (parallel to the surface of the electrode 1i). A columnar electrode 1i having a projecting portion 1j that protrudes (projects) in the surface direction) is formed.

  After that, “solder material printing (ball mounting)” shown in step S31 of FIG. 17 is performed. Here, the solder material 6c is supplied so as to be bonded to the surface (including the tip surface and the side surface) of the electrode 1i by a printing method. Note that the solder material in the present embodiment has a lead (Pb) content based on a so-called lead-free solder material (RoHS (Restriction of Hazardous Substances) directive) that does not substantially contain, for example, tin (Sn). 1000 ppm (0.1 wt% or less), but is not limited thereto, and tin (Sn) or an alloy mainly composed of tin (Sn) may be used. At this time, as shown in step S31 of FIG. 17, the solder material 6c is also wound around the lower portion of the protruding portion 1j of the electrode 1i.

  Thereafter, “reflow bump formation / cleaning” shown in step S32 is performed. Here, the solder material 6c is melted by conveying the workpiece (structure) supplied with the solder material 6c to a reflow furnace. Thereafter, the molten solder material 6c is deformed into a substantially spherical shape due to the influence of the surface tension. And the temperature of the solder material 6c falls, it solidifies again, and the bump 6a joined to the electrode 1i is formed. Thereafter, the flux material remaining in the vicinity of the bump 6a or the bump 6a is cleaned using a cleaning liquid.

  After that, “insulating material (NCF etc.) formation” shown in step S33 of FIG. 18 is performed. Here, a case where an insulating and film-like (tape-like) resin 7 containing no conductive particles called NCF (Non Conductive Film) is used will be described. First, the resin 7 is disposed on the insulating film 1m so as to cover the bumps 6a.

  Thereafter, “curing baking”, that is, baking processing shown in step S34 is performed. In this step, the resin 7 is heated and melted. The molten resin 7 adheres to the surfaces of the insulating film 1m and the bumps 6a. Thereafter, the melted resin 7 is cured to form the resin (resin layer) 7 on the insulating film 1m so as to cover the surface of the bump 6a (the surface exposed from the insulating film 1m).

  Thereafter, “terminal exposure grinding” shown in step S <b> 35 is performed to expose a part (tip portion) of the bump 6 a from the resin 7. In this grinding step, as in the case of the first embodiment, as shown in FIG. 19, a part of the resin 7 and a part of the bump 6a are ground (bite grinding) using a cutting tool 9, and the resin A part of the bump 6 a is exposed from the (resin layer) 7. Here, as another grinding means, there is polishing by chemical and mechanical action, so-called CMP (Chemical Mechanical Polishing). In this step S35, two types of insulating material and metal, in other words, insulating material or Since only one type of metal is not polished, it is preferable to employ a bite grinding using a bite 9. Thereby, the mounting surface of WPP5 can be planarized. Further, in the above-described bite grinding, it is preferable to perform grinding so that the film of the bump 6a remains on the electrode 1i as shown in step S35 of FIG. Thereby, it is not necessary to manage the state of the surface (metal surface) of the electrode 1i, and the management of the state of the surface (metal surface) of the electrode 1i can be omitted. However, it goes without saying that the surface of the electrode 1i may be exposed. Furthermore, after grinding, a reflow process may be further performed so that the bumps 6 a protrude from the surface of the resin 7.

  Through the above steps, the main manufacturing process of the semiconductor device having bumps is completed. However, as described above, even in the second embodiment, since a part of the solder material constituting the bump 6a is removed, when the amount of solder necessary for mounting the semiconductor device cannot be secured, After the step “terminal exposure grinding”, a bump addition process shown in FIG. 20 may be performed. Thereby, it is possible to improve the connection height of solder. This step S36 will be described below.

  First, the bump 6b made of the same material as the material of the bump 6a is disposed on the exposed part (surface) of the bump 6a from the insulating film 1m by bite grinding. At this time, the bump 6b is disposed on the exposed surface of the bump 6a through the flux (adhesive) 10.

  Thereafter, “reflow bump formation / cleaning” shown in step S37 is performed. Here, the bump (6a) and the bump (6b) are melted by conveying the work (structure) supplied with the bump (6b) to a reflow furnace. Thereby, the melted bump 6a and the bump 6b are integrated. Then, the integrated bump tends to be deformed into a substantially spherical shape due to the influence of the surface tension, but also in the second embodiment, since the opening diameter of the resin 7 is smaller than the diameter of the bump 6a, step S37 in FIG. As shown in the figure, it becomes a gourd. And the temperature of the solder material 6c falls, it solidifies again, and the bump 6 which protruded from the surface of the resin 7 is formed. Thereafter, the flux material remaining in the vicinity of the bump 6 or the bump 6 is cleaned using a cleaning liquid.

  Thus, by stacking the bumps 6b on the bumps 6a, the solder amount of the bumps 6 that are external terminals of the WPP 5 can be sufficiently increased, and the connection strength (mounting strength) in solder connection can be improved.

  In “flux supply / ball mounting” shown in step S36, solder may be supplied by a paste printing method.

  Thereafter, the wafer 2 is separated into individual packages by dicing, and the assembly of the WPP 5 is completed. Thereafter, the WPP 5 is transported to another process for testing and further shipping.

  Also in the WPP 5 (semiconductor device) of the second embodiment, similarly to the WPP 5 of the first embodiment, in the bump bonding, a protruding portion 1j protruding in the horizontal direction is formed on the columnar electrode 1i to which the bump 6 is bonded. As a result (mushroom-type electrode), the anchor effect can be given to the bump 6 and the bonding strength of the bump 6 can be improved.

  Further, in the WPP 5 of the second embodiment, the UBM 1p is formed as a barrier layer on the rewiring 1f made of copper (Cu) and immediately below the columnar electrode 1i, so that, similarly to the WPP 5 of the first embodiment, It is possible to eliminate an area where the solder directly contacts copper (Cu).

  In other words, when copper and solder are in direct contact, there is a problem that when heat is applied, the copper moves into the solder and the copper itself breaks down. Even in the WPP 5 of the second embodiment, the solder By eliminating the region in which copper directly touches copper (Cu), copper erosion can be prevented or reduced.

  Further, a resin 7 is disposed on the insulating film 1m so as to cover the surface of the bump 6a, and after the resin 7 is cured, the resin 7 is ground to expose the bump 6a, thereby, for example, an insulating film made of polyimide. 1 m can be covered with the resin 7, and moisture intrusion (penetration) can be suppressed. That is, the moisture absorption resistance of WPP 5 can be improved as in the first embodiment.

  Next, the thinning (downsizing) of WPP 5 will be described. When thinning the WPP 5 of the second embodiment, the back surface side of the wafer (base material) 2 is ground in the wafer state before the singulation processing into the package as in the first embodiment. .

  That is, after the formation of the rewiring 1f in step S25 in FIG. 15, after the “terminal exposure grinding” in step S35 in FIG. 18 and before the “flux supply / ball mounting process” in step S36 in FIG. After the “reflow bump formation / cleaning step” in step S37, the back surface of the wafer 2 can be ground (back grind (BG)) to make the WPP 5 thinner.

  In addition, when the thickness of the semiconductor chip 1 (wafer 2) is reduced by the above-described BG process, a problem of warping of the semiconductor chip 1 occurs. That is, the semiconductor chip 1 is thinned by the BG, and as a result, the rigidity of the semiconductor chip 1 is lowered, so that warpage is likely to occur.

  Therefore, as a countermeasure against warping of the semiconductor chip 1, also in the WPP 5 of the second embodiment, the warp of the semiconductor chip 1 (wafer 2) is reduced by thinning the copper (Cu) rewiring 1f. be able to.

  That is, by thinning the rewiring 1f made of copper (Cu) in the WPP 5 as much as possible, the balance of rigidity in the WPP 5 body can be maintained even when the thickness of the semiconductor chip 1 is reduced in the BG process. Thus, the warpage of the semiconductor chip 1 can be reduced.

  Further, in the transportation and shipment of the WPP 5 after assembly, vibration and impact may be applied to the WPP 5, but also in the WPP 5 of the second embodiment, in the bump bonding, the columnar electrode 1i to which the bump 6 is bonded is applied. Since the protruding portion 1j that protrudes in the horizontal direction (mushroom-type electrode) is formed, the anchoring effect is given to the bump 6 to improve the bonding strength of the bump 6, so that vibration and impact are applied. In addition, it is possible to prevent or reduce the occurrence of defective bonding of the bumps 6.

  Next, also in the WPP 5 of the second embodiment, the same effect as that of the WPP 5 of the first embodiment can be obtained at the time of mounting on a mounting board or in a shear strength test.

  That is, the WPP 5 of the second embodiment is also solder-mounted on a mounting board such as the mother board 11 as shown in FIG. At this time, each bump 6 of the WPP 5 is soldered to the corresponding terminal 11a of the mother board 11. At that time, in order to perform the reflow process through a reflow furnace, thermal stress is also applied to the bump bonding portion by heating. In the WPP 5 of the second embodiment, the columnar electrode 1i bonded to the bump 6 Since the protruding portion 1j protruding in the horizontal direction is formed and the bonding strength of the bump 6 is improved by giving an anchor effect to the bump 6, it is possible to prevent the bonding failure of the bump 6 from occurring. That is, even when stress concentrates on the bump bonding portion due to expansion / contraction due to heat, the columnar electrode 1i has the protruding portion 1j in the horizontal direction, thereby preventing peeling at the interface of the bump 6. be able to.

  Also in the WPP 5 of the second embodiment, since the resin (resin layer) 7 is formed on the insulating film 1m, the main surface (circuit forming surface) 1a of the semiconductor chip 1 is protected from mechanical shock. In addition, the penetration of light into the main surface 1a can be suppressed.

  Also in the shear strength test shown in FIG. 12, the WPP 5 of the second embodiment is similar to the WPP 5 of the first embodiment in that the columnar electrode 1i joined to the bump 6 has a protruding portion 1j protruding in the horizontal direction. Since the bonding strength of the bump 6 is improved by giving an anchor effect to the bump 6, the number of occurrences of defective bonding of the bump 6 is reduced in the shear strength test of the bump 6. The result that it is hard to be defective can be obtained.

  Also in the second embodiment, the method of arranging by the printing method when placing the solder material 6c on the columnar electrode 1i in step S31 of FIG. 17 has been described. However, the arrangement of the solder on the electrode 1i is described. The method may be a ball supply method using a flux material or a ball supply method by laser melting. In the printing method, since the columnar electrode 1i (conductor) has the protruding portion 1j, it is easy to place solder in the lower portion of the protruding portion 1j (more reliably, the solder can wrap around the lower portion of the protruding portion 1j). However, the ball supply method is preferable in that the amount of the solder material 6c constituting each bump 6 is made uniform.

  In the second embodiment, the case where NCF is used as the insulating film formed on the insulating film 1m on the rewiring 1f of the WPP 5 has been described. However, the insulating film on the insulating film 1m is made of NCP (Non Conductive Paste, paste-like resin, mold type) or a liquid material by spin coating may be used, and even when NCP or spin coating material is adopted, the same effect as in the case of resin can be obtained.

  NCP is, for example, a liquid epoxy resin. On the other hand, the spin coat material is, for example, a flux resin that reacts with an epoxy resin or the like, a polyimide resin, or an epoxy resin.

  Next, a modification of the second embodiment will be described.

  21 is a partial cross-sectional view showing the structure of a semiconductor device according to Modification 1 of Embodiment 2 of the present invention, and FIG. 22 is a partial cross-sectional view showing the structure of a semiconductor device according to Modification 2 of Embodiment 2 of the present invention. is there.

  In Modification 1 of FIG. 21, an electrode (conductor, metal film, mushroom electrode) 1i on the UBM 1p of the WPP 5 of the present embodiment is formed of nickel (Ni). Thus, by forming the electrode 1i with nickel (Ni), the problem of copper (Cu) diffusing into the bumps 6b formed of a tin (Sn) solder material as described above can be suppressed. That is, erosion of the electrode 1i can be suppressed. However, with respect to electrical resistance, nickel (Ni) is larger than copper (Cu). Therefore, in order to improve electrical characteristics, copper (Cu) is used as in the first and second embodiments. It is preferable to form the electrode 1i using.

  Accordingly, in Modification 2 shown in FIG. 22, the electrode 1i on the UBM 1p has a two-layer structure of nickel (upper layer side) and copper (UBM side). That is, by forming the electrode 1i by a plating method, the formation of the nickel portion can be accelerated, and the electrical resistance can be reduced in the copper portion. That is, the assembly throughput of the WPP 5 can be increased and the electrical characteristics can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

(Modification 1)
For example, in the first and second embodiments, the rewiring 1f, the upper wiring 1g, and the electrode 1i are formed by the electrolytic plating method. However, the present invention is not limited to this, and an electroless plating method is used. May be formed. In this case, the seed layer 1e is not necessary.

(Modification 2)
For example, in the first and second embodiments, the case where only the SiN film 1d is formed as the insulating film in the lower layer of the rewiring 1f has been described. However, FIG. 23 (Modification 2) and FIG. As shown in Example 3), in addition to the insulating film (silicon nitride film) 1d, another insulating film (polyimide film, insulating layer, fourth insulating film) 1r may be formed below the rewiring 1f.

  23, in the WPP 5 in which the barrier layer described in the first embodiment is the upper wiring 1g made of nickel and the columnar electrode 1i is also made of nickel, the insulating film 1d is added to the lower layer of the rewiring 1f. In this case, another insulating film 1r is formed.

  In this way, by forming another insulating film 1r in addition to the insulating film 1d in the lower layer of the rewiring 1f in the WPP 5, damage to the lower layer of the rewiring 1f layer can be alleviated. In the structure of FIG. 23, the same effect can be obtained when the columnar electrode 1i is made of copper.

(Modification 3)
Further, in Modification 3 of FIG. 24, in the WPP 5 in which the barrier layer described in the second embodiment is the UBM 1p and the columnar electrode 1i is made of copper, in addition to the insulating film 1d, a layer other than the insulating film 1d is added. This is a case where the insulating film 1r is formed.

  Similarly to Modification 2 of FIG. 23 described above, even in the WPP 5 having the barrier layer UBM1p, by forming another insulating film 1r in addition to the insulating film 1d below the rewiring 1f, the rewiring 1f layer Damage to the lower layer of can be mitigated. In the structure of FIG. 24, the same effect can be obtained when the columnar electrode 1i is made of nickel.

(Modification 4)
In the first and second embodiments, the case where the bump 6 formed as the external terminal of the WPP 5 is made only of solder has been described. However, the bump 6 is added as shown in FIG. 25 (Modification 4). The core ball 6d may be provided inside the bump 6b joined in step (b).

  That is, when a part of the bump 6a is exposed by grinding an insulating film such as NCF7 or NCP and then a solder material to be additionally arranged is supplied by a ball supply method, as in Modification 4 of FIG. The bump 6 is composed of a bump 6a bonded to the columnar electrode 1i and a bump 6b laminated (added) on the bump 6a. At this time, a bump 6b (solder ball) having a core ball 6d provided therein is adopted. To do. The core ball 6d is preferably formed of, for example, copper or resin.

  Since the bump 6 has the core ball 6d inside as described above, the core ball 6d absorbs the stress due to the heat change, so that the temperature cycle performance can be improved.

(Modification 5)
In the first and second embodiments, the case where one rewiring 1f is electrically connected to one pad (original pad) 1c has been described. However, the present invention is not limited to this. For example, FIG. As shown, a plurality of pads (original pads) 1c may be electrically connected to one rewiring 1f.

(Modification 6)
Further, in the first and second embodiments, the case where the pad 1c of the semiconductor chip 1 and the columnar electrode 1i in the WPP 5 are electrically connected by the rewiring 1f has been described. As shown, in the WPP 5, the pad 1c of the semiconductor chip 1 and the columnar electrode 1i may be electrically connected without the rewiring 1f. That is, the WPP 5 may have a structure in which the columnar electrode 1i and the bump 6b are formed directly above the pad 1c via the UBM 1p.

  However, in the structure in which the columnar electrode 1i and the bump 6b are formed immediately above the pad 1c (position overlapping the original pad 1c), the rewiring 1f layer is formed as in the WPP 5 of the first and second embodiments. The problem of warpage is less likely to occur as compared with the first and second embodiments because it is not provided. That is, for the WPP structure in which the problem of warpage is likely to occur, the structure of the modified example 6 in FIG.

  The present invention is applicable to an electronic device having bump bonding and a manufacturing technique thereof.

1 Semiconductor chip (base material)
DESCRIPTION OF SYMBOLS 1a Main surface 1b Back surface 1c Pad 1d Insulating film 1e Seed layer 1f Rewiring 1g Upper layer wiring 1h Bump land 1i Electrode 1j Protruding part 1k Plating film 1m Insulating film 1n Semiconductor element 1p UBM
1q seed layer 1r insulating film 2 wafer (base material)
3 Mask 3a Exposure 4a, 4b Resist film 4c, 4d Opening 5 WPP (semiconductor device)
6, 6a, 6b Bump 6c Solder material 6d Core ball 7 Resin (resin layer)
8 mark 9 byte 10 flux 11 motherboard 11a terminal 12 pressing member

Claims (12)

A substrate having a main surface, a semiconductor element formed on the main surface, a pad electrically connected to the semiconductor element, and a back surface opposite to the main surface;
A first insulating film formed on the main surface of the substrate so that the pad is exposed;
A first wiring formed on the first insulating film and electrically connected to the pad and made of copper;
A second wiring formed on the first wiring;
A second insulating film formed on the second wiring such that the first region of the second wiring is exposed;
Columnar electrodes formed in the first region of the second wiring;
A bump made of a tin-based material that is bonded to the surface of the electrode and the surface exposed from the electrode in the first region of the second wiring, and
A third insulating film formed on the second insulating film so that a part of the bump is exposed;
Including
The semiconductor device according to claim 1, wherein the first region of the second wiring is arranged at a position that does not overlap the pad in a plan view. In claim 1,
The electrode has a projecting portion projecting in a horizontal direction. In claim 1,
A semiconductor device, wherein a fourth insulating film is formed under the first wiring. In claim 1,
The bump is composed of a first bump bonded to the electrode and a second bump laminated on the first bump, and the second bump has a core ball inside. apparatus. A method for manufacturing a semiconductor device comprising the following steps:
(A) a main surface, a semiconductor element formed on the main surface, a pad electrically connected to the semiconductor element, a first insulating film formed on the main surface so that the pad is exposed, and the main Providing a substrate having a back side opposite to the side;
(B) After the step (a), forming a first wiring made of copper electrically connected to the pad on the first insulating film;
(C) after the step (b), forming a second wiring having a first region on the first wiring;
(D) a step of forming a columnar electrode in the first region of the second wiring after the step (c);
(E) after the step (d), forming a second insulating film on the second wiring so that a part of the first region of the second wiring is exposed;
(F) After the step (e), forming a first bump made of a tin-based material so as to be bonded to the surface of the electrode and the part of the first region of the second wiring;
(G) After the step (f), forming a third insulating film on the second insulating film so as to cover the surface of the first bump;
(H) after the step (g), exposing a part of the first bump;
here,
In the step (c), the first region of the second wiring is disposed at a position that does not overlap the pad in plan view. In claim 5,
When forming the electrode in the first region of the second wiring in the step (d), a part of the electrode protrudes horizontally from the opening of the resist film formed on the second wiring. And forming the electrode in the first region of the opening. In claim 5,
In the step (h), the third insulating film and the first bump are bite-ground to expose a part of the first bump. In claim 7,
In the bite grinding, the semiconductor device is manufactured so that the film of the first bump remains on the electrode. In claim 5,
A film-like resin or a paste-like resin is used as the third insulating film in the step (g), and the film-like resin or the resin on the second insulating film so as to cover the surface of the first bump in the step (g). A method of manufacturing a semiconductor device, comprising: arranging the paste-like resin, and thereafter performing a baking process to cure the film-like resin or the paste-like resin. In claim 5,
After the step (h), the back surface of the base material is ground. In claim 5,
When forming the first bump in the step (f), the surface of the electrode and the part of the first region of the second wiring are joined by solder printing before the step (f). A method of manufacturing a semiconductor device, comprising: applying a tin-based solder material to the first bump and then performing reflow in the step (f) to form the first bump. In claim 5,
After the step (h), a second bump made of the same material as that of the first bump is joined to the exposed part of the first bump.

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