KR100863502B1 - Shift register and liquid crystal display with the same - Google Patents

Abstract

Disclosed are a shift register and a liquid crystal display device having the same. The shift register is composed of a plurality of stages connected to each stage, and each stage is configured to control transfer of a corresponding clock among the first and second clocks to the down stage, the pull up unit, the pull down unit, the pull down unit, and the pull down unit. And a second carry buffer provided from the first carry buffer of the previous stage to maintain a level of a corresponding carry voltage among the first and second clocks applied to the pull-up unit. Accordingly, it is possible to provide a shift resistor insensitive to a threshold voltage when applied to a large screen, high resolution a-Si TFT LCD.

LCD, shift register, charge, shift register, threshold voltage, large screen

Description

SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY WITH THE SAME}

1 is a schematic view showing the configuration of a TFT substrate of a poly-TFT LCD.

2 is a schematic view showing the structure of a TFT substrate of a conventional a-Si LCD.

3 is an exploded perspective view of the a-Si TFT liquid crystal display device according to the present invention.

4 is a view showing the configuration of a TFT substrate of an a-Si TFT LCD according to the present invention.

5 is a block diagram of a shift register of the data driving circuit of FIG. 4 described above.

FIG. 6 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.

FIG. 7 shows a detailed circuit configuration of each stage of the shift register shown in FIG.

8 is an output waveform diagram according to FIG. 7 described above.

FIG. 9 is a waveform diagram illustrating the driving waveform shown in FIG. 6 described above.

10A to 10C are diagrams for explaining simulation results of the gate signal waveforms output from the a-Si TFT shift register of FIG. 7 described above.

FIG. 11 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.                 

12 is a circuit diagram illustrating a shift register according to a first embodiment of the present invention.

13 is a circuit diagram illustrating a shift register according to a second embodiment of the present invention.

14A to 14C are output waveform diagrams according to FIG. 13 described above.

15 is a circuit diagram for describing a shift register according to a third embodiment of the present invention.

16 is a circuit diagram illustrating a shift register according to a fourth embodiment of the present invention.

FIG. 17 is a diagram illustrating the charging potential of the capacitor node of FIG. 16.

<Description of the symbols for the main parts of the drawings>

110: liquid crystal display panel assembly 120: backlight assembly

130: chassis 140: cover

150: display cell array circuit 160: data driving circuit

162, 163, 169: external connection terminal 170: gate driving circuit

171: pull-up unit 172: pull-down unit

173: pull-up driving unit 174: pull-down driving unit

Carry buffer: 175, 176, 275, 276, 375, 376, 475, 476

The present invention relates to a shift register and a liquid crystal display having the same, and more particularly, to a shift register and a liquid crystal display having the same, which can be applied to a large-screen, high-resolution a-Si TFT LCD.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage compared to a typical CRT display device, and is capable of full color and is emerging as a next generation display device.

A liquid crystal display device applies voltage to a specific molecular array of a liquid crystal and converts it into another molecular array, and visually changes the optical properties such as birefringence, photoreactivity, dichroism, and light scattering characteristics of the liquid crystal cell that emit light by the molecular arrangement. It is a display using the modulation of the light by a liquid crystal cell by converting into.

The liquid crystal display is divided into TN (Twisted Nematic) and STN (Super-Twisted Nematic) methods, and the difference between the driving method is the active matrix display method using the switching element and the TN liquid crystal and the passive matrix using the STN liquid crystal. There is a passive matrix display method.                         

The big difference between these two methods is that the active matrix display method is used for TFT-LCD, which drives the LCD using the TFT as a switch, and the passive matrix display method does not use transistors, thus requiring a complicated circuit. Do not

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones.

The a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

1 is a schematic view showing the configuration of a TFT substrate of a poly-TFT LCD, and FIG. 2 is a schematic view showing the configuration of a TFT substrate of a conventional a-Si LCD.

As shown in Fig. 1, a poly-Si TFT LCD forms a data driving circuit 12 and a gate driving circuit 14 on a glass substrate 10 on which a pixel array is formed, and a terminal portion 16 and an integrated printed circuit. The substrate 20 is connected with the film cable 18. Such a structure can reduce manufacturing cost, minimize power loss by integrating a driving circuit, and provide a slim display device.

However, as shown in FIG. 2, the a-Si TFT LCD forms the data driving chip 34 on the flexible printed circuit board 32 by a chip on film (COF) method, and the flexible printed circuit board 32. The data printed circuit board 36 is connected to the data line terminal portion of the pixel array through the through circuit. In addition, the gate driving chip 40 is formed on the flexible printed circuit board 38 by the above-described COF method, and the gate printed circuit board 42 and the gate line terminal portion of the pixel array are formed through the flexible printed circuit board 40. Connect.

That is, in the a-Si TFT LCD, despite the high productivity which is an advantage of the a-Si process, the poly Si-TFT LCD has a disadvantage in terms of cost and slim structure.

Accordingly, the technical and problem of the present invention have been made in view of this point, and an object of the present invention is to provide a shift register applicable to a large screen and a high-resolution a-Si TFT LCD.

Another object of the present invention is to provide a liquid crystal display device having the shift register.

According to one aspect of the present invention, a shift register includes a plurality of stages, a first stage of which a start signal is coupled to an input terminal, and a shift for sequentially outputting output signals of the stages. In the register, odd-numbered stages of the shift register are provided with a first clock and a first control signal for removing an output of the first clock, and even-numbered stages are phase-inverted with respect to the first clock. Two clocks and a second control signal for removing the output of the second clock are provided;

A first carry buffer controlling the transfer of a corresponding one of the first and second clocks to a next stage; A pull-up unit configured to provide a corresponding clock among the first and second clocks to an output terminal; A pull-down unit providing a first power supply voltage to the output terminal; Connected to an input node of the pull-up part, the pull-up part is turned on in response to a carry voltage provided from a first carry buffer of a previous stage, and in response to a leading end of the first or second control signal provided from a next stage; A pull-up driving unit which turns off the pull-up unit; The pull-down unit is connected to an input node of the pull-down unit, and the pull-down unit is turned off in response to a clock provided from a first carry buffer of a previous stage, and the pull-down unit is turned on in response to a leading end of the first or second control signal. To pull down driving unit; And a second carry buffer provided from the first carry buffer of the previous stage to maintain a level of a corresponding carry voltage among the first and second clocks applied to the pull-up unit.

According to another aspect of the present invention, a liquid crystal display device includes a display cell array circuit, a data driving circuit, and a gate driving circuit formed on a transparent substrate, and the display cell array circuit includes a plurality of display cell array circuits. And a plurality of gate lines, each display cell circuit being connected to a corresponding data and gate line pair, wherein the gate driving circuit includes a plurality of stages, and starts at the first stage. A signal is coupled to an input terminal, and comprises a shift register that sequentially selects the plurality of gate lines according to output signals of respective stages, wherein odd-numbered stages of the shift register are provided to odd-numbered stages of the shift register. A first control for removing one clock and the output of the first clock The call is provided, and the even-numbered stages is provided with a second control signal to remove the phase shift of the second clock and an output of the second clock to the first clock, wherein said each stage,

A first carry buffer controlling the transfer of a corresponding one of the first and second clocks to a next stage; A pull-up unit configured to provide a corresponding clock among the first and second clocks to an output terminal; A pull-down unit providing a first power supply voltage to the output terminal; A pull-up unit connected to an input node of the pull-up unit and turning on the pull-up unit in response to a clock provided from a first carry buffer of a previous stage, and responsive to a tip of the first or second control signal provided from a next stage; A pull-up driving unit which turns off the pull-up unit; A pull-down part connected to an input node of the pull-down part, the pull-down part being turned off in response to a carry voltage provided from a first carry buffer of a previous stage, and the pull-down part being turned in response to a leading end of the first or second control signal; Pull down driving unit to turn on; And a second carry buffer provided from the first carry buffer of the previous stage to maintain a level of a corresponding carry voltage among the first and second clocks applied to the pull-up unit.

According to such a shift register and a liquid crystal display having the same, a carry buffer which generates a carry voltage independently in the middle of each stage constituting the shift register is insensitive to a threshold voltage when applied to a large screen and a high-resolution a-Si TFT LCD. One shift register can be provided.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

3 is an exploded perspective view of the a-Si TFT liquid crystal display device according to the present invention.

Referring to FIG. 3, the liquid crystal display 100 largely includes a liquid crystal display panel assembly 110, a backlight assembly 120, a chassis 130, and a cover 140.

The liquid crystal display panel assembly 110 includes a liquid crystal display panel 112, a flexible printed circuit board 116, an integrated control and data driving chip 118. The liquid crystal display panel 112 includes a TFT substrate 112a and a color filter substrate 112b. In the TFT substrate 112a, a display cell array circuit, a data driving circuit, a gate driving circuit, and external connection terminals are formed by an a-Si TFT process. Color filters and transparent common electrodes are formed on the color filter substrate 112b. The TFT substrate 112a and the color filter substrate 112b are opposed to each other and liquid crystal is injected therebetween and then encapsulated.

The integrated control and data driver chip 118 and the circuits of the TFT substrate 112a provided in the flexible printed circuit board 116 are electrically connected by the flexible printed circuit board 116. The flexible printed circuit board 116 provides data signals, data timing signals, gate timing signals, and gate driving voltages to the data driving circuit and gate driving circuit of the TFT substrate 112a.

The backlight assembly 120 includes a lamp assembly 122, a light guide plate 124, optical sheets 126, a reflector plate 128, and a mold frame 129.

4 is a view showing the configuration of a TFT substrate of an a-Si TFT LCD according to the present invention.

Referring to FIG. 4, the display cell array circuit 150, the data driver circuit 160, the gate driver circuit 170, the data driver circuit external connection terminals 162 and 163 and the gate are disposed on the TFT substrate 112a of the present invention. The driving circuit external connection terminal portion 169 is formed together in the TFT process.                     

The display cell array circuit 150 includes m data lines DL1 to DLm extending in a column direction and n gate lines GL1 to GLn extending in a row direction.

In the exemplary embodiment of the present invention, the number of data lines and gate lines in the 2-inch liquid crystal display panel has a resolution of 525 (ie, 176 × 3) × 192.

At each intersection of the data lines and the gate lines, a switching transistor ST is formed. The drain of the switching transistor STi is connected to the data line DLi, and the gate is connected to the gate line GLi. The source of the switching transistor STi is connected to the transparent pixel electrode PE. The liquid crystal LC is positioned between the transparent pixel electrode PE and the transparent common electrode CE formed on the color filter substrate 112b.

Therefore, the liquid crystal array is controlled by the voltage applied between the transparent pixel electrode PE and the transparent common electrode CE, thereby controlling the amount of light passing through to display the gray level of each pixel.

The data driving circuit 160 includes a shift register 164 and 528 switching transistors SWT. The 528 switching transistors SWT form eight data line blocks BL1 to BL8 for 66 units.

Each data line block BLi has 66 input terminals commonly connected to the external input terminal 163 composed of 66 data input terminals, and 66 output terminals are connected to the corresponding 66 data lines. In addition, a block select terminal is connected to a corresponding one of the eight output terminals of the shift register 164.

Each of the 528 switching transistors SWT has a source connected to a corresponding data line, a drain connected to a corresponding input terminal of 66 data input terminals, and an a-Si TFT MOS transistor connected to a block selection terminal at a gate thereof. It consists of.

Accordingly, the 528 data lines are divided into eight blocks of 66 pieces, and each block is sequentially selected by the eight block selection signals of the shift register 164.

The shift register 164 receives a first clock CKH, a second clock CKHB, and a block selection start signal STH through an external connection terminal 162 of three terminals. The output terminals of the shift register 164 are connected to block select terminals of the corresponding line blocks, respectively.

5 is a block diagram of a shift register of the data driving circuit of FIG. 4 described above.

Referring to FIG. 5, in the shift register 164 according to the present invention, nine stages SRH1 to SRH9 are connected. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The number of stages is composed of eight stages SRH1 to SRH8 and one dummy stage SRH9 corresponding to the data line blocks. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD. The eight stages SRH1 to SRH8 provide the block select start signals DE1 to DE8 to the block select terminals of the data line blocks BL1 to BL8, respectively. The block selection start signal is an enable signal of each line block.

The first clock CKH is provided to the odd-numbered stages SRH1, SRH3, SRH5, SRH7, and SRH9, and the second clock CKHB is provided to the even-numbered stages SRC2, SRC4, SRH6, and SRH8. The first clock CKH and the second clock CKHB have phases opposite to each other. The duty periods of the clocks CKH and CKHB are 1/66 ms or less.                     

The output signal of the next stage is input to the control terminal CT as a control signal to each control terminal CT of each stage. That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since output signals of each stage are sequentially generated with an active period (that is, a high state), corresponding data line blocks are selected and enabled in the active period of each output signal.

The dummy stage SRH9 is for providing a control signal to the control terminal CT of the previous stage SRH8.

FIG. 6 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.

Referring to FIG. 6, the gate driving circuit 170 of FIG. 4 includes one shift register, and the shift register is connected to a plurality of stages SRC1 to SRC193. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The stages include 192 stages SRC1 to SRC192 and one dummy stage SRC193 corresponding to the gate lines. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

The scan start signal STV is input to the input terminal IN of the first stage SRC1. The scan start signal STV is a pulse synchronized with the vertical synchronization signal Vsync.

The output signals GOUT1 to GOUT192 of each stage are connected to the corresponding gate lines. The odd clock stages SRC1, SRC3,... Are provided with a first clock CKV, and the even stages SRC2, SRC4, ... are provided with a second clock CKVB. Here, the first clock CKV and the second clock CKVB have phases opposite to each other. In addition, the duty period of the first clock CKV and the second clock CKVB may be a period of 16.6 / 192 ms.

Therefore, the duty period of the clock of the shift register 170 of the gate driving circuit is about 8 times or more than the duty period of the clock of the shift register 164 of the data driving circuit.

In each control terminal CT of each stage SRC1, SRC2, SRC3, ..., output signals GOUT2, GOUT3, GOUT4 of the next stage SRC2, SRC3, SRC4, ... are used as control signals. It is input to (CT). That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since the output signals of each stage are sequentially generated with an active period (high state), the corresponding horizontal line is selected in the active period of each output signal.

FIG. 7 shows a detailed circuit configuration of each stage of the shift register shown in FIG. 6, and FIG. 8 is an output waveform diagram according to FIG.

Referring to FIG. 7, each stage of the shift register 170 includes a pull up unit 171, a pull down unit 172, a pull up driver 173, and a pull down driver 174.

The first NMOS transistor M1 having a drain connected to a power clock input terminal CKV, a gate connected to a third node N3, and a source connected to an output terminal GOUT [N] is connected to the pull-up unit 171. It consists of.

The second NMOS transistor M2 having a drain connected to an output terminal GOUT [N], a gate connected to a fourth node N4, and a source connected to a first power voltage VSS. It consists of.

The pull-up driving unit 173 includes a capacitor C and third to fifth NMOS transistors M3 to M5. The capacitor C is connected between the third node N3 and the output terminal GOUT [N]. The third transistor M3 has a drain connected to the second power supply voltage VON, a gate connected to an input terminal IN, that is, an output signal GOUT [N-1] of a previous stage, and a source of the third transistor M3. It is connected to node N3. In the fourth transistor M4, a drain is connected to the third node N3, a gate is connected to the fourth node N4, and a source is connected to the first power voltage VOFF. In the fifth transistor NT5, a drain is connected to the third node N3, a gate is connected to the fourth node N4, and a source is connected to the first power voltage VOFF. In this case, the size of the third transistor M3 is about twice as large as that of the fifth transistor M5.

The pull-down driver 174 includes sixth and seventh NMOS transistors M6 and M7. The sixth transistor M6 has a drain and a gate in common and is connected to the second power supply voltage VON, and a source is connected to the fourth node N4. In the seventh transistor M7, a drain is connected to the fourth node N4, a gate is connected to the third node N3, and a source is connected to the first power voltage VOFF. In this case, the size of the sixth transistor M6 is about 16 times larger than the size of the seventh transistor M7.

As shown in FIG. 8, when the first and second power clocks CKV and CKVB and the scan start signal ST are supplied to the shift register, the first stage SRC1 is provided at the leading end of the scan start signal ST. In response, the high level section of the first power clock CKV is delayed by a predetermined time Tdr1 to generate an output signal GOUT1 at the output terminal OUT.

As described above, the first and second power clocks CKV and CKVB are supplied to the glassy shift register on which the array substrate is disposed together with the scan start signal STV to perform an operation as a gate driving circuit.

FIG. 9 is a waveform diagram illustrating the driving waveform shown in FIG. 6 described above.

Referring to FIG. 9, the shift register selects either one of the first power clock CKV or the second power clock CKVB in which the phase is inverted with respect to the first power clock CKV. When applied, the gate signals GOUT1, GOUT2, GOUT3, ... are sequentially output to the TFT-LCD gate line. In this case, the first and second power clocks CKV and CKVB may output a signal having an amplitude of 0 to 3 V, which is an output of a timing controller (not shown), to drive a-TFT. Amplified signal.

However, when the shift register is used as a gate driving circuit, as described with respect to a liquid crystal display panel having a resolution of 525 (176 × 3) × 192, it is suitable for a small or small screen, but not for a large screen having a high resolution.

This is because the size of each transistor M1 / M2 performing the pull up / pull function must be increased to cover the gate line corresponding to the large screen, but it is a burdensome size to design the integrated shift register in a predetermined space.

Therefore, due to the size and amorphous characteristics of the pull-up / pull-down transistors M1 / M2 that do not sufficiently drive the gate line, the temperature and the threshold voltage Vth of the TFT are changed in a polycrystalline silicon (POLY-Si) or a single crystal silicon device. It is very large compared to the problem of reliability and yield.

10A to 10C are diagrams for explaining simulation results of the gate signal waveforms output from the a-Si TFT shift register of FIG. 7 described above.

Referring to FIG. 10A, at room temperature and normal threshold voltage, the gate signals GOUT1, GOUT2, GOUT3, ... output from each stage of the a-Si TFT shift register are approximately 25 volts with a slope close to that of a square wave. Have the same level.

Meanwhile, referring to FIG. 10B, since the threshold voltage decreases as the temperature increases, the gate signals GOUT1 ', GOUT2', GOUT3 ', ... outputted from the respective stages of the a-Si TFT shift registers are inclined by the square wave. While having a slope close to, the first gate signal GOUT1 ′ has a level of approximately 20 volts, and the second gate signal GOUT2 ′ has a voltage level that decreases sequentially.

In particular, it can be seen that a spark-like override is applied to a specific gate line before the gate signal is applied. This override causes the levels of the gate signals to sequentially decrease, causing malfunctions in the output waveform of each stage.

Meanwhile, referring to FIG. 10C, since the threshold voltage increases as the temperature decreases, the gate signals GOUT1 ", GOUT2", GOUT3 ", ... outputted from each stage of the a-Si TFT shift register have a gentle slope. Also, the first gate signal GOUT1 ″ has a level of about 22 volts, and the second gate signal GOUT2 ″ has a voltage level that decreases sequentially.

As described in the waveform diagrams above, the shift register operates normally at room temperature and the normal threshold voltage Vth, and gate signals output from each stage of the shift register are output as uniform voltage levels. However, when the threshold voltage Vth changes as the temperature increases or decreases, the gate signals output from each stage of the shift register have an abnormal waveform. These abnormal waveforms do not normally turn on the switching elements included in the liquid crystal display panel, thereby causing a failure to display a normal screen.

In particular, the above results are caused by a circuit structure in which the gate signal output from the front stage becomes a carry and adversely affects the gate signal output from the current stage, as shown in FIG. 6. When this occurs and each stage is driven continuously, it can be seen that there are stages that fail to output a gate signal.

The above results are more prominent in the large-screen, high-resolution liquid crystal display panel in which the capacity of the pull-up unit 142 and the pull-down unit 144 for outputting the gate signal is insufficient compared to the length of the gate line, and the number of stages is increased.

Next, a description will be given with reference to the accompanying drawings in which a-Si TFT shift registers are insensitive to the threshold voltage Vth essential for application to a large screen, high-resolution liquid crystal display panel.                     

FIG. 11 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.

Referring to FIG. 11, the gate driving circuit 170 of FIG. 4 includes one shift register, and the shift register includes a plurality of stages SRC1, SRC2, SRC3,..., SRCg, SRC ( g + 1)) is connected and a plurality of carry buffers CB1, CB2, ..., CBg are provided between stages. That is, the output terminal GOUT of each stage is connected to the control terminal CT of the previous stage. Here, the stages are composed of g stages SRC1 to SRCg corresponding to the gate lines and one dummy stage SRC (g + 1). Each stage includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, a second power supply voltage terminal VDD, and a carry output terminal. CRR).

The scan start signal STV is input to the input terminal IN of the first stage SRC1. The scan start signal STV is a pulse synchronized with the vertical synchronization signal Vsync provided from an external graphic controller.

The input terminal IN of the second and subsequent stages SRC2, SRC3, SRC4, ... receives the carry voltage provided from the carry output terminal CRR of the previous stage via the carry buffer.

Output signals GOUT1 to GOUTg of each stage are connected to corresponding gate lines. The odd clock stages SRC1, SRC3,... Are provided with a first clock CKV, and the even stages SRC2, SRC4, ... are provided with a second clock CKVB. Here, the first clock CKV and the second clock CKVB have phases opposite to each other. In addition, the duty period of the first clock CKV and the second clock CKVB may be approximately 16.6 / g [ms].

In each control terminal CT of each stage SRC1, SRC2, SRC3, ..., output signals GOUT2, GOUT3, GOUT4 of the next stage SRC2, SRC3, SRC4, ... are used as control signals. It is input to (CT). That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since the output signals of each stage are sequentially generated with an active period (high state), the corresponding horizontal line is selected in the active period of each output signal.

As described above, the carry buffers CB1, CB2, ..., CBg provided between stages use a clock voltage directly input from the outside as a carry instead of a gate signal to be loaded. The carry buffers CB1, CB2, ..., CBg are preferably provided in the respective stages. The carry buffers provided in the stage will be described with reference to the accompanying drawings.

FIG. 12 is a circuit diagram for explaining a shift register according to a first embodiment of the present invention. In particular, FIG. 12 is a diagram for explaining a specific circuit configuration of each stage of the shift register shown in FIG. In the drawings, only two stages are shown for convenience of description.

12, each stage of the shift register according to the first embodiment of the present invention may include a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, a pull-down driver 174, and a first carry buffer ( 175 and a second carry buffer 176. As compared with FIG. 7, the pull-up unit 171, the pull-down unit 172, the pull-up driver 173, and the pull-down driver 174 are the same, and therefore, the same reference numerals will be given, and detailed description thereof will be omitted.

The first carry buffer 175 is configured of the first transistor TR1 to control the transfer of the corresponding clock among the first and second clocks CKV / CKVB to the next stage.

More specifically, the gate of the first transistor TR1 is connected to the input terminal of the pull-down driver 174, the drain is connected to the clock terminal input from the outside, and the source is connected to the second carry buffer 176 of the next stage. do.

The second carry buffer 176 is composed of a second transistor TR2 controlled by the pull-down driver 174 which performs an inverting function, and is in a turn-on state from the first carry buffer 175 of the previous stage. When the buffer transistor M3 is operated by the corresponding one of the first and second clocks provided to the pull-up unit 171 and the pull-down driving unit 174 is inverted, the turn-off time results in a carry voltage being transferred. Prevent the carry level from dropping.

Here, the drain of the second transistor TR2 is connected to the source of the first transistor TR1 of the previous stage and the input terminal of the pull-up driver 173 of the current stage, respectively, and the gate is the pull-down unit 172, that is, the transistor M2. ) Is connected to the gate, and the source is connected to the first power supply voltage through the first power supply voltage terminal VOFF.

In addition, the second carry buffer 176 maintains the turn-on state by the operation of the pull-down driver 174 again after 1H and applies the first power supply voltage VOFF to turn off the buffer transistor M3. . Here, the first power supply voltage terminal VOFF is the same as the first power supply voltage terminal VSS described with reference to FIG. 5.

As such, instead of using the output signal of the previous stage that is loaded on each stage outputting the gate signals as a carry, the gate signals output from each stage are output to the output signals of the previous stage by using an external clock as a carry. It is possible to obtain gate signals irrelevant to.

Then, the upper stage among the stages shown in FIG. 12 is defined as the previous stage, the lower stage is defined as the current stage, and the same reference numerals are applied to the first embodiment of the present invention. The operation of the shift register will be described.

The first transistor TR1 provided in the previous stage samples a signal for activating the gate signal GOUT [N], that is, a clock CKV, which is a control signal of the pull-up transistor M1, and converts the sampled signal into a carry voltage. To the current stage. In other words, the constant clock level is always used as the carry voltage, thereby eliminating the chain reaction that may occur when the stage output voltage drops.

The second transistor TR2 is in a high impedance (that is, turn-off) state when the capacitor provided in the pull-up driving unit 173 of the current stage is charged, and is applied to the second transistor TR2 when the current stage is in the idle state. The voltage VOFF is applied to the gate of the buffer transistor M3 to keep the buffer transistor M3 turned off.

More specifically, the transistor M3 included in the pull-up driving unit 173 of the current stage maintains the turn-off state and transitions to the idle state when the carry voltage is input via the first transistor TR1 of the previous stage. do. In this case, the voltage applied to the gate of the transistor M3 is divided by the resistance of the first transistor TR1, the resistance of the second transistor TR2, and the resistance of the second transistor TR2 that is still turned on. Voltage.

Subsequently, when a predetermined time passes, the second transistor TR2 is turned off, and when a carry voltage such as a clock is applied to the gate of the buffer transistor M3, a voltage corresponding to the voltage VON applied through the drain is charged to the capacitor. Form a path if possible.

Subsequently, when a predetermined time has elapsed and a low level clock voltage, for example, a VOFF level clock voltage is applied to the gate of the buffer transistor M3, it is turned off.

FIG. 13 is a circuit diagram for explaining a shift register according to a second embodiment of the present invention. In particular, FIG. 13 is a diagram for explaining a specific circuit configuration of each stage of the shift register shown in FIG. In the drawings, only two stages are shown for convenience of description.

Referring to FIG. 13, each stage of the shift register according to the second embodiment of the present invention may include a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, a pull-down driver 174, and a first carry buffer ( 275 and a second carry buffer 276. Compared with FIG. 7, the pull-up unit 171, the pull-down unit 172, the pull-up driver 173, and the pull-down driver 174 are the same, and therefore, the same reference numerals will be given, and detailed description thereof will be omitted.

The first carry buffer 275 includes the first transistor TR1 to control a corresponding clock among the first and second clocks CKV / CKVB to be transferred to the next stage.                     

More specifically, the gate of the first transistor TR1 is connected to the input terminal of the pull-down driver 174, the drain is connected to the clock terminal CKV or CKVB input from the outside, and the source is the second carry buffer of the next stage. 176 is connected.

The second carry buffer 276 is composed of the second and third transistors TR2 and TR3. The second carry buffer 276 is initially turned on and is provided from the first carry buffer 175 of the previous stage to the pull-up unit 171. Carry level during the time when the pull-down driver 174 which performs the inverting operation by turning the buffer transistor M3 by the corresponding clock among the applied first and second clocks is turned off and the carry voltage is transferred. This voltage is prevented from being lowered, and a voltage for turning off the buffer transistor M3 is applied by maintaining the turn-on state by the operation of the pull-down driver 174 again after 1H time.

Here, the drain of the second transistor TR2 is connected to the source of the first transistor TR1 of the previous stage and the input terminal of the pull-up driver 173 of the current stage, respectively, and the gate is the pull-down unit 172, that is, the transistor M2. ) Is connected to the gate of the source, and the source is connected to the third transistor TR3. In this case, the first power supply voltage terminal VOFF is the same as the first power supply voltage terminal VSS described with reference to FIG. 5.

In addition, the drain and the gate of the third transistor TR3 are commonly connected to the source of the second transistor TR2, and the source is connected to the first power supply voltage through the first power supply voltage terminal VOFF.

Then, the upper stage among the stages shown in FIG. 13 is defined as the previous stage, the lower stage is defined as the current stage, and the same reference numerals are used for the components provided in each stage, according to the second embodiment of the present invention. The operation of the shift register is described.

The first transistor TR1 provided in the previous stage samples a signal for activating the gate signal GOUT [N], that is, a clock CKV, which is a control signal of the pull-up transistor M1, and converts the sampled signal into a carry voltage. To the current stage. In other words, the constant clock level is always used as the carry voltage, thereby eliminating the chain reaction that may occur when the stage output voltage drops.

The second transistor TR2 is in a high impedance (that is, turn-off) state when the capacitor provided in the pull-up driver 173 of the current stage is charged, and is applied to the third transistor TR3 when the current stage is in the idle state. The voltage VOFF + Vth is applied to the gate of the buffer transistor M3 to keep the buffer transistor M3 turned off.

More specifically, the transistor M3 included in the pull-up driver 173 of the current stage maintains a turn-off state and transitions to an idle state when a carry voltage is input via the first transistor TR1 of the previous stage. . In this case, the voltage applied to the gate of the transistor M3 is divided by the resistance of the first transistor, the resistance of the second transistor TR2 that is still on, and the clock voltage divided by the threshold voltage of the third transistor TR3. to be.

Subsequently, when a predetermined time elapses, the second transistor TR2 transitions from the idle state to the turn-off state. When the highest carry voltage is applied to the gate of the buffer transistor M3, the second transistor TR2 is applied to the voltage VON applied through the drain. Paths are formed such that the resulting voltage is charged to the capacitor.

Subsequently, when a predetermined time has elapsed and a low level clock voltage, for example, a VOFF level clock voltage is applied to the gate of the buffer transistor M3, the signal is turned off. At this time, the turn-on / off timing of the buffer transistor M3 varies according to the voltage level applied to the gate of the buffer transistor M3 provided in the pull-up driver 173 of the current stage.

The turn-on / off timing is inversely proportional to the threshold voltage of the buffer transistor M3. In other words, when the threshold voltage drops due to an increase in the ambient temperature, the turn-on time point is pulled out from the normal temperature driving time, and when the threshold voltage rises due to the ambient temperature dropping, the turn-on time is delayed from the normal temperature driving time. Therefore, the capacitor charge amount is changed according to the temperature change, and thus the gate signal may be output.

This may prevent an override phenomenon that occurs when the threshold voltage Vth is lowered during the transition process where the second transistor TR2 is not sufficiently turned off. Here, the override phenomenon is a small spark waveform before each stage output waveform is generated, as shown in the simulation result described with reference to FIG. 10B. The spark waveforms cause the output voltage of the front stage to be lowered by lowering the control voltage of the transistor which performs the pull-up function of the capacitor potential by operating the discharge transistor of the front stage.

In the second exemplary embodiment of the present invention described above, the voltage applied to the gate of the buffer transistor M3 is determined by the resistance and threshold voltages of the second and third transistors TR2 and TR3, and by the first transistor TR1. Since the clock divided by the resistance is applied, the temperature compensation operation may be performed. That is, even though the threshold voltage of the buffer transistor M3 changes with temperature, the threshold voltage of the third transistor TR3 also changes with temperature, and a carry voltage interlocked with the temperature is applied to the gate of the buffer transistor to cancel each other. The problem that the output of the gate signal changes with temperature can be solved.

14A to 14C are output waveform diagrams according to FIG. 13 described above.

Referring to FIG. 14A, at room temperature and normal threshold voltage, the gate signals GOUTn1, GOUTn2, GOUTn3, ... outputted from each stage of the a-Si TFT shift register have approximately the same slope close to the square wave, Have the same level. Here, the waveforms of the gate signals GOUTn1, GOUTn2, GOUTn3, ... shown in FIG. 14A and the waveforms of the gate signals GOUT1, GOUT2, GOUT3, ... shown in FIG. 10A are the same. can confirm.

Meanwhile, referring to FIG. 14B, since the threshold voltage decreases as the temperature increases, the gate signals GOUTn1 ', GOUTn2', GOUTn3 ', ... outputted from each stage of the a-Si TFT shift register are close to the square wave. With the same slope, it has the same level of approximately 25 volts. Here, an override, which is a spark waveform, occurs before an arbitrary gate signal is output to an arbitrary gate line, but it can be confirmed that the waveform has a much reduced level than the override shown in FIG. 10B. As such, the level of the gate signals does not decrease due to the reduced level of override.                     

Meanwhile, referring to FIG. 14C, since the threshold voltage increases as the temperature decreases, the gate signals GOUTn1 ", GOUTn2", GOUTn3 ", ... outputted from each stage of the a-Si TFT shift register are inclined to the square wave. Compared to Fig. 10c, the slope of the waveform is close to the slope of the square wave, and the level does not decrease.

As can be seen from the waveform diagrams above, by implementing the carry buffer in the stage constituting the a-Si TFT shift register, the threshold that causes malfunction due to temperature fluctuations as well as the threshold voltage Vth of the a-Si TFT is normal. It can be seen that the a-Si TFT shift register operates normally even if the voltage changes.

According to the second embodiment of the present invention described above, by configuring a carry buffer composed of the first to third transistors TR1, TR2, and TR3 in each stage constituting the shift register, a constant first or second clock is provided. The voltage CKV or CKVB can be transferred to the next stage as well as to generate a carry voltage which is compensated by the variation of the threshold voltage Vth of the a-Si TFT. As a result, when applied to a large screen and a high resolution TFT LCD, it is possible to implement an a-Si TFT shift register insensitive to the threshold voltage (Vth) which yields good yield in terms of reliability and productivity.

FIG. 15 is a circuit diagram for explaining a shift register according to a third embodiment of the present invention. In particular, FIG. 15 is a view for explaining a specific circuit configuration of each stage of the shift register shown in FIG. In the drawings, only two stages are shown for convenience of description.                     

Referring to FIG. 15, each stage of the shift register according to the third embodiment of the present invention may include a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, a pull-down driver 174, and a first carry buffer ( 375 and a second carry buffer 376. As compared with FIGS. 7, 14 and 15, the pull-up unit 171, the pull-down unit 172, the pull-up driver 173, and the pull-down driver 174 are the same, and therefore the same reference numerals will be given, and detailed description thereof will be omitted. .

In addition, since the first carry buffer 375 performs the same operation as the first carry buffers 175 and 275 described above with reference to FIGS. 12 and 13, only the drawing numbers thereof are the same, detailed description thereof will be omitted.

The second carry buffer 376 includes the second transistor TR2 and the fourth transistor TR4, and is initially maintained in a turn-on state and is provided from the first carry buffer 375 of the previous stage. When the pull-down driver 174 which performs the inverting operation by operating the buffer transistor M3 by the corresponding clock among the first and second clocks applied to 171 is turned off, the carry voltage is transferred. During the time, the carry level is prevented from being lowered, and after a 1H time, the voltage is maintained to be turned on by the inverting operation to turn off the buffer transistor M3.

Here, the second transistor TR2 has a drain connected to the source of the first transistor TR1, a gate connected to the pull-up driver 173, and a source connected to the first power supply voltage terminal VOFF. Connected with At this time, the first power supply voltage terminal VOFF is the same as the first power supply voltage terminal VOFF described with reference to FIG. 5.                     

In addition, the fourth transistor TR4 has a drain connected to the gate of the second transistor TR2, a gate connected to the drain of the second transistor, and a source connected to the first power voltage terminal VOFF. Connected with

Then, among the stages shown in FIG. 15, the upper stage is defined as the previous stage, the lower stage is defined as the current stage, and the same reference numerals are used for the components provided in each stage, according to the third embodiment of the present invention. The operation of the shift register is described.

The first transistor TR1 provided in the previous stage samples a signal for activating the gate signal GOUT [N], that is, a clock CKV, which is a control signal of the pull-up transistor M1, and converts the sampled signal into a carry voltage. To the current stage. That is, since a constant clock level is always used as a carry voltage for all stages, it is possible to eliminate the chain reaction that may occur when the stage output voltage drops.

The second transistor TR2 is in a high impedance (that is, turn-off) state when the capacitor provided in the pull-up driving unit 173 of the current stage is charged, and is applied to the second transistor TR2 when the current stage is in the idle state. The voltage VOFF is applied to the gate of the buffer transistor M3 to keep the buffer transistor M3 turned off.

More specifically, when the carry voltage is input through the first transistor TR1 of the previous stage while the transistor M3 of the pull-up driving unit 173 of the current stage is turned off, the transistor M3 The voltage applied to the gate is a clock voltage divided by the resistance of the first transistor TR1, the resistance of the second transistor TR2, and the resistance of the second transistor TR2 that is still turned on.

Subsequently, when a predetermined time passes, the second transistor TR2 is turned off, and when a carry voltage such as a clock is applied to the gate of the buffer transistor M3, a voltage corresponding to the voltage VON applied through the drain is charged to the capacitor. Form a path if possible.

Subsequently, when a predetermined time has elapsed and a low level clock voltage, for example, a VOFF level clock voltage is applied to the gate of the buffer transistor M3, the signal is turned off.

The fourth transistor TR4 is turned on as a carry voltage is generated from the front end stage and applied to the gate, thereby lowering the gate voltage of the second transistor TR2 more quickly, thereby turning on the second transistor TR2 at turn-on. Acts as an acceleration switch to increase the switching speed to switch off-off. This acceleration switch speeds up the carry buffer.

FIG. 16 is a circuit diagram for explaining a shift register according to a fourth embodiment of the present invention. In particular, FIG. 16 is a view for explaining a specific circuit configuration of each stage of the shift register shown in FIG. In the drawings, only two stages are shown for convenience of description.

Referring to FIG. 16, each stage of the shift register according to the fourth embodiment of the present invention may include a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, a pull-down driver 174, and a first carry buffer ( 375 and a second carry buffer 376. Compared with FIG. 7, the pull-up unit 171, the pull-down unit 172, the pull-up driver 173, and the pull-down driver 174 are the same, and therefore, the same reference numerals will be given, and detailed description thereof will be omitted.

The first carry buffer 375 includes the first transistor TR1 to control the transfer of the corresponding clock among the first and second clocks CKV / CKVB to the next stage. More specifically, the gate of the first transistor TR1 is connected to the input terminal of the pull-down driver 174, the drain is connected to the clock terminal CKV or CKVB input from the outside, and the source is the second carry buffer of the next stage. 476.

The second carry buffer 476 is composed of the second to fourth transistors TR2, TR3, and TR4. The second carry buffer 476 is initially turned on and is provided from the first carry buffer 475 of the previous stage. When the buffer transistor M3 is operated by the corresponding one of the first and second clocks applied to the P1 and the pull-down driver 174 is inverted, the carry level decreases during the time when the carry voltage is transferred. And a voltage for turning off the buffer transistor M3 by applying the pull-down driving unit 174 to maintain the turn-on state after 1H time.

Here, the drain of the second transistor TR2 is connected to the source of the first transistor TR1, the gate is connected to the pull-up driver 173, and the source is connected to the third transistor TR3.

In addition, the drain and the gate of the third transistor TR3 are commonly connected to the source of the second transistor TR2, and the source is connected to the first power supply voltage through the first power supply voltage terminal VOFF. In this case, the first power supply voltage terminal VOFF is the same as the first power supply voltage terminal VSS described with reference to FIG. 5.                     

In addition, the fourth transistor TR4 has a drain connected to the gate of the second transistor TR2, a gate connected to the drain of the second transistor TR2, and a source of the fourth transistor TR4 formed through the first power voltage terminal VOFF. 1 It is connected to the power supply voltage. In operation, the fourth transistor TR4 is turned on as a carry voltage is generated from the front end stage and applied to the gate to lower the gate voltage of the second transistor TR2 more quickly, thereby turning on the second transistor TR2. It acts as an acceleration switch to increase the switching speed of switching from on to turn-off. This acceleration switch speeds up the carry buffer.

According to the fourth embodiment of the present invention described above, by mounting the fourth transistor TR4 capable of controlling the turn-on / off of the second transistor TR2, the second transistor TR2 is turned on. You can speed up the carry buffer by adding an acceleration switch that can increase the turn-off switching speed.

FIG. 17 illustrates the charging potential of the capacitor node of FIG. 16 described above. Particularly, when A does not have the fourth transistor TR4 which is an acceleration switch as in the first and second embodiments of the present invention, B is viewed. As shown in the third and fourth embodiments of the present invention, when the fourth transistor TR4, which is an acceleration switch, is added, it is a waveform diagram showing a change in the charging potential of each capacitor node.

As can be seen from FIG. 17, since the fourth transistor TR4 is added, the turn-off time of the second transistor TR2 can be shortened so that the buffer transistor M3 can be driven faster, so that the charge potential of the capacitor node is increased. Can be increased relatively. This is advantageous when driving a high resolution in which charging time is insufficient, and the buffer transistor M3 can be driven at the maximum control voltage, thereby improving the performance of the a-Si TFT shift register.

As described in the various embodiments above, instead of using the output of the front stage as the carry of the next stage, by separately embedding a carry buffer in each stage, the a-Si TFT shift register The malfunction due to the distribution of the threshold voltage (Vth) of can be prevented. By preventing such a malfunction, the LCD is highly reliable in a relatively wide temperature environment and insensitive to the distribution of threshold voltage (Vth) during production, thereby providing a liquid crystal display module equipped with a-Si TFT shift register having high yield.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, by implementing a carry buffer independently for each stage constituting the shift register, a shift register insensitive to a threshold voltage (Vth) when applied to a large screen and a high resolution TFT LCD is provided. to provide. That is, a malfunction due to the distribution of the threshold voltage (Vth) of the a-Si TFT shift resistor can be prevented, thereby improving reliability in a relatively wide temperature environment.

In addition, it is possible to provide a liquid crystal display device equipped with a-Si TFT shift register having high yield since it is insensitive to the threshold voltage Vth distribution during production.

Claims (7)

In the shift register for arranging a plurality of stages, the start signal is coupled to the input terminal in the first stage, and sequentially outputs the output signals of each stage, Odd-numbered stages of the shift register are provided with a first clock, a first control signal for removing the output of the first clock, and even-numbered stages with a second clock phase-inverted to the first clock; A second control signal is provided for removing the output of the second clock. Each stage, First carry means for controlling the transfer of a corresponding one of the first and second clocks to a next stage; Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; A pull-up means connected to an input node of the pull-up means and turning on the pull-up means in response to a carry provided from the first carry means of the previous stage, and responding to a tip of the first or second control signal provided from the next stage; Pull-up driving means for turning off the pull-up means; A pull-down means connected to an input node of the pull-down means, the pull-down means being turned off in response to a clock provided from a first carry means of a previous stage, and the pull-down means being responsive to a tip of the first or second control signal; Pull-down driving means for turning on; And And second carry means provided from a first carry means of a previous stage to maintain a level of a corresponding carry voltage of the first and second clocks applied to the pull-up means. The method of claim 1, wherein the first carry means samples the corresponding one of the first and second clocks applied to the drain in response to an input signal of the pull-down manual means applied to a gate, and the sampled signal is sampled. And a first transistor which outputs to the next stage through the source. The second transistor of claim 1, wherein the second carry means has a drain connected to an output terminal of the first carry means, a gate connected to an input terminal of the pull-up driving means, and a source of the second transistor receiving the first power supply voltage. The shift register further comprises. The method of claim 1, wherein the second carry means, A second transistor having a drain connected to an output terminal of the first carry means and a gate connected to an input terminal of the pull-up driving means; And And a third transistor having a common drain and a gate, the third transistor being connected to a source of the second transistor, and having a source supplied with the first power supply voltage. The method of claim 1, wherein the second carry means, A second transistor having a drain connected to an output terminal of the first carry means and a gate connected to an input terminal of the pull-down driving means; And And a third transistor having a drain connected to the gate of the second transistor, a gate connected to the drain of the second transistor, and a source supplied with the first power supply voltage. The method of claim 1, wherein the second carry means, A second transistor having a drain connected to an output terminal of the first carry means and a gate connected to an input terminal of the pull-down driving means; A third transistor having a common drain and a gate and connected to a source of the second transistor, wherein the source receives the first power supply voltage; And And a fourth transistor having a drain connected to a gate of the second transistor, a gate connected to a drain of the second transistor, and a source supplied with the first power supply voltage. And a display cell array circuit, a data driving circuit, and a gate driving circuit formed on the transparent substrate, wherein the display cell array circuit includes a plurality of data lines and a plurality of gate lines, and each display cell circuit includes corresponding data and In a liquid crystal display device connected to a pair of gate lines, The gate driving circuit includes a plurality of stages, and a first stage includes a shift register coupled to an input terminal and sequentially selecting the plurality of gate lines by an output signal of each stage. Odd-numbered stages of the register are provided with odd-numbered stages of the shift register and a first control signal for canceling the output of the first clock, and even-numbered stages are phased with the first clock. A second inverted clock and a second control signal for removing the output of the second clock are provided, Each stage, First carry means for controlling the transfer of a corresponding one of the first and second clocks to a next stage; Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; Connected to an input node of the pull-up means, turn on the pull-up means in response to a clock provided from the first carry means of the previous stage, and respond to a tip of the first or second control signal provided from the next stage; Pull-up driving means for turning off the pull-up means; A pull-down means connected to an input node of the pull-down means, the pull-down means being turned off in response to a clock provided from a first carry means of a previous stage, and the pull-down means being responsive to a tip of the first or second control signal; Pull-down driving means for turning on; And And second carry means provided from a first carry means of a previous stage to maintain a level of a corresponding carry voltage among the first and second clocks applied to the pull-up means.

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