KR100796125B1 - Shift register and data driver and Organic Light Emitting Display Using the same - Google Patents

Abstract

The data driving circuit according to the present invention is a data driving circuit for outputting a data signal to each of n channels, comprising: a shift register section for receiving first and second clock signals and data, and shifting and outputting the received data; ; And a latch unit for receiving first and second enable signals and simultaneously outputting data received from the shift register unit.

According to an exemplary embodiment of the present invention, the shift register, the data driver, and the organic light emitting display device using the same may be mounted on a panel because the shift registers and latches included in the data driver are configured only with PMOS transistors. There is an advantage to reduce.

Description

Shift register and data driver circuit and organic electroluminescent display using same {shift register and data driver and Organic Light Emitting Display Using the same}

1 illustrates an organic electroluminescent display device according to an embodiment of the present invention.

2 is a diagram illustrating one frame of an organic electroluminescent display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating an embodiment of a pixel illustrated in FIG. 1;

4 is a diagram illustrating a circuit configuration of a shift register provided in the data driver and / or the scan driver shown in FIG. 1.

FIG. 5 is a waveform diagram showing the operation of the shift register shown in FIG. 4; FIG.

6A to 6D are diagrams showing a circuit configuration of a shift register according to the second to fifth embodiments of the present invention.

7 is a waveform diagram showing operation of another embodiment of the shift register according to the embodiment of the present invention;

8 is a block diagram showing a data driving circuit according to an embodiment of the present invention.

FIG. 9 is a waveform diagram showing a method of driving the data driving circuit shown in FIG. 8; FIG.

FIG. 10 is a diagram showing a circuit configuration of a shift register provided in the shift register section shown in FIG. 8; FIG.

FIG. 11 is a view showing a circuit configuration of a latch provided in the latch unit shown in FIG. 8. FIG.

12 is a diagram illustrating a circuit configuration according to another embodiment of a shift register provided in the shift register unit shown in FIG. 8.

Fig. 13 is a waveform diagram showing a method of driving a data driving circuit according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: scan driver 20: data driver

30 pixel portion 40 pixel

42: pixel circuit 50: timing controller

80: shift register portion 90: latch portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, a data driver, and an organic electroluminescent display using the same. In particular, a shift register, a data driver, and an organic electroluminescent display using the same may include a PMOS transistor. Relates to a device.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display.

Among the flat panel displays, an organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. Such an organic light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

Such an organic electroluminescent display includes pixels arranged in a matrix, a data driver for driving data lines connected to the pixels, and a scan driver for driving scan lines connected with the pixels.

The data driver supplies a data signal corresponding to the data every horizontal period so that a predetermined image is displayed in the pixels. The scan driver sequentially selects pixels to which the data signal is to be supplied by sequentially supplying the scan signal every horizontal period.

On the other hand, in order to reduce size, weight, and manufacturing cost of the organic light emitting display device toward a large panel, a data driver must be mounted on the panel. However, since the shift register, which is a component of the conventional data driver and the data driver, is composed of a PMOS transistor and an NMOS transistor, it is difficult to be mounted on a panel. Accordingly, there is a demand for a data driver configured with a PMOS and mounted on a panel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register, a data driver, and an organic electroluminescent display using the same, which are configured by PMOS transistors and can be applied during digital driving.

In order to achieve the above object, the shift register according to the embodiment of the present invention receives the first and second clock signals CLK and / CLK and an input signal in, and stores the input signal in. A transfer unit for outputting; An inversion unit which receives the first and second clock signals CLK and / CLK and an input signal in, stores the input signal, and then inverts and outputs the input signal; It is composed of a pull-up transistor and a pull-down transistor, characterized in that it is composed of a buffer unit (buffer unit) for selecting and outputting the signal output from the transfer section and the inverting section.

Here, the plurality of shift registers may be connected in cascade form to sequentially output the first input signal, and the input signal in may be an initial start pulse SP or an output signal of a previous stage. .

Also. In the case of the odd shift register among the shift registers connected to the cascade, the first clock signal CLK is supplied to the first clock terminal, and the second clock signal / CLK is supplied to the second clock terminal. When the first clock signal CLK is supplied at a low level and the second clock signal / CLK is supplied at a high level, the output of the previous section is maintained as a high impedance output state, and the first clock signal CLK is When the high level and the second clock signal / CLK are supplied at the low level, the same waveform as the input signal stored in the previous section is output.

In addition, in the case of the even shift register among the shift registers connected to the cascade, the second clock signal / CLK is supplied to the first clock terminal, and the first clock signal CLK is supplied to the second clock terminal. When the second clock signal / CLK is supplied at a low level and the first clock signal CLK is supplied at a high level, the second clock signal / CLK maintains the output of the previous section as a high impedance output state and the second clock signal / CLK When the high level and the first clock signal CLK are supplied at the low level, the same waveform as the input signal stored in the previous section is output.

In addition, the data driving circuit according to the present invention is a data driving circuit for outputting a data signal to each of n channels, the shift register receiving first and second clock signals and data, and shifting and outputting the received data. Wealth; And a latch unit for receiving first and second enable signals and simultaneously outputting data received from the shift register unit.

Here, the shift register unit is composed of 2n shift registers S / R1 to S / R2n connected in cascade, and the first shift register S / R1 receives a data signal and second to second nn shift registers. (S / R2 ~ S / R2n) is characterized by receiving the output signal of the previous shift register.

The odd-numbered shift register of the 2n shift registers receives the first clock signal CLK through the first clock terminal clk and receives the second clock signal / CLK through the second clock terminal / clk. The even-numbered shift register receives the second clock signal / CLK through the first clock terminal clk, and receives the first clock signal CLK through the second clock terminal / clk. do.

In addition, the latch unit is composed of n latches for inputting the output of the odd shift register among the outputs of the 2n shift registers constituting the shift register, respectively, and simultaneously output data respectively received from the odd shift register. It is characterized by.

In addition, the organic electroluminescent display device according to the present invention is a digitally driven organic light emitting display device, comprising: a scan driver for sequentially supplying a scan signal to scan lines, and a first data signal or a first data line to each of the data lines; And a data driver for supplying a second data signal, and pixels selected when the scan signal is supplied and controlled to emit light by receiving the first data signal or the second data signal.

A latch for receiving first and second clock signals and data, shifting the outputted data and outputting the first and second enable signals, and simultaneously outputting data received from the shift register section; It is characterized in that the addition is configured.

Hereinafter, preferred embodiments of the present invention may be easily implemented by those skilled in the art with reference to FIGS. 1 to 13 as follows.

1 illustrates an organic electroluminescent display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an organic electroluminescent display according to an exemplary embodiment of the present invention includes a pixel unit including a plurality of pixels 40 connected to scan lines S1 to Sn and data lines D1 to Dm. 30, the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20. Is provided with a timing controller 50 for controlling.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The data driver 20 supplies a data signal to the data lines D1 to Dm for each of a plurality of sub frame periods included in one frame. Here, the data signal is divided into a first data signal that can emit light of the pixel 40 and a second data signal that does not emit light of the pixel 40. In other words, the data driver 20 supplies the first data signal or the second data signal for controlling whether the pixel 40 emits light to the data lines D1 to Dm in each sub frame period.

The scan driver 10 sequentially supplies a scan signal to the scan lines S1 to Sn in each sub frame period. When the scan signals are sequentially supplied to the scan lines S1 to Sn, the pixels 40 are sequentially selected for each line, and the selected pixels 40 are first data signals or first supplied from the data lines D1 to Dm. 2 The data signal is supplied.

The pixel unit 30 receives the first power source ELVDD and the second power source ELVSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power source ELVDD and the second power source ELVSS receives a data signal (a first data signal or a second data signal) when a scan signal is supplied, and the supplied data signal. Corresponding to the light emission or non-light emission during each sub frame period.

2 is a view briefly illustrating one frame of an organic electroluminescent display device according to an exemplary embodiment of the present invention. In FIG. 2, one frame is divided into eight subframes for convenience of description, but the present invention is not limited thereto.

Referring to FIG. 2, one frame 1F of an organic electroluminescent display according to an exemplary embodiment of the present invention is divided into a plurality of subframes SF1 to SF8 and driven. Each of the subframes SF1 to SF8 is driven by being divided between the syringes and the light emission period.

During the syringe period, the scanning signals are sequentially supplied to the scanning lines S1 to Sn. The data signal is supplied to the data lines D1 to Dm so as to be synchronized with the scanning signal during the interval between the syringes. That is, during the syringe period, the pixels 40 to be turned on in response to the data signal are selected.

During the light emitting period, the pixels 40 emit or not emit light in response to the data signal supplied during the syringe period. Here, the intervals between the syringes are set equally during each subframe SF1 through SF8, while the light emission period is set differently in each subframe SF1 through SF8. For example, the light emission period is increased in the ratio of 2 ⁰ , 2 ¹ , 2 ² , 2 ³ , 2 ⁴ , 2 ⁵ , 2 ⁶ , 2 ⁷ in each subframe SF1 to SF8. That is, in the present invention, the pixels 40 display images of a predetermined gray level while being emitted or non-emitted in each of the subframes SF1 to SF8 included in one frame.

Meanwhile, in the present invention, each subframe SF1 to SF8 included in one frame 1F may be changed in various forms. For example, a reset period may be added to each subframe SF1 through SF8. In addition, the light emission period of each subframe SF1 to SF8 may be variously changed.

3 is a diagram illustrating a structure of a pixel illustrated in FIG. 1. In FIG. 3, for convenience of description, the pixel 40 connected to the n-th scan line Sn and the m-th data line Dm will be illustrated.

Referring to FIG. 3, a pixel of the present invention is connected to an organic light emitting diode OLED, a data line Dm, and a scanning line Sn to control pixel emission of the organic light emitting diode OLED. It is provided.

The anode electrode of the organic light emitting diode OLED is connected to the pixel circuit 42, and the cathode electrode is connected to the second power source ELVSS. The organic light emitting diode OLED emits or not emits light in units of subframes SF1 to SF8 in response to a current supplied from the pixel circuit 42.

The pixel circuit 42 controls whether the organic light emitting diode OLED emits light in response to the data signal supplied to the data line Dm when the scan signal is supplied to the scan line Sn. To this end, the pixel circuit 42 includes a second transistor M2 connected between the first power source ELVDD and the organic light emitting diode OLED, the second transistor M2, the data line Dm, and the scan line Sn. ) And a storage capacitor (C) connected between the gate electrode and the first electrode of the second transistor (M2).

The gate electrode of the first transistor M1 is connected to the scan line Sn, and the first electrode is connected to the data line Dm. The second electrode of the first transistor M1 is connected to one terminal of the storage capacitor. The first transistor M1 is turned on when the scan signal is supplied to the scan line Sn during each of the syringes of the subframes SF1 to SF8 to store the data signal supplied to the data line Dm. Supply to C). On the other hand, the first electrode is set to any one of the source electrode and the drain electrode, and the second electrode is set to a different electrode from the first electrode. For example, when the first electrode is set as the source electrode, the second electrode is set as the drain electrode.

The gate electrode of the second transistor M2 is connected to one terminal of the storage capacitor C, and the first electrode is connected to the other terminal of the storage capacitor C and the first power supply ELVDD. The second electrode of the second transistor M2 is connected to the organic light emitting diode OLED. The second transistor M2 controls whether the organic light emitting diode OLED emits light or not emits light in response to the voltage stored in the storage capacitor C. FIG. For example, when the voltage corresponding to the first data signal is charged to the storage capacitor C, the second transistor M2 supplies a predetermined current so that the organic light emitting diode OLED can emit light. When the voltage corresponding to the second data signal is charged in the storage capacitor C, the second transistor M2 does not supply a current so that the organic light emitting diode OLED may not be emitted.

4 is a diagram illustrating a circuit configuration of a shift register included in the data driver and / or the scan driver illustrated in FIG. 1, and FIG. 5 is a waveform diagram illustrating the operation of the shift register illustrated in FIG. 4.

Referring to FIG. 4, a shift register according to an embodiment of the present invention includes a transfer unit for storing an input signal in and outputting the same, and inverting and outputting the input signal after inverting the input signal. It is composed of an inversion unit, a pull-up transistor and a pull-down transistor, and a buffer unit for selecting and outputting a signal output from the transfer unit and the inverting unit.

More specifically, the shift register includes: a first PMOS transistor M1 receiving an input signal in and having a gate connected to the first clock terminal; A second PMOS transistor (M2) connected to a gate of the first clock terminal and connected between a first power supply (VDD) and a first node (N1); A third POMS transistor (M3) connected to an output terminal of the first PMOS transistor (M1) and connected between a second clock terminal and a first node (N1); A fourth PMOS transistor (M4) receiving the input signal (in) and having a gate connected to the first clock terminal; A fifth PMOS transistor M5 having a gate connected to the first clock terminal and connected between a second power supply VSS and a second node N2; A sixth POMS transistor (M6) connected to a gate of an output terminal of the fourth PMOS transistor (M4) and connected between a first clock terminal and a second node (N2); A seventh PMOS transistor M7 having a gate connected to the first clock terminal and connected between the first power supply VDD and the third node N3; An eighth PMOS transistor M8 having a gate connected to the second node and connected between the second clock terminal and the third node N3; A ninth PMOS transistor M9 connected to a gate of the first node N2 and connected between the second power supply VSS and an output terminal OUT; A gate is connected to the third node N3 and a tenth PMOS transistor M10 is connected between the first power source VDD and the output terminal OUT.

In addition, a first capacitor (C1) connected between the output terminal of the first PMOS transistor (M1) and the first node (N1); A second capacitor C2 connected between the first node N1 and the second power source VSS; A third capacitor C3 connected between the output terminal of the fourth PMOS transistor M4 and the second power supply VSS; A fourth capacitor C4 connected between the second node N2 and the third node N3; A fifth capacitor C5 connected between the third node N3 and the second power source VSS is further included.

The first and third capacitors C1 and C3 are data storage capacitors, and the second, fourth and fifth capacitors C2, C4 and C5 are precharge capacitors, which connect separate capacitors as shown. Not only can be implemented by using the parasitic capacitance of the transistor can be implemented.

As shown, the transfer part includes first, second, and three POMS transistors M1, M2, and M3 and first and second capacitors C1 and C2, and the inverting part includes fourth, fifth, sixth, seventh, and eighth times. PMOS transistors M4, M5, M6, M7, M8 and third, fourth, and fifth transistors C3, C4, C5, and the buffer part is composed of ninth, tenth PMOS transistors M9, M10.

The shift register composed of such a circuit is connected to a cascade to perform an operation of sequentially shifting the first input signal and outputting the input signal. Thus, the input signal in is the first start pulse SP or the previous one. It becomes the output signal of the stage.

In addition, in the case of an odd shift register among a plurality of shift registers connected to the cascade, a first clock signal CLK is supplied to the first clock terminal and a second clock signal (/ CLK) is supplied to the second clock terminal. In contrast, when the shift register is the even-numbered second, the second clock signal / CLK is supplied to the first clock terminal, and the first clock signal CLK is supplied to the second clock terminal.

In addition, a separate negative power may be applied to the second power source VSS, but may be configured to be grounded (GND) as shown.

In addition, the low level of the first clock signal CLK and the second clock signal / CLK may have a voltage lower than that of the second power supply VSS, thereby increasing an operation speed during a pull-down operation. do.

The operation of the shift register illustrated in FIG. 4 will be described with an example in which the first clock signal CLK is supplied to the first clock terminal and the second clock signal / CLK is supplied to the second clock terminal.

An operation of the shift register according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5 as follows.

First, when the first clock signal CLK is at a low level, the second clock signal / CLK is at a high level, and the input signal in is at a low level, the operation in the first section T1 is performed. , M2 is turned on, and since the low level input signal is transmitted to the gate of M3 by turning on M1, M3 is turned on.

Accordingly, the voltage corresponding to the difference between the input signal and the second clock signal / CLK input through the source of the M3 is stored in the C1, and the first power source VDD is turned on by the turn-on of the M2. It is delivered to the gate electrode of M9 contained in.

At this time, the C2 serves to stabilize the output of the transfer unit, and may be implemented using parasitic capacitance of the transistor as described above.

In addition, in the inverting unit, M4 and M7 are turned on. Accordingly, an input signal (in) is stored in C3, and the first power source VDD is supplied to the gate electrode of M10 included in the buffer unit by turning on the M7. Delivered. In this case, the C5 serves to stabilize the output of the transfer unit and may be implemented using parasitic capacitance of the transistor as described above.

By turning on the M4, a low level input signal is transmitted to the gate of M6 so that the M6 is turned on, and the M5 is also turned on so that the second node N2 has a low level voltage (the first clock signal CLK) or Second power supply (VSS) is formed.

On the other hand, a high level voltage (a second clock signal / CLK or a first power supply VDD) is formed at the third node N3 by turning on the M7 and M8.

Therefore, the voltage corresponding to the difference between the second node N2 and the third node N3, that is, a voltage independent of the input signal in is stored in the C4.

In addition, the M9 and M10 of the buffer unit are output by the transfer unit and the inverting unit, that is, the first power source VDD is applied to the gate electrodes of the M9 and M10, respectively, so that all are turned off. Accordingly, the output terminal OUT of the shift register is turned off. ) Becomes a high impedance state to maintain the output of the previous section.

That is, in the first section T1, the shift register is in a high impedance state maintaining the output of the previous section.

Next, when the first clock signal CLK is at the high level, the second clock signal / CLK is at the low level, and the input signal in is at the low level, the operation is performed in the second section T2. M1 and M2 are turned off, and M3 is turned on by the voltage stored in C1 through the first section T1.

Accordingly, the low level second clock signal / CLK input to the source of M3 is transmitted to the first node, and the low level voltage is transmitted to the gate electrode of M9 included in the buffer unit. That is, the voltage (low level) corresponding to the second clock signal becomes the output of the transfer unit.

In the inverting unit, M4, M5, and M7 are turned off, and M6 is turned on by the voltage stored in C3 through the first section T1.

Accordingly, the high level first clock signal CLK input to the source of M6 is transmitted to the gate of M8, and M8 is turned off. However, since the first clock signal CLK of the high level is transmitted to the second node N2 of C4, C4 connected between the second node N2 and the third node N3 is stored in the first section. The voltage is boosted and stored by the first clock signal. Accordingly, a high level voltage is formed at the third node N3 and transferred to the gate electrode of M10 included in the buffer unit. In other words, the high level voltage becomes the output of the inverting unit.

Accordingly, M9 of the buffer unit is turned on, M10 is turned off, and as a result, the second power source VSS of low level is output by the M9 to the output terminal OUT of the shift register.

That is, in the second section T2, the shift register is in a state of outputting a low level signal as shown in FIG.

Next, when the first clock signal CLK is at a low level, the second clock signal / CLK is at a high level, and the input signal in is at a high level, an operation of the third section T3 is performed. In this case, M1 and M2 are turned on, and since the high level input signal is transmitted to the gate of M3 by turning on M1, M3 is turned off.

Therefore, the voltage corresponding to the difference between the input signal and the first power source VDD input through the source of the M2 is stored in the C1, and the first power source VDD is included in the buffer unit by turning on the M2. Is delivered to the gate electrode of M9.

In addition, in the inverting unit, M4 and M7 are turned on. Accordingly, an input signal in is stored in C3, and the first power source VDD is transferred to the gate electrode of M10 included in the buffer unit by turning on the M7. do.

By turning on the M4, a high level input signal is transmitted to the gate of M6 and the M6 is turned off, but the M5 is turned on so that the second node N2 has a low level voltage (second power supply VSS). Is formed, and accordingly the M8 is turned on.

On the other hand, a high level voltage (a second clock signal / CLK or a first power supply VDD) is formed at the third node N3 by turning on the M7 and M8.

Therefore, the voltage corresponding to the difference between the second node N2 and the third node N3, that is, a voltage independent of the input signal in is stored in the C4.

In addition, the M9 and M10 of the buffer unit are both turned off by the output signal of the transfer unit and the inverting unit, and the output terminal OUT of the shift register is in a high impedance state to maintain the output of the previous section.

That is, in the third section T3, the shift register is in a high impedance state maintaining the output of the previous section T2.

Finally, when the first clock signal CLK is at the high level, the second clock signal / CLK is at the low level, and the input signal in is at the high level, the operation is performed in the fourth section T4. M1 and M2 are turned off, and M3 is turned off by the voltage stored in C1 through the third section T3. As a result, M1, M2, and M3 included in the transfer unit are all turned off.

In the inverting unit, M4, M5, and M7 are turned off, and M6 is turned off by the voltage stored in C3 through the first section T3.

However, M8 is turned on by the voltage stored in C4 through the third section T3, and thus a second clock signal / CLK of low level input to the source of M8 is transmitted to the third node. This is transferred to the gate electrode of M10 included in the buffer unit. That is, the low level voltage becomes the output of the inverting unit.

In addition, since M1, M2, and M3 of the transfer unit are all turned off, and the output terminal of the transfer unit is in a floating state, M9 of the buffer unit is turned off and M10 is turned on, thereby outputting to the output terminal OUT of the shift register. The first power source VDD having a high level is output by the M10.

That is, in the fourth section T4, the shift register is in a state of outputting a high level signal as shown in FIG.

Since the output of the shift register output through the first to fourth sections T1 to T4 as described above becomes an input signal of the shift register connected to the cascade, the plurality of shift registers connected in the cascade form. The output is shifted and continues to be output.

However, in the case of the even-numbered shift register, as described above, the second clock signal / CLK is supplied to the first clock terminal, and the first clock signal CLK is supplied to the second clock terminal.

As a result, the shift register having the circuit configuration of FIG. 4 has a high impedance output state when the first clock signal CLK is at a low level and the second clock signal / CLK is at a high level. That is, the output signal of the previous section is maintained while the first clock signal CLK is at the high level and the second clock signal / CLK is at the low level. It is characterized in that it has a 3-Stage output state that outputs the same waveform as.

6A to 6D are diagrams showing the circuit configuration of the shift register according to the second to fifth embodiments of the present invention.

However, the same reference numerals are used for the same components as those of the first embodiment of the present invention shown in FIG. 4, and the description of the operation of the circuit is the same as described above, and thus the description thereof will be omitted.

Referring first to FIG. 6A, the shift register circuit according to the second embodiment of the present invention removes the inverting portion M4 and compares the gate of M6 to the output terminal of M1 in comparison with the first embodiment shown in FIG. 4. It is composed. At this time. Since M1 and M4 of the first embodiment have the same signal and are inputted to the first clock terminal connected to the gate, the operation is the same even if M4 is removed as in the second embodiment.

However, when the number of transistors for input is reduced in this way, one side of C3 provided in the inverting unit of the first embodiment is connected to C1, and the other side is connected to ground (GND). In this case, the circuit having the above configuration When the output of the low level outputs the bootstrap operation by the voltage stored in the C1, as the output voltage is lowered, charge redistribution between the C1 and C3 occurs, the phenomenon that the voltage of the C1 is reduced 6A, the C3 is removed in the second embodiment of the present invention.

Next, referring to FIG. 6B, in the shift register circuit according to the third embodiment of the present invention, in comparison with the second embodiment of FIG. 6A, the input terminals of the transfer unit M2 and M3 are connected to the second clock terminal and inverted. The input terminals of the negative M7 and M8 are configured to be connected to the second clock terminal, and the operation thereof is the same as the first embodiment described with reference to FIGS. 4 and 5.

Next, referring to FIGS. 6C and 6D, the shift register circuits according to the third and fourth embodiments of the present invention remove M8 of the inverting unit as compared with the second embodiment according to FIG. 6A, respectively (FIG. 6C). In addition, a diode connection structure for connecting the gate and the drain to the first clock terminal with respect to M5 of the inverter is implemented (FIG. 6D), and the operation thereof is described with reference to FIGS. 4 and 5. Same as the embodiment.

7 is a waveform diagram showing the operation of another embodiment of the shift register according to the embodiment of the present invention.

However, the shift register is one of the shift registers shown in FIG. 4 or FIGS. 6A to 6D, and the first clock signal and the second clock signal are overlapped with each other at a high level in comparison with the waveform diagram of FIG. 5. There is a difference in that.

As an example, referring to the shift register circuit shown in FIG. 4 and FIG. 7, first, when the first and second clock signals CLK and / CLK are provided at a high level, the M1 controlled by the first clock signal CLK is controlled. , M2, M4, M5, M7 are all turned off, and M3 is turned on to store the second clock signal at high level in C2, or M3 is turned off to float C2, and M6 and / or M8 are turned on to be high. The level voltage is stored at C5, resulting in M9 and M10 turning off to maintain the output of the previous section.

That is, as long as the first clock signal CLK and the second clock signal / CLK overlap at the high level, the output signal waveform of the shift register maintains the output state of the previous section.

8 is a block diagram illustrating a data driver circuit according to an exemplary embodiment of the present invention, and FIG. 9 is a waveform diagram illustrating a method of driving the data driver circuit shown in FIG. 8.

However, it is assumed that the data driving circuit has n channels.

Referring to FIG. 8, a data driving circuit according to an embodiment of the present invention receives data, outputs a shift register unit 80 for shifting and outputting the received data, and simultaneously outputs data received from the shift register unit. It is configured to include a latch portion 90.

The shift register 80 is composed of 2n shift registers S / R1 to S / R2n connected in cascade, and the first shift register S / R1 receives a data signal, and the second to second nn The shift registers S / R2 to S / R2n receive the output signal of the previous shift register.

In addition, each shift register receives a first clock signal CLK and a second clock signal CLK. However, in the case of an odd shift register, the first clock signal CLK is applied to the first clock terminal clk. Is received, the second clock signal (/ CLK) is input to the second clock terminal (/ clk), and in the case of the even-numbered shift register, the second clock signal (/ CLK) is input to the first clock terminal (clk). The first clock signal CLK is input to the second clock terminal / clk.

FIG. 10 is a diagram illustrating a circuit configuration of a shift register included in the shift register shown in FIG. 8.

This is the same as the circuit configuration of the shift register shown in FIG. 6C, and thus the operation thereof is the same as previously described with reference to FIGS. 4 and 7.

That is, the odd shift registers maintain the high impedance output state, that is, the output of the previous section, when the first clock signal CLK is low level and the second clock signal / CLK is high level. When the first clock signal CLK is at a high level and the second clock signal / CLK is at a low level, the same waveform as the input signal stored in the previous section is output.

Further, the even-numbered shift registers maintain a high impedance output state, that is, a previous section output when the second clock signal / CLK is at a low level and the first clock signal CLK is at a high level. When the second clock signal / CLK is at the high level and the first clock signal CLK is at the low level, the second waveform signal / CLK is input in the previous section and outputs the same waveform as the stored input signal.

However, when both of the first clock signal CLK and the second clock signal / CLK are high level, the output state of the previous section is maintained.

Referring to FIGS. 9 and 10, the output signal S [1] by the first shift register S / R1 will be described. When the data signal a1 is input, the second clock signal / CLK is first output. The data signal a1 is output during the low level and the first clock signal CLK is at a high level, the second clock signal / CLK is at a high level, and the first clock signal CLK is at a low level. Since the level is a high impedance state, the output of the previous section is maintained and the output of the data signal a1 is maintained. In addition, the data signal a1 is also maintained and output in a section in which both the first and second clock signals are high level.

Thereafter, even when the data signal a2 to the data signal an are input, the data signals a2 to an are sequentially output as shown in FIG. 10.

On the other hand, since the second shift register S / R2 is an even-numbered shift register and receives the output signal of the first shift register S / R1, the second shift register S / R2 receives a data signal from the first shift register S / R1. When a1) is input, the data signal a1 is output in a period where the first clock signal CLK is at a low level and the second clock signal / CLK is at a high level, and the first clock signal CLK is output. Is a high level and the second clock signal / CLK is at a low level, so the output of the previous section is maintained because the output of the previous section is maintained. In addition, the data signal a1 is also maintained and output in a section in which both the first and second clock signals are high level.

Thereafter, even when the data signals a2 to an are input, the data signals a2 to an are sequentially output as shown in FIG. 9.

The above operation is performed in the same manner as the remaining odd-numbered shift registers S / R3 to S / R2n-1, and the even-numbered shift registers S / R4 to S / R2n are the same as shown in FIG. Outputs

Accordingly, the latch unit 90 is composed of n latches for inputting the output of the odd shift register among the outputs of the 2n shift registers constituting the shift register 80, respectively, from the odd shift register unit. It outputs the data received at the same time.

At this time, the data input to the latch unit 90 is n data corresponding to n channels, that is, a1 to an, for example.

That is, the first latch 1 receives the output S [1] of the first shift register S / R1, and the second latch 2 receives the output of the third shift register S / R3. The output S [3] is input, and the nth latch Latch n receives the output S [2n-1] of the second n-1 shift register S / R2n-1.

In addition, each latch receives the first enable signal EN1 and the second enable signal EN2, and in this case, the first enable is performed by the first clock terminal clk without distinguishing the odd or even latch. The signal EN1 is input, and the second enable signal EN2 is input to the second clock terminal / clk.

FIG. 11 is a diagram illustrating a circuit configuration of the latch provided in the latch unit illustrated in FIG. 8.

This is the same as the circuit configuration of the shift register shown in FIG. 6C, and thus the operation thereof is the same as previously described with reference to FIGS. 4 and 7.

That is, the latches maintain the high impedance output state, that is, the output of the previous section, when the first enable signal EN1 is low level and the second enable signal EN2 is high level. When the enable signal EN1 is at a high level and the second enable signal EN2 is at a low level, an operation of outputting the same waveform as the input signal stored in the previous section is performed.

9 and 11, 2n-1 during a period in which respective signals a1 to an corresponding to n channels are output (S [1] to S [2n-1]) through the odd shift registers. For the period until a1 is output by the shift register, as shown in FIG. 9, the first enable signal EN1 maintains a high level, and the second enable signal EN2 maintains a low level. Thus, the initialization voltage previously stored in each latch is outputted through each latch.

In the example shown in Fig. 9, each latch outputs a low level during the period, regardless of the data received.

Accordingly, when a1 is output by the 2n-1 shift register, the first enable signal EN1 is provided at a low level and the second enable signal is provided at a high level in response thereto. As such, the first enable signal EN1 is provided. For a period in which N) is at a low level and a second enable signal is at a high level, each latch stores a data signal input in the period, after which the first enable signal EN1 is at a high level, a second level. When the enable signal EN2 is at the low level, the voltage corresponding to the stored data signal is simultaneously output.

That is, the first latch 1 stores an data as shown during the period in which the first enable signal EN1 is provided at the low level and the second enable signal is at the high level. When the enable signal EN1 becomes high level and the second enable signal EN2 becomes low level, a voltage corresponding to the stored data signal an is output.

Similarly, the second to nth latches Latch 2 to Latch n may each have an-1 to a1 as shown during the period in which the first enable signal EN1 is provided at a low level and the second enable signal is provided at a high level. Storing the data, and then the voltage corresponding to the stored data signals an-1 to a1 when the first enable signal EN1 becomes high level and the second enable signal EN2 becomes low level. Will output simultaneously.

However, in the operation of the data driving circuit described above, the low level of the first clock signal CLK1 and the second clock signal CLK2 and the first enable signal EN1 or the second enable signal EN2 is The voltage lower than the second power supply VSS is preferable.

12 is a diagram illustrating a circuit configuration according to another embodiment of a shift register included in the shift register shown in FIG. 8, and FIG. 13 is a waveform diagram illustrating a method of driving a data driver circuit according to another embodiment of the present invention. to be.

However, the shift register part is composed of 2n shift registers S / R1 to S / R2n connected in cascade, and the first shift register S / R1 receives a data signal and the second to second n shift registers. (S / R2 ~ S / R2n) receives the output signal of the previous shift register.

In addition, each shift register receives a first clock signal CLK and a second clock signal CLK. However, in the case of an odd shift register, the first clock signal CLK is applied to the first clock terminal clk. Is received, the second clock signal (/ CLK) is input to the second clock terminal (/ clk), and in the case of the even-numbered shift register, the second clock signal (/ CLK) is input to the first clock terminal (clk). The first clock signal CLK is input to the second clock terminal / clk.

Referring to FIG. 12, the shift register S / R according to another embodiment of the present invention receives an input signal (data signal or previous stage output signal) and an eleventh transistor having a gate electrode connected to the first clock terminal. M11, the twelfth transistor M12 connected between the eleventh transistor M11 and the output terminal out, the fourteenth transistor M14 connected between the first clock terminal and the second power supply VSS, and A capacitor connected between the thirteenth transistor M13, the fifteenth transistor M15 connected between the first power supply VDD, and the output terminal out, and the gate electrode and the second electrode of the twelfth transistor M12. (C11) is provided. Herein, the eleventh transistors M11 to 15th transistor M15 are formed of PMOS. In addition, the first power supply VDD is set to a higher voltage value than the second power supply VSS.

The first electrode of the eleventh transistor M11 receives an input signal, that is, a data signal or a previous output signal. The gate electrode of the eleventh transistor M11 is connected to the first clock terminal, and the second electrode is connected to the first node N1. The eleventh transistor M11 is turned on or off in response to the first clock signal CLK or the second clock signal / CLK supplied to the first clock terminal.

The gate electrode of the twelfth transistor M12 is connected to the first node N1, and the first electrode is connected to the second clock terminal. The second electrode of the twelfth transistor M12 is connected to the output terminal out. The twelfth transistor M12 is turned on or turned off in response to the voltage applied to the first node N1.

The first electrode of the thirteenth transistor M13 is connected to the second node N2, and the second electrode is connected to the second power source VSS. The gate electrode of the thirteenth transistor M13 is connected to the first clock terminal. The thirteenth transistor M13 is turned on or off in response to the first clock signal CLK or the second clock signal / CLK supplied to the first clock terminal.

The first electrode of the fourteenth transistor M14 is connected to the first clock terminal, and the second electrode is connected to the second node N2. The gate electrode of the fourteenth transistor M14 is connected to the first node N1. The fourteenth transistor M14 is turned on or turned off in response to the voltage applied to the first node N1.

The first electrode of the fifteenth transistor M15 is connected to the first power source VDD, and the second electrode is connected to the output terminal out. The gate electrode of the fifteenth transistor M15 is connected to the second node N2. The fifteenth transistor M15 is turned on or turned off in response to the voltage applied to the second node N2.

The capacitor C11 is connected between the gate electrode and the second electrode of the twelfth transistor M12. The capacitor C11 charges a voltage corresponding to the input signal applied to the first node N1 when the eleventh transistor M11 is turned on.

An operation process will be described on the assumption that the shift register S / R shown in FIG. 12 is the first shift register S / R1.

First, assuming that the first clock signal CLK is at a low level, the second clock signal / CLK is at a high level, and a low level input signal is input, the first clock signal CLK at a low level is applied. The eleventh transistor M11 and the thirteenth transistor M13 that are input are turned on. When the eleventh transistor M11 is turned on, an input signal is supplied to the first node N1. In this case, the twelfth transistor M12 and the fourteenth transistor M14 are turned on.

When the fourteenth transistor M14 is turned on, the low level first clock signal CLK is input to the second node N2. When the thirteenth transistor M13 is turned on, the second power source VSS is input to the second node N2. In this case, the fifteenth transistor M15 is turned on so that the voltage of the first power source VDD is supplied to the output terminal out. On the other hand, when the twelfth transistor M12 is turned on, the second clock signal / CLK of high level is supplied to the output terminal out.

At this time, the capacitor C11 is charged with a voltage corresponding to the difference between the first node N1 and the output terminal out. In other words, the voltage corresponding to the difference between the low voltage of the input signal and the first power source VDD is charged in the capacitor C11.

Thereafter, when it is assumed that the first clock signal CLK is switched to the high level and the second clock signal / CLK is turned to the low level and the supply of the input signal is stopped, the first clock signal CLK of the high level is input. The eleventh transistor M11 and the thirteenth transistor M13 are turned off. At this time, the first node N1 is set at a low level in response to the voltage charged in the capacitor C11. Then, the twelfth transistor M12 is turned on so that the voltage of the output terminal out is reduced to the low level voltage of the second clock signal / CLK. That is, as shown in Fig. 10, the data signal a1 as an input signal is output.

On the other hand, when the voltage of the first node N1 is set to the low level, the fourteenth transistor M14 is turned on. When the fourteenth transistor M14 is turned on, the first clock signal CLK having a high level is supplied to the second node N2 to turn off the fifteenth transistor M15.

Thereafter, when the second clock signal / CLK is switched to the high level and the first clock signal CLk is turned to the low level, the eleventh transistor M11 and the thirteenth received the first clock signal CLK at the low level. Transistor M13 is turned on. When the thirteenth transistor M13 is turned on, the voltage of the second power supply VSS is supplied to the second node N2, and the fifteenth transistor M15 is turned on. The voltage of one power supply VDD is supplied.

When the eleventh transistor M11 is turned on, a high level voltage is supplied to the first node N1. Then, the capacitor C11 does not charge the voltage. Therefore, even if the phases of the next clock signals CLK1 and CLK2 are reversed, the second transistor M2 and the fourth transistor M4 remain turned off, and thus the shift register S / R is in a high state. Keep the output of

When the first and second clock signals overlap each other at a high level, the first and second clock signals CLK1 and CLK2 overlap each other at a high level. It is characterized in that the output.

As a result, the odd-numbered shift register of the shift register illustrated in FIG. 12 outputs a high level as a precharge period when the first clock signal CLK is at a low level and the second clock signal / CLK is at a high level. When the first clock signal CLK is at a high level and the second clock signal / CLK is at a low level, an operation of outputting the same waveform as the input signal stored in the previous section is performed.

The even-numbered shift registers output a high level as a precharge period when the second clock signal / CLK is at a low level and the first clock signal CLK is at a high level, and the second clock signal / CLK is outputted. When the high level and the first clock signal CLK are at the low level, the same waveform as the input signal stored in the previous section is output.

However, when the first clock signal CLK and the second clock signal / CLK are both at a high level, a high level is output and a time interval is provided at each output of the shift register.

Referring to FIGS. 12 and 13, when the output signal S [1] by the first shift register S / R1 is described, first, when the data signal a1 is input, the second clock signal / CLK is generated. The data signal a1 is output during the low level and the first clock signal CLK is at a high level, the second clock signal / CLK is at a high level, and the first clock signal CLK is at a low level. The section which is a level outputs a high level as a precharge section. In addition, a high level is also output in a period where both the first and second clock signals are high level.

Thereafter, even when data signals a2 to an data signal are input, the data signals a2 to an are output at a predetermined interval as shown in FIG. 13.

On the other hand, since the second shift register S / R2 is an even-numbered shift register and receives the output signal of the first shift register S / R1, the second shift register S / R2 receives a data signal from the first shift register S / R1. When a1) is input, the data signal a1 is output in a period where the first clock signal CLK is at a low level and the second clock signal / CLK is at a high level, and the first clock signal CLK is output. Is a high level, and the section in which the second clock signal / CLK is at a low level outputs a high level as a precharge section. In addition, a high level is also output in a section in which both the first and second clock signals are high level.

Thereafter, even when data signals a2 to an data signal are input, the data signals a2 to an are output at a predetermined interval as shown in FIG. 13.

The above operation is performed in the same manner as the remaining odd-numbered shift registers S / R3 to S / R2n-1 and the even-numbered shift registers S / R4 to S / R2n. Outputs

Accordingly, the latch unit is composed of n latches each of which outputs an odd-numbered shift register as an input among the outputs of the 2n shift registers constituting the shift register unit, and simultaneously outputs data respectively received from the odd-numbered shift register unit. Do this.

At this time, the data input to the latch unit is n data corresponding to n channels, that is, a1 to an, for example.

That is, the first latch 1 receives the output S [1] of the first shift register S / R1, and the second latch 2 receives the output of the third shift register S / R3. The output S [3] is input, and the n-th latch Latch n receives the output S [2n-1] of the second n-1 shift register S / R2n-1.

In addition, each latch receives the first enable signal EN1 and the second enable signal EN2, and in this case, the first enable is performed by the first clock terminal clk without distinguishing the odd or even latch. The signal EN1 is input, and the second enable signal EN2 is input to the second clock terminal / clk.

The configuration and operation of the latch unit are the same as described above with reference to FIGS. 9 and 11.

That is, the latches maintain the high impedance output state, that is, the output of the previous section, when the first enable signal EN1 is low level and the second enable signal EN2 is high level. When the enable signal EN1 is at a high level and the second enable signal EN2 is at a low level, an operation of outputting the same waveform as the input signal stored in the previous section is performed.

Referring to FIGS. 11 and 13, 2n-1 of a period during which signals a1 to an corresponding to n channels are output (S [1] to S [2n-1]) through the odd shift registers. For the period until a1 is output by the shift register, as shown in FIG. 10, the first enable signal EN1 maintains a high level, and the second enable signal EN2 maintains a low level. Thus, the initialization voltage previously stored in each latch is outputted through each latch.

According to the example shown in FIG. 13, during the period, each latch outputs a low level regardless of input data.

Accordingly, when a1 is output by the 2n-1 shift register, the first enable signal EN1 is provided at a low level and the second enable signal is provided at a high level in response thereto. As such, the first enable signal EN1 is provided. For a period in which N) is at a low level and a second enable signal is at a high level, each latch stores a data signal input in the period, after which the first enable signal EN1 is at a high level, a second level. When the enable signal EN2 is at the low level, the voltage corresponding to the stored data signal is simultaneously output.

That is, the first latch 1 stores an data as shown during the period in which the first enable signal EN1 is provided at the low level and the second enable signal is at the high level. When the enable signal EN1 becomes high level and the second enable signal EN2 becomes low level, a voltage corresponding to the stored data signal an is output.

Similarly, the second to nth latches Latch 2 to Latch n may each have an-1 to a1 as shown during the period in which the first enable signal EN1 is provided at a low level and the second enable signal is provided at a high level. Storing the data, and then the voltage corresponding to the stored data signals an-1 to a1 when the first enable signal EN1 becomes high level and the second enable signal EN2 becomes low level. Will output simultaneously.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims.

Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, the shift register, the data driver, and the organic light emitting display device using the same according to the embodiment of the present invention can be mounted on a panel because the shift registers and latches included in the data driver are composed of only PMOS transistors. Accordingly, there is an advantage that can reduce the manufacturing cost. Further, in the present invention, since the first data signal or the second data signal is supplied as the data signal, the present invention can be applied to an organic electroluminescence display device of digital driving.

Claims (26)

A transfer unit which receives the first and second clock signals CLK and / CLK and an input signal in, stores the input signal in, and outputs the input signal in; An inversion unit which receives the first and second clock signals CLK and / CLK and an input signal in, stores the input signal, and then inverts and outputs the input signal; And a buffer unit comprising a pull-up transistor and a pull-down transistor to select and finally output a signal output from the transfer unit and the inverter. The method of claim 1, wherein the delivery unit, A first transistor M1 receiving an input signal in and having a gate connected to the first clock terminal; A second transistor (M2) connected to a gate of the first clock terminal and connected between a first power supply (VDD) or a second clock terminal and a first node (N1); And a third transistor (M3) connected to an output terminal of the first transistor (M1) and connected between a second clock terminal and a first node (N1). The method of claim 2, wherein the delivery unit, A first capacitor C1 connected between the output terminal of the first transistor M1 and the first node N1; The shift register further comprises a second capacitor (C2) connected between the first node (N1) and the second power source (VSS). The method of claim 1, wherein the inversion unit, A fourth transistor (M4) receiving the input signal (in) and having a gate connected to the first clock terminal; A fifth transistor M5 having a gate connected to the first clock terminal and connected between a second power supply VSS and a second node N2; A sixth transistor (M6) connected to an output terminal of the fourth transistor (M4) and connected between a first clock terminal and a second node (N2); A seventh transistor M7 having a gate connected to the first clock terminal and connected between the first power supply VDD or the second clock terminal and the third node N3; And a eighth transistor (M8) connected between the second clock terminal and the third node (N3), the gate being connected to the second node. The method of claim 4, wherein the inversion unit, A third capacitor C3 connected between the output terminal of the fourth transistor M4 and the second power supply VSS; A fourth capacitor C4 connected between the second node N2 and the third node N3; And a fifth capacitor (C5) further connected between the third node (N3) and the second power source (VSS). The method of claim 2, wherein the inversion unit, A fifth transistor M5 having a gate connected to the first clock terminal and connected between the second power supply VSS and the second node N2; A sixth transistor (M6) connected to an output terminal of the first transistor (M1) and connected between a first clock terminal and a second node (N2); And a eighth transistor (M8) connected between the second clock terminal and the third node (N3), the gate being connected to the second node. The method of claim 6, wherein the inversion unit, And a seventh transistor (M7) connected to a gate of the first clock terminal and connected between a first power supply (VDD) or a second clock terminal and a third node (N3). The method of claim 6, wherein the inversion unit, A fourth capacitor C4 connected between the second node N2 and the third node N3; And a fifth capacitor (C5) further connected between the third node (N3) and the second power source (VSS). delete The method of claim 1, The shift register is a plurality of shift registers are connected in cascade form, characterized in that for shifting the first input signal sequentially output shift register. The method of claim 10, The input signal (in) is a shift register, characterized in that the first start pulse (SP) or the output signal of the previous stage. The method of claim 10, In the case of an odd shift register among a plurality of shift registers connected to the cascade, a first clock signal CLK is supplied to a first clock terminal, and a second clock signal / CLK is supplied to a second clock terminal. Shift register. The method of claim 10, In the case of the even shift register among the shift registers connected to the cascade, the second clock signal / CLK is supplied to the first clock terminal, and the first clock signal CLK is supplied to the second clock terminal. Shift register. The method of claim 13, When the second clock signal / CLK is supplied at a low level and the first clock signal CLK is supplied at a high level, the second clock signal / CLK maintains the output of the previous section as a high impedance output state and the second clock signal / CLK Is a high level and the first clock signal CLK is supplied at a low level, and the shift register outputs the same waveform as the input signal stored in the previous section. In a data driving circuit for outputting a data signal to each of n channels, A shift register unit configured to receive first and second clock signals and data, and to shift and output the received data; And a latch unit for receiving first and second enable signals and simultaneously outputting data received from the shift register unit. The method of claim 15, The shift register part is composed of 2n shift registers S / R1 to S / R2n connected in cascade, and the first shift register S / R1 receives a data signal and the second to second n shift registers S / R2 ~ S / R2n) is a data drive circuit characterized in that receives the output signal of the previous shift register. The method of claim 16, The shift register receives a first and second clock signals CLK and / CLK and an input signal (a data signal or an output signal of a previous shift register) to store the input signal and then output the same. Wow; An inversion unit which receives the first and second clock signals CLK and / CLK and an input signal in, stores the input signal, and then inverts and outputs the input signal; And a buffer unit including a pull-up transistor and a pull-down transistor to select and output a signal output from the transfer unit and the inverter. The method of claim 16, The odd-numbered shift register of the 2n shift registers receives the first clock signal CLK through the first clock terminal clk and receives the second clock signal / CLK through the second clock terminal / clk. The even-numbered shift register receives the second clock signal / CLK through the first clock terminal clk and the first clock signal CLK through the second clock terminal / clk. Driving circuit. The method of claim 18, When the first clock signal CLK is input at the low level and the second clock signal / CLK is input at the high level, the odd-numbered shift registers maintain the output of the previous section as a high impedance output state. And when the clock signal CLK is input at the high level and the second clock signal / CLK is input at the low level, the data driving circuit outputs the same waveform as the input signal stored in the previous section. The method of claim 18, The even-numbered shift registers maintain the output of the previous section as a high impedance output state when the second clock signal / CLK is input at a low level and the first clock signal CLK is at a high level. And when the clock signal / CLK is at a high level and the first clock signal CLK is at a low level, the same waveform as the input signal stored in the previous section is output. The method of claim 19 or 20,  And when the first clock signal CLK and the second clock signal / CLK are both at a high level, the output state of the previous section is maintained. The method of claim 16, The latch unit is composed of n latches each of which outputs an odd shift register among the outputs of the 2n shift registers constituting the shift register unit, and simultaneously outputs data respectively inputted from the odd shift register unit. A data drive circuit, characterized in that. The method of claim 22, The latches may include: a transfer unit configured to receive first and second enable signals EN1 and EN2 and a data signal output from an odd-numbered shift register, store the data signal, and output the same; An inversion unit which receives the data signals output from the first and second enable signals EN1 and EN2 and the odd shift register, stores the data signals, and inverts them to output the data signals; And a buffer unit including a pull-up transistor and a pull-down transistor to select and output a signal output from the transfer unit and the inverter. The method of claim 23, wherein And the first enable signal (EN1) is input to the first clock terminal, and the second enable signal is input to the second clock terminal. The method of claim 22, The latches maintain the output of the previous section as a high impedance output state when the first enable signal EN1 is low level and the second enable signal EN2 is high level, and the first enable signal is maintained. And (EN1) a high level and a second enable signal (EN2) at a low level, outputting the same waveform as the input signal input and stored in the previous section. In an organic light emitting display device driven digitally, A scan driver for sequentially supplying scan signals to scan lines; A data driver for supplying a first data signal or a second data signal to each of the data lines; And a pixel selected when the scan signal is supplied and controlled to emit light by receiving the first data signal or the second data signal, The data driver, A shift register unit configured to receive first and second clock signals and data, and to shift and output the received data; And a latch unit configured to receive first and second enable signals and to simultaneously output data received from the shift register unit.

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