KR100736855B1 - Level translator in ddc communication module adopting iic communication protocol - Google Patents

Abstract

A level converter within a DDC(Display Data Channel) communication module adopting an IIC(Inter Integrated Circuit) communication protocol is provided to enable a PC host apparatus, which performs a high voltage IIC communication, to drive an AV display unit, which performs a low voltage IIC communication and to enable an AV host apparatus, which performs the low voltage IIC communication, to drive a PC display unit, which performs the high voltage IIC communication. A level converter within a DDC(Display Data Channel) communication module adopting an IIC(Inter Integrated Circuit) communication protocol comprises low voltage pull-up elements(Rp1-Rp2), high voltage pull-up elements(Rp3-Rp4), and transistor-diode pairs(TR1-TR2). The low voltage pull-up elements(Rp1-Rp2) are connected between low voltage supplying ports and low voltage transmission or receipt ports. The high voltage pull-up elements(Rp3-Rp4) are connected between high voltage supplying ports and high voltage transmission or receipt ports. The transistor-diode pairs(TR1-TR2) are connected between the low voltage transmission or receipt ports and the high voltage transmission or receipt ports. The transistor-diode pairs turn on/off according to voltage levels of the low voltage transmission or receipt ports and the high voltage transmission or receipt ports.

Description

Level translator in DDC communication module adopting IIC communication protocol

1 is a timing diagram for explaining an Inter-Integrated Circuit (IIC) communication protocol.

FIG. 2 is a block diagram illustrating a first digital visual interface (DVI) system including a 5 volt (V) standard display data channel (DDC) communication module.

FIG. 3 is a block diagram illustrating a second digital visual interface (DVI) system including an 3.3 V (V) standard IIC communication module.

4 is a circuit diagram illustrating a level converter according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a third digital visual interface (DVI) system using the level converter of FIG. 4.

FIG. 6 is a block diagram illustrating a fourth digital visual interface (DVI) system using the level converter of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

SDA ... serial data signal, SCL ... serial clock signal,

21 ... PC host device, 211,311 ... TMDS transmitter,

212,312 ... Graphic Control Unit, DVI1 ... First DVI,

DVI2 ... 2nd DVI, DVI3 ... 3rd DVI,

DVI4 ... 4th DVI, 22 ... PC Display Unit, 221,321 ... TMDS Receiver, 222,322 ... Serial EEPROM, 31 ... AV Host Device,

TMDS3.3V ... TMDS communication lines,

DDC communication module of DDC5V ... 5V (V) specification,

DDC 3.3 V ... 3.3 V DDC communication module,

SDA1 _IN , SDA2 _IN ... serial data input terminals,

SDA1 _OUT , SDA2 _OUT ... serial data output terminals,

SCL1 _IN , SCL2 _IN ... serial clock input terminals,

SCL1 _OUT , SCL2 _OUT ... serial clock output terminals,

EI1, EI2 ... IIC interface, TL _D ... serial data transmission line,

TL _C ... serial clock transmit and receive lines, 41 ... level converter,

R _P1 , R _P2 ... low voltage pull-up resistor elements, R _P3 , R _P4 ... high voltage pull-up resistor elements,

TR1, TR2 ... transistor-diode pairs, T _{D3 .3} , T _{C3 .3} ... low voltage transmit and receive terminals,

T _D5 , T _C5 ... high voltage transmit and receive terminals, V _DD1 = 3.3 V ... low voltage _accept terminals,

V _DD2 = 5V ... high voltage applying terminals,

DDC3.3 / 5V ... 3.3 / 5V (V) DDC communication module,

DDC5 / 3.3V ... DDC communication module with 5 / 3.3 Volt (V) specification.

The present invention relates to a level converter, and more particularly, IIC (Inter-Integrated Circuit, less than I ² C referred to) (Display Data Channel) that employs communication protocol DDC the low voltage receiving terminal in the communication module and high voltage transmission and reception A level converter is connected between the terminals.

In a DDC communication module employing an I ² C communication protocol, an example of a DDC communication module that typically does not have a level translator is US Publication No. 2003-0053172 filed by the present applicant (name of the invention: Optical communication interface module connected). to electrical communication interface module of I ² C communication protocol).

1 shows waveforms for describing an I ² C communication protocol.

Referring to FIG. 1, the I ² C communication protocol is used to perform serial communication by removing two channels of a control signal and performing only two channels of a serial data signal (SDA) and a serial clock signal (SCL) in a typical serial communication protocol. Protocol. According to this I ² C communication protocol, the state of the serial data signal SDA is set whenever the serial clock signal SCL becomes a logic '1' (high voltage level).

While the serial clock signal SCL is logic '1', the time t1 at which the serial data signal SDA falls from logic '1' to logic '0' (low voltage level) is one data package. ) Is the starting point. In addition, at a time t14 at which the serial data signal SDA rises from logic '0' to logic '1' while the serial clock signal SCL is a logic '1' (high voltage level), one data package. It is the end point of (packet). Therefore, at times t1 to t14 of one data package, the logic of the serial data signal SDA should not be switched while the corresponding serial clock signal SCL is logic '1'.

At time t2 to t3 where the serial clock signal SCL is logic '1', data '1' at t4 to t5, data '0' at t6 to t7, and data '0' at t6 to t7, and t8 to t9 Data '1' is sequentially transmitted or received at time t10 to t11 and data '0' at time t12 to t13.

2 shows a first Digital Visual Interface (DVI) system (DVI1) including a 5 volt (V) standard DDC communication module (DDC5V). The first DVI system DVI1 that does not perform encryption / decryption includes a transition minimized differential signaling (TMDS) transmitter 211, a graphic controller 212, and TMDS communication lines TMDS3 in the personal computer (PC) host device 21. .3V), 5-volt (V) standard DDC communication module (DDC5V), TMDS receiver 221 in PC display device 22 and serial EEPROM (Electrically Erasable and Programmable Read Only Memory) 222.

The configuration information and the control information of the PC display device 22 are stored in the serial EEPROM 222 in the PC display device 22. The graphic control unit 212 in the PC host device 21 reads configuration information and control information stored in the serial EEPROM 222 in the PC display device 22 through I ² C communication, and according to the read information, TMDS The operation of the transmitter 211 is controlled. Accordingly, the TMDS transmitter 211 transmits display data and control data to the TMDS receiver 221 through TMDS communication lines TMDS3.3V.

A 5 volt (D) compliant DDC communication module (DDC5V) employing an I ² C communication protocol provides I ² C interfaces (EI1, EI2), serial data transmit and receive lines (TL _D ), and serial clock transmit and receive lines (TL _C). ).

Via the serial data transmit and receive lines I ² C interface that is connected to the _{(TL D) (EI1, EI2} ) , each of the serial data output terminal serial data transmission line (TL _D) the serial data from the (SDA1 _OUT, SDA2 _OUT) opponent transmitting the I ² C interface (EI1, EI2) and allowed to input the serial data from the serial data transmission line (TL _D) to the serial data input terminal _(iN SDA1, SDA2 _iN).

Likewise, the serial clock transmission line of the I ² C interface that is connected to the _{(TL C) (EI1, EI2} ) , each serial clock output terminal of the clock signal, the serial clock transmission line (TL _C) from (SCL1 _OUT, SCL2 _OUT) It transmits to the counterpart I ² C interface (EI1, EI2) through the clock signal from the serial clock transmission and reception line (TL _C ) to the serial clock input terminals (SCL1 _IN , SCL2 _IN ).

Figure 3 shows a second DVI system (DVI2) including a 3.3V (V) standard DDC communication module (DDC3.3V). The second DVI system DVI2 that performs encryption / decryption includes the TMDS transmitter 311, the graphic controller 312, the TMDS communication lines TMDS3.3V, I ^{2 in the} audio-video host device 31. A 3.3 volt (V) standard DDC communication module (DDC3.3V) employing the C communication protocol, a TMDS receiver 321 in the AV display device 32, and a serial EEPROM 322 are included.

In the serial EEPROM 322 in the AV display device 32, configuration information and control information of the AV display device 32 are stored. The graphic control unit 312 in the AV host device 31 reads configuration information and control information stored in the serial EEPROM 322 in the AV display device 32 via I ² C communication, and TMDS according to the read information. The operation of the transmitter 311 is controlled. Accordingly, the TMDS transmitter 311 transmits display data and control data to the TMDS receiver 321 through TMDS communication lines TMDS3.3V.

The 3.3 volt (V) compliant DDC communication module (DDC3.3V), which is involved in performing the encryption / decryption, includes the I ² C interfaces (EI1, EI2), serial data transmit and receive lines (TL _D ), and serial clock transmit and receive lines ( TL _C ). Since the configuration and operation of the 3.3 volt (V) standard DDC communication module (DDC 3.3 V) are the same as those of the 5 volt (V) standard DDC communication module (DDC5V), the description thereof is omitted.

According to the conventional DVI systems as described above, the AV display device (32 in FIG. 3) cannot be driven by the PC host device (21 in FIG. 2) because the operating voltage of the I ² C communication does not match. There is a problem that the PC display device 22 cannot be driven by the AV host device (31 in FIG. 3).

An object of the present invention, and by the PC host apparatus of the high voltage I ² C communication, the AV display device with a low voltage I ² C communication can be driven, the high voltage I ² C communication by the AV host device on the low voltage I ² C communication PC It is to provide a level converter in a display data channel (DDC) communication module that enables a display device to be driven.

The level converter of the present invention for achieving the above object is connected between the low voltage transmission and reception terminals and the high voltage transmission and reception terminals in the DDC communication module employing the I ² C communication protocol to convert the low voltage signals of the low voltage transmission and reception terminals into high voltage signals. Applying to the high voltage transmission / reception terminals and converting the low voltage signals of the low voltage transmission / reception terminals into high voltage signals to the high voltage transmission / reception terminals, wherein the low voltage pull-up devices, the high voltage pull-up devices, and the transistors are applied. Contains diode pairs.

The low voltage pull-up elements are connected between low voltage applying terminals and the low voltage transmitting and receiving terminals, respectively. The high voltage pull-up elements are connected between high voltage applying terminals and the high voltage transmitting and receiving terminals, respectively. The transistor-diode pairs are connected between the low voltage transmit and receive terminals and the high voltage transmit and receive terminals, respectively. The transistor-diode pairs are turned on / off according to the potentials of the low voltage transceiver terminals and the high voltage transceiver terminals.

According to the level converter of the present invention, when any one of the low voltage transmit and receive terminals is a low voltage logic high state, the transistor-diode pair corresponding to the low voltage transmit and receive terminal is turned off, and the low voltage transmit and receive The high voltage transmission / reception terminal is in a high voltage logic high state through the high voltage pull-up element corresponding to the terminal.

Similarly, when any one of the high voltage transmit / receive terminals is in a high voltage logical high state, the transistor-diode pair corresponding to the high voltage transmit / receive terminal is turned off, and the low voltage corresponding to the high voltage transmit / receive terminal is turned off. The low voltage transmission / reception terminal is brought to a low voltage logic high state through the pull-up element.

Meanwhile, when any one of the low voltage transmit / receive terminals is in a low voltage logic low state, the transistor-diode pair corresponding to the low voltage transmit / receive terminal is turned on, so that the high voltage transmit / receive terminal corresponding to the low voltage transmit / receive terminal is turned on. Enters the high voltage logic low state.

In addition, when any one of the high voltage transceiver terminals is in a high voltage logic low state, the transistor-diode pair is turned on due to the action of the diode of the transistor-diode pair corresponding to the high voltage transceiver. The low voltage transmission / reception terminal corresponding to the high voltage transmission / reception terminal is in a low voltage logic low state.

Therefore, according to the level converter of the present invention, the AV display of I ² C communication of low voltage, for example 3.3 V, by the PC host device of I ² C communication of high voltage, for example 5 volts (V). The device can be driven. Conversely, by the host device on the low voltage AV I ² C communication, the PC display device of high voltage I ² C communication can be driven.

Hereinafter, preferred embodiments of the present invention will be described in detail.

4 shows a level converter 41 according to an embodiment of the present invention. FIG. 5 shows a third DVI (Digital Visual Interface) system in which the level translator 41 of FIG. 4 is used. FIG. 6 shows a fourth DVI (Digital Visual Interface) system in which the level translator 41 of FIG. 4 is used.

4 to 6, the level converter 41 according to an embodiment of the present invention is a low voltage transmission / reception terminal in a DDC communication module (DDC3.3 / 5V or DDC5 / 3.3V) employing an I ² C communication protocol. s (T _{D3 .3, .3} T _C3) and is connected between the high voltage receiving terminals (T _D5, T _C5), a low voltage receiving terminals (T _{D3 .3, .3} T _C3) high voltage signals of low voltage signals the conversion of the high voltage receiving terminals to a (T _{D5, C5} T) applied to, and receiving a low voltage terminal to the (T _{D3 .3, .3} T _C3) receiving a high voltage terminal converts a low-voltage signal into a high voltage signal of the (T _D5 , T _C5 ).

Referring to FIG. 4, the level converter 41 according to an embodiment of the present invention includes low voltage pull-up devices R _P1 and R _P2 , high voltage pull-up devices R _P3 and R _P4 , and Transistor-diode pairs TR1 and TR2.

The low voltage pull-up elements R _P1 and R _P2 as resistive elements are connected between the low voltage applying terminals V _DD1 = 3.3 V and the low voltage transmit / receive terminals T _{D3 .3} and T _{C3 .3} , respectively. The high voltage pull-up elements R _P3 and R _P4 as resistive elements are connected between the high voltage applying terminals V _DD2 = 5V and the high voltage transmitting and receiving terminals T _D5 and T _C5 , respectively. The transistor-diode pairs TR1 and TR2 are connected between the low voltage transmit and receive terminals T _{D3 .3} and T _{C3 .3} and the high voltage transmit and receive terminals T _D5 and T _C5 , respectively. The transistor-diode pairs TR1 and TR2 are turned on / off according to the potentials of the low voltage transmission and reception terminals T _{D3 .3} and T _{C3 .3} and the high voltage transmission and reception terminals T _D5 and T _C5 . )do.

Each of the transistor-diode pairs TR1 and TR2 includes a field effect transistor and a diode. The anode of the diode, which may be produced in the manufacturing process of the field effect transistor, is connected to the source s of the field effect transistor. The cathode of the diode is connected to the drain d of the field effect transistor. The sources s of the field effect transistors are connected to the low voltage transmit and receive terminals T _{D3 .3} and T _{C3 .3} , respectively. Gates g of the field effect transistors are respectively connected to the low voltage application terminals V _DD1 = 3.3V. The drains d of the field effect transistors are connected to the high voltage transmission and reception terminals T _D5 and T _C5 , respectively.

When any one of the low voltage transmit / receive terminals T _{D3 .3} and T _{C3 .3} is a low voltage logic high state, a transistor-diode pair corresponding to the low voltage transmit / receive terminal T _{D3 .3} or T _{C3 .3} . The voltage applied to the gate g and the source s of the field effect transistor of TR1 or TR2 is lower than the threshold voltage. Accordingly, the field effect transistor of the transistor-diode pair TR1 or TR2 is turned off and the high voltage pull-up element R _P3 corresponding to the low voltage transmission / reception terminal T _{D3 .3} or T _{C3 .3} . Alternatively, the high voltage transmission / reception terminal T _D5 or T _C5 is set to a high voltage logic high state through R _P4 .

Similarly, when any one of the high voltage transmit / receive terminals T _D5 and T _C5 is in a high voltage logic high state, the field effect transistor of the transistor-diode pair corresponding to the high voltage transmit / receive terminal T _D5 or T _C5 . Is turned off. Accordingly, the low voltage transmit / receive terminal T _{D3 .3} or T _{C3 .3 is} connected to the low voltage pull-up element R _P1 or R _P2 corresponding to the high voltage transmit / receive terminal T _D5 or T _C5 . Becomes

On the other hand, when any one of the low voltage transmit and receive terminals (T _{D3 .3} , T _{C3 .3} ) is a low voltage logic low state, the transistor corresponding to the low voltage transmit and receive terminals (T _{D3 .3} or T _{C3 .3} )- The voltage applied to the gate g and the source s of the field effect transistor of the diode pair TR1 or TR2 becomes higher than the threshold voltage. Accordingly, since the field effect transistor of the transistor-diode pair TR1 or TR2 is turned on, the high voltage transmit / receive terminal T _D5 corresponding to the low voltage transmit / receive terminal T _{D3 .3} or T _{C3 .3} . Or T _C5 ) becomes a high voltage logic low state.

In addition, when any one of the high voltage transceiver terminals T _{D3 .3} and T _{C3 .3} is in a high voltage logic low state, the diode of the transistor-diode pair TR1 or TR2 corresponding to the high voltage transceiver terminal is turned on. -Turned on. As a result, the potential of the source s of the field effect transistor of the transistor-diode pair TR1 or TR2 is lowered, so that the voltage applied to the gate g and the source s becomes higher than the threshold voltage. Therefore, since the field effect transistor of the transistor-diode pair TR1 or TR2 is turned on, the low voltage transmit / receive terminal T _D3.3 or T corresponding to the high voltage transmit / receive terminal T _D5 or T _C5 . _{C3 .3} ) is put into the low voltage logic low state.

According to the level converter 41 described above, the AV display of I ² C communication of low voltage, for example 3.3 V (V), by the PC host device of I ² C communication of high voltage, for example 5 V (V). The device can be driven. Conversely, by the host device on the low voltage AV I ² C communication, the PC display device of high voltage I ² C communication can be driven.

Referring to FIG. 5, the third DVI system DVI3 employing the level converter 41 according to the present invention includes a TMDS transmitter 311, a graphic controller 312, and TMDS communication lines in the AV host device 31. TMDS3.3V), DDC communication module (DDC3.3 / 5V) of 3.3 / 5V (V) standard employing I ² C communication protocol, TMDS receiver 221 and serial EEPROM (Electrically) in PC display device 22 Erasable and Programmable Read Only Memory, 222).

The configuration information and control information of the PC display device 22 are stored in the serial EEPROM 222 in the PC display device 22. The graphic control unit 312 in the AV host device 31 reads configuration information and control information stored in the serial EEPROM 222 in the PC display device 22 via I ² C communication, and TMDS in accordance with the read information. The operation of the transmitter 311 is controlled. Accordingly, the TMDS transmitter 311 transmits display data and control data to the TMDS receiver 221 through TMDS communication lines TMDS3.3V.

The 3.3 / 5 volt (DDC) communication module (DDC3.3 / 5V) employing the I ² C communication protocol provides I ² C interfaces (EI1, EI2), level converter 41, serial data transmission and reception lines ( TL _D ), and a serial clock transmit / receive line (TL _C ).

The configuration and operation of the level converter 41 are as described with reference to FIG. 4.

I ² C interfaces (EI1, EI2), each serial data output terminals (SDA1 _OUT, SDA2 _OUT) serial data to the level converter 41 and the serial data transmission line (TL _D) a through the other I ² C interface from And serial data from the level converter 41 or the serial data transmission / reception line TL _D to the serial data input terminals SDA1 _IN and SDA2 _IN .

Similarly, each of the I ² C interfaces EI1 and EI2 connected to the serial clock transmit / receive line TL _C transmits a clock signal from the serial clock output terminals SCL1 _OUT and SCL2 _OUT to the level converter 41 and the serial clock. the transmission line (TL _C), the other I ² C interface (EI1, EI2) transmission, and the level converter (41) or the serial clock transmission line (TL _C) portion emitter a clock signal the serial clock input terminal of the the via (SCL1 _IN , SCL2 _IN ).

Referring to FIG. 6, the fourth DVI system DVI3 employing the level converter 41 according to the present invention includes the TMDS transmitter 211, the graphic controller 212, and the TMDS communication lines in the PC host device 21. TMDS3.3V), DDC communication module (DDC5 / 3.3V) of 5 / 3.3 volt (V) standard employing I ² C communication protocol, TMDS receiver 321 and serial EEPROM 322 in AV display device 32 It includes.

In the serial EEPROM 322 in the AV display device 32, configuration information and control information of the AV display device 32 are stored. The graphics control unit 212 in the PC host device 21 reads configuration information and control information stored in the serial EEPROM 222 in the AV display device 32 via I ² C communication, and TMDS in accordance with the read information. The operation of the transmitter 211 is controlled. Accordingly, the TMDS transmitter 211 transmits display data and control data to the TMDS receiver 321 through TMDS communication lines TMDS3.3V.

The 5 / 3.3 volt DDC communication module (DDC5 / 3.3V) employing the I ² C communication protocol provides the I ² C interfaces (EI1, EI2), level translator 41, and serial data transmission / reception line (TL). _D ), and a serial clock transmit / receive line (TL _C ). The configuration and operation of the DDC communication module DDC5 / 3.3V are as described with reference to FIG. 5.

As described above, according to the level converter according to the present invention, a high voltage, for example, I ² C of 5 volts (V) by a PC host device of communication, low voltage, for example 3.3 volts (V) I ² C The AV display device of communication can be driven. Conversely, by the host device on the low voltage AV I ² C communication, the PC display device of high voltage I ² C communication can be driven.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (4)

It is connected between the low voltage transmission and reception terminals and the high voltage transmission and reception terminals in the DDC communication module employing the I ² C communication protocol, converts the low voltage signals of the low voltage transmission and reception terminals into high voltage signals, and applies them to the high voltage transmission and reception terminals, A level converter converting low voltage signals of terminals into high voltage signals and applying the same to the high voltage transmission / reception terminals. Low voltage pull-up elements, high voltage pull-up elements, and transistor-diode pairs, The low voltage pull-up elements are respectively connected between low voltage applying terminals and the low voltage transmitting and receiving terminals, The high voltage pull-up elements are respectively connected between high voltage applying terminals and the high voltage transmitting and receiving terminals, The transistor-diode pairs are connected between the low voltage transceiver terminals and the high voltage transceiver terminals, respectively, so that the transistor-diode pairs are turned on / off according to the potentials of the low voltage transceiver terminals and the high voltage transceiver terminals. (Off) Level shifter. The method of claim 1, Each of the transistor-diode pairs comprises a field effect transistor and a diode, An anode of the diode is connected to a source of the field effect transistor, And a cathode of said diode is connected to the drain of said field effect transistor. The method of claim 2, Sources of the field effect transistors are respectively connected to the low voltage transmission and reception terminals, Gates of the field effect transistors are connected to the low voltage applying terminals, respectively, And drains of the field effect transistors are respectively connected to the high voltage transmission and reception terminals. The method of claim 1, And said low voltage pull-up elements and said high voltage pull-up elements are resistive elements, respectively.

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