WO2021196958A1

WO2021196958A1 - Capacitive isolation circuit, interface module, chip, and system

Info

Publication number: WO2021196958A1
Application number: PCT/CN2021/078807
Authority: WO
Inventors: 白谱伟; 李浩杰; 任红强
Original assignee: 华为技术有限公司
Priority date: 2020-03-31
Filing date: 2021-03-03
Publication date: 2021-10-07
Also published as: CN112202439B; CN112202439A; CN113472338A

Abstract

The present application relates to the technical field of electronic devices, and provides a capacitive isolation circuit, an interface module, a chip, and a system. A first terminal of a first switch circuit of the capacitive isolation circuit is connected to a first pull-up circuit, the first terminal is further connected to a first main unit, and a second terminal of the first switch circuit is connected to an interface; the interface is connected to a second main unit; a control terminal of the first switch circuit is connected to a power source; a second switch circuit has a control terminal grounded, a first terminal connected to the first terminal of the first switch circuit, and a second terminal connected to the power source; the voltage difference between the first terminal and second terminal of the first switch circuit is a preset voltage value, and the preset voltage value is used for ensuring the level states of the first terminal and the second terminal to be consistent; in the first switch circuit, when the voltage difference between the control terminal and the first terminal is greater than a voltage threshold, the first terminal and the second terminal are connected; in the second switch circuit, when the voltage difference between the control terminal and the first terminal is greater than the voltage threshold, the first terminal and the second terminal are connected. The use of the circuit can reduce load capacitance of a transmission link to ensure the signal transmission quality.

Description

Capacitance isolation circuit, interface module, chip and system

This application claims the priority of a Chinese patent application filed with the State Intellectual Property Office of China, the application number is 202010244788.6, and the invention title is "a capacitive isolation circuit, interface module, chip and system" on March 31, 2020, and its entire content Incorporated in this application by reference.

Technical field

This application relates to the technical field of electronic equipment, and in particular to a capacitive isolation circuit, an interface module, a chip and a system.

Background technique

For electronic equipment that uses high-speed signals, the load capacitance of the high-speed signal transmission link will cut the rising edge of the high-speed signal. When the load capacitance is too large, it will cause insufficient signal level and excessive rising edge time, which will lead to electronic equipment. The signal cannot be received normally.

Therefore, in order to ensure the compatibility of electronic devices, high-speed signal protocol specifications usually have clear constraints on the load capacitance of the transmission link. However, when encountering a long signal transmission link system, physical constraints will make it difficult for the load capacitance to meet the constraint requirements. Taking the HDMI (High Definition Multimedia Interface) interface of TV equipment as an example, the link load capacitance specification of the CEC (Consumer Electronics Control) signal transmitted through the HDMI interface is required to be within 200pF to ensure Device compatibility. As for the hardware architecture of TV equipment with a long HDMI path, the link load capacitance of the CEC signal cannot meet the requirements of the link load capacitance specification, which in turn causes the TV equipment to fail to receive signals normally.

Therefore, how to reduce the load capacitance of the signal transmission link is an urgent problem to be solved at present.

Summary of the invention

In order to solve the above technical problems, the present application provides a capacitive isolation circuit, interface module, chip and system, which can reduce the load capacitance of the transmission link to ensure signal transmission quality.

In the first aspect, the embodiments of the present application provide a capacitive isolation circuit, which can reduce the load capacitance of the link to ensure the signal transmission quality during use, and is suitable for long signal transmission distances, load capacitance requirements cannot be met, or signal driving A scene where power cannot be satisfied. The capacitive isolation circuit includes: a first switch circuit, a second switch circuit, and a first pull-up circuit; the first end of the first switch circuit is connected to the first pull-up circuit, and the first end of the first switch circuit is also used for Connect to the first host; the second end of the first switch circuit is used to connect to the interface; the interface is used to connect to the second host; the control end of the first switch circuit is connected to the power supply; the control end of the second switch circuit is grounded, and the second switch circuit The first terminal of the first switch circuit is connected to the first terminal, and the second terminal of the second switch circuit is connected to the power supply; the voltage difference between the first terminal and the second terminal of the first switch circuit is a preset voltage value, which is preset The voltage value is used to ensure that the level states of the first terminal and the second terminal of the first switch circuit are consistent; when the voltage difference between the control terminal and the first terminal of the first switch circuit is greater than the voltage threshold, the first terminal of the first switch circuit When the voltage difference between the control terminal and the first terminal of the second switch circuit is greater than the voltage threshold, the first terminal and the second terminal of the second switch circuit are conducted.

The value principle of the preset voltage value is to enable the voltages of the first terminal and the second terminal of the first switch circuit to be determined to be the same level, that is, the same high level or the same low level, so the preset voltage value The judgment interval of the value relative to the level is small. The capacitive isolation circuit, by using two switch circuits, can shorten the load link length and reduce the load capacitance, thereby ensuring the quality of signal transmission.

With reference to the first aspect, in a first possible implementation manner, the first pull-up circuit includes: a first pull-up resistor. The first end of the first switch circuit is connected to the power source through the first pull-up resistor. The first pull-up circuit can play a role in signal enhancement.

Combining the first aspect and any one of the foregoing implementation manners, in a second possible implementation manner, the first switch circuit is a first NMOS transistor, the first terminal of the first switch circuit is the source of the first NMOS transistor, and the first switch circuit is the source of the first NMOS transistor. The second terminal of a switch circuit is the drain of the first NMOS transistor, and the control terminal of the first switch circuit is the gate of the first NMOS transistor.

By using the first NMOS tube to realize the function of the first switch circuit, the circuit structure is simple, the hardware cost is low, and there is no need to add a complex signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need to increase software development investment.

Combining the first aspect and any one of the above implementations, in a third possible implementation, the second switch circuit is a second NMOS transistor, the first end of the second switch circuit is the source of the second NMOS transistor, and the first terminal of the second switch circuit is the source of the second NMOS transistor. The second end of the two switch circuits is the drain of the second NMOS transistor, and the control end of the second switch circuit is the gate of the second NMOS transistor.

By using the second NMOS tube to realize the function of the second switch circuit, the circuit structure is simple, the hardware cost is low, and there is no need to add a complex signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need to increase software development investment.

With reference to the first aspect and any one of the foregoing implementation manners, in a fourth possible implementation manner, the first switch circuit includes a first switch and a first diode; the anode of the first diode is connected to the first switch of the first switch. At one end, the cathode of the first diode is connected to the second end of the first switch.

By using the first switch and the first diode to realize the function of the first switch circuit, the circuit structure is simple, the hardware cost is low, and there is no need to add a complex signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need to add software Development investment.

With reference to the first aspect and any one of the foregoing implementation manners, in a fifth possible implementation manner, the second switch circuit includes a second switch and a second diode; the anode of the second diode is connected to the second switch of the second switch. At one end, the cathode of the second diode is connected to the second end of the second switch.

By using the second switch and the second diode to realize the function of the first switch circuit, the circuit structure is simple, the hardware cost is low, and there is no need to add a complicated signal processing chip, so the signal response speed is fast, the power consumption is low, and no software is required. Development investment.

With reference to the first aspect and any one of the foregoing implementation manners, in a sixth possible implementation manner, the capacitive isolation circuit further includes a protection circuit. The control terminal of the second switch circuit is grounded through the protection circuit. The protection circuit is used to filter out interference signals.

With reference to the first aspect and any one of the foregoing implementation manners, in a seventh possible implementation manner, the protection circuit includes a grounding resistance. The control terminal of the second switch circuit is grounded through a grounding resistance.

Using grounding resistance as a protection circuit, the circuit structure is simple, and can filter out interference signals

With reference to the first aspect and any one of the foregoing implementation manners, in an eighth possible implementation manner, the capacitive isolation circuit further includes: a current-limiting resistor. The control terminal of the first switch circuit is connected to the power supply through a current limiting resistor. The current-limiting resistor is used to prevent excessive current and protect the circuit.

With reference to the first aspect and any one of the foregoing implementation manners, in a ninth possible implementation manner, the capacitive isolation circuit further includes: a second pull-up circuit. The second end of the first switch circuit is connected to the second pull-up circuit.

The second pull-up circuit can enhance the transmission signal on the second end side of the first switch circuit to improve the signal transmission quality.

With reference to the first aspect and any one of the foregoing implementation manners, in a tenth possible implementation manner, the second pull-up circuit includes: a second pull-up resistor. The second end of the first switch circuit is connected to the power supply through the second pull-up resistor, so as to enhance the signal.

In the second aspect, the present application also provides a docking station, including the capacitive isolation circuit provided by any one of the above possible implementations, and further including: an interface. The interface is used to connect to the second host, and is used to send the signal sent by the second host to the first host through the capacitive isolation circuit.

The application of the expansion dock can shorten the load link length, reduce the load capacitance and ensure the quality of signal transmission, and the capacitive isolation circuit in the expansion dock has a simple structure, low hardware cost, does not need to add a complex signal processing chip, and the signal response speed is fast , Low power consumption, no need to increase software development investment.

With reference to the second aspect, in the first possible implementation manner, the interface is a high-definition multimedia interface HDMI interface.

In an application scenario of the docking station, the docking station can be a Dock box, which is used to realize signal transmission between the TV host and the TV box. At this time, the docking station’s interface can include an HDMI interface. The docking station is connected to the TV box through an HDMI cable. The HDMI cable can transmit CEC signals. At this time, the capacitive isolation circuit of the docking station 400 is used to reduce the chain of CEC signal transmission. Load capacitance and ensure the transmission quality of the signal between the TV host and the TV box.

In the third aspect, the present application also provides a capacitive isolation chip, which specifically includes: a first input/output IO port, a second IO port, and a third IO port. The first IO port is used to connect to the first host; the second IO port is used to connect to the second host through the interface; the voltage difference between the first IO port and the second IO port is a preset voltage value, and the preset voltage value is used for Make the level state between the first IO port and the second IO port consistent. When the voltage difference between the first IO port and the third IO port is greater than the voltage threshold, the first IO port and the second IO port are turned on, so that a signal is transmitted between the first host and the second host.

The capacitive isolation circuit of the capacitive isolation chip can be any of the above possible implementations, so the signal link length can be shortened, thereby reducing the load capacitance, and the pull-up circuit of the capacitive isolation circuit can also play a role in signal enhancement , So it can guarantee the quality of signal transmission. In addition, the capacitive isolation chip has a simple structure and low hardware cost. Compared with a complex signal processing chip, the signal response speed is fast and the power consumption is low, and there is no need to increase software development investment.

In a fourth aspect, the present application also provides a playback system. The playback system includes the docking station provided by any one of the above implementations, and further includes: a first host. The first host is connected to the docking station through a transmission cable; the docking station is used to send the signal sent by the second host to the first host. The first host is used to play content.

With reference to the fourth aspect, in the first possible implementation manner, the first host is a television host, and the second host is a video source host. At this time, the docking station (that is, the Dock box) is used to send the content sent by the video source host to the TV host, so that the TV host can play.

The expansion dock of the playback system includes a capacitive isolation circuit. After using the capacitive isolation circuit, the load link length is the link length from the second host to the second end of the first switch circuit of the capacitive isolation circuit, excluding the first host The length of the link to the first end of the first switch circuit can shorten the length of the load link, reduce the load capacitance, and at the same time ensure the signal transmission quality, thereby ensuring that the TV host of the playback system can normally play the video source The content sent by the host.

The solution provided by this application has at least the following advantages:

The capacitive isolation circuit includes a first switch circuit, a second switch circuit, and a first pull-up circuit. Wherein, the first end of the first switch circuit is connected to the first pull-up circuit, and the first end of the first switch circuit is also connected to the first host. The second end of the first switch circuit is connected to the interface, the interface is connected to the second host, and the control end of the first switch circuit is connected to the power supply. The control terminal of the second switch circuit is grounded, the first terminal of the second switch circuit is connected to the first terminal of the first switch circuit, and the second terminal of the second switch circuit is connected to the power supply. The voltage difference between the first terminal and the second terminal of the first switch circuit is a preset voltage value, and the principle of the preset voltage value is to enable the voltage of the first terminal and the second terminal of the first switch circuit to be determined The same level, that is, the same high level or the same low level.

When the second host inputs a high level to the second terminal of the first switch circuit, the first terminal of the first switch circuit is also at high level at this time, and the first pull-up circuit enhances the signal at the first terminal of the first switch circuit. Therefore, the high-level signal can be transmitted to the first host normally.

When the second host inputs a low level to the second terminal of the first switch circuit, the voltage at the first terminal of the first switch circuit is equal to the preset voltage value, and the control terminal of the first switch circuit is connected to the power supply to be high level, The voltage difference between the control terminal and the first terminal of the first switch circuit is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit are turned on, so that the potential of the first terminal of the first switch circuit drops to low level, The low level is transmitted to the first host.

When the first host sends a high level to the first terminal of the first switch circuit, the control terminal of the first switch circuit is connected to the power supply to be high level, because the voltage difference between the control terminal of the first switch circuit and the first terminal is less than the voltage threshold At this time, the first terminal and the second terminal of the first switch circuit are disconnected, and the second terminal of the first switch circuit is also at a high level. At this time, the high level is transmitted to the second host.

When the first host sends a low level to the first terminal of the first switch circuit, the control terminal of the first switch circuit is connected to the power supply to be high level, because the voltage difference between the control terminal of the first switch circuit and the first terminal is greater than the voltage threshold At this time, the first terminal and the second terminal of the first switch circuit are turned on, so that the second terminal of the first switch circuit is at a low level, and the low level is transmitted to the second host at this time.

For the system using the capacitive isolation circuit, when testing the load capacitance of the transmission link, the positive pole of the tester is connected to the control end of the second switch circuit, which is high level, and the negative pole of the tester is connected to the first switch circuit through the interface. The second end is low level. When the first host is the device under test and is not powered on, the power supply is not powered on at this time, and the first terminal, the second terminal and the control terminal of the first switch circuit are all low level. The control terminal of the second switch circuit is connected to the positive terminal of the tester, so it is at a high level. The voltage difference between the control terminal of the second switch circuit and the first terminal is greater than the voltage threshold. At this time, the first terminal and the second terminal of the second switch circuit The terminal is turned on, so that the control terminal of the first switch circuit and the first terminal have the same potential, and the first terminal and the second terminal of the first switch circuit are disconnected. The load link length at this time is the link length between the tester and the second end of the first switch circuit, and does not include the link length between the first host and the first end of the first switch circuit. That is, in actual application, the length of the load link is the length of the link between the second host and the second end of the first switching circuit, and the shortened link length is the length between the first host and the first end of the first switching circuit. Therefore, the length of the load link is shortened, and the load capacitance can be reduced.

In summary, by using the capacitive isolation circuit provided by the embodiments of the present application, by using two switching circuits, the load link length can be shortened, the load capacitance can be reduced, and the signal transmission quality can be ensured.

Description of the drawings

Figure 1 is a schematic diagram of an application scenario;

Figure 2 is a schematic diagram when a CEC signal conversion chip is used;

Figure 3 is a schematic diagram when a CEC control chip is used;

4A is a schematic diagram of a capacitive isolation circuit provided by an embodiment of this application;

FIG. 4B is a schematic diagram of an application scenario provided by an embodiment of this application;

FIG. 5 is a schematic diagram of a working principle corresponding to FIG. 3 provided by an embodiment of the application;

FIG. 6 is a schematic diagram of another working principle corresponding to FIG. 3 according to an embodiment of the application;

FIG. 7 is a schematic diagram of another working principle corresponding to FIG. 3 according to an embodiment of the application;

FIG. 8 is a schematic diagram of still another working principle corresponding to FIG. 3 according to an embodiment of the application;

FIG. 9 is a schematic diagram of the working principle of the load capacitance test performed by the circuit shown in FIG. 3;

FIG. 10 is a schematic diagram of another capacitive isolation circuit provided by an embodiment of the application;

FIG. 11 is a schematic diagram of a working principle corresponding to FIG. 10 according to an embodiment of the application;

FIG. 12 is a schematic diagram of another working principle corresponding to FIG. 10 according to an embodiment of the application;

FIG. 13 is a schematic diagram of another working principle corresponding to FIG. 10 according to an embodiment of the application;

FIG. 14 is a schematic diagram of still another working principle corresponding to FIG. 10 according to an embodiment of the application;

FIG. 15 is a schematic diagram of the working principle of the circuit shown in FIG. 10 when the load capacitance is tested;

FIG. 16 is a schematic diagram of yet another capacitive isolation circuit provided by an embodiment of this application;

FIG. 17 is a schematic diagram of still another capacitive isolation circuit provided by an embodiment of this application;

FIG. 18 is a schematic diagram of another capacitive isolation circuit provided by an embodiment of the application;

FIG. 19 is a schematic diagram of an expansion dock provided by an embodiment of the application;

FIG. 20 is a schematic diagram of a capacitive isolation chip provided by an embodiment of the application;

FIG. 21 is a schematic diagram of another capacitive isolation chip provided by an embodiment of the application;

22 is a schematic diagram of a packaged capacitive isolation chip provided by an embodiment of the application;

FIG. 23 is a schematic diagram of a playback system provided by an embodiment of the application.

Detailed ways

In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present application, the following first describes the impact of the load capacitance of the transmission link on the high-speed signal transmission process in conjunction with specific application scenarios.

In the following, an application scenario is a television device as an example, see FIG. 1, which is a schematic diagram of an application scenario provided by an embodiment of the application.

Take the playback system including the TV host 101, the Dock box 102, and the TV box 103 as an example.

Among them, the TV host 101 is connected to the Dock box 102 through a cable. The Dock box 102 is mainly convenient for users to operate, and transfers the interface on the TV host 101 to the Dock box 102. The Dock box 102 is connected to the TV box 103 through an HDMI cable, and transmits the information sent by the TV box 103 to the TV host 101.

However, the TV box transmits signals to the TV device through the HDMI interface for the TV device to play, and the link load capacitance of the CEC signal transmitted through the HDMI interface is required to be within 200pF to ensure device compatibility. As for TV equipment with a long HDMI path, the link load capacitance of the CEC signal cannot meet the requirements of the link load capacitance specification, which in turn causes the TV equipment to fail to receive signals normally.

The following specifically describes the principle that the playback system including the TV host, the Dock box and the TV box makes the link load capacitance meet the specification requirements.

The following first describes the first possible implementation.

Refer to Figure 2, which is a schematic diagram when a CEC signal conversion chip is used.

The motherboard SOC (System-on-a-chip) of the TV host 101 is connected to the Dock box 102 through a connection cable. The TV host 101 and the Dock box 102 form a receiving device, and the Dock box 102 is connected through an HDMI interface An HDMI cable, and the other end of the HDMI cable is connected to the TV box 103 as a transmitting device.

This implementation uses a CEC conversion IC (Integrated Circuit, chip) at the Dock box 102 to convert the CEC signal into an I2C (Inter-Integrated Circuit, integrated circuit) signal, and the Dock box 102 sends the converted signal to the TV host The 101 mainboard SOC realizes the function of CEC signal. Since the CEC signal is no longer transmitted between the TV host 101 and the Dock box 102, the transmission link length of the CEC signal is shortened, thereby achieving the purpose of reducing the load capacitance.

However, this implementation requires the motherboard SOC of the television host 101 to poll the CEC signal conversion chip in the Dock box 102 to monitor whether there is a new command input. This will cause the CEC conversion chip and the I2C of the motherboard SOC to not be powered off in the standby state, which increases the standby power consumption. Moreover, due to the addition of CEC conversion chips and peripheral devices, corresponding software needs to be developed, and the hardware cost and software development investment in R&D are large. In addition, due to the signal conversion process, the function response will be slow.

The second possible implementation is described below.

Refer to Figure 3, which is a schematic diagram when a CEC control chip is used.

The TV host 101 is connected to the Dock box 102 through a connection cable. This implementation uses a CEC control IC at the Dock box 102, and the CEC control IC directly processes CEC signals and communicates with the TV box 103, thus shortening the CEC link length.

However, the investment in hardware design and software design of this implementation method is large and the cost is high. And in the standby state, the CEC control IC needs to be in working state, which increases additional power consumption.

The above description only takes television equipment as an example. It can be understood that for other electronic equipment that uses high-speed signals, there are also too long high-speed signal transmission links, which causes the load capacitance of the high-speed signal transmission link to fail to meet the requirements. I will not explain each application scenario one by one here.

In order to solve the above technical problems, an embodiment of the present application provides a capacitive isolation circuit. The isolation circuit includes a first switch circuit, a second switch circuit, and a first pull-up circuit. Wherein, the first end of the first switch circuit is connected to the first pull-up circuit, and the first end of the first switch circuit is also connected to the first host. The second end of the first switch circuit is connected to an interface, the interface can be connected to a second host, and the control end of the first switch circuit is connected to a power source. The control terminal of the second switch circuit is grounded, the first terminal of the second switch circuit is connected to the first terminal of the first switch circuit, and the second terminal of the second switch circuit is connected to the power supply. The voltage between the first terminal and the second terminal of the first switch circuit is a preset voltage value, and the principle of the preset voltage value is to enable the voltage at the first terminal and the second terminal of the first switch circuit to be determined as The same level, that is, the same high level or the same low level.

When the second host inputs a high level to the second terminal of the first switch circuit, the first terminal of the first switch circuit is also at high level at this time. At this time, the first pull-up circuit signals the first terminal of the first switch circuit. It has an enhancement effect, so the high-level signal can be transmitted to the first host normally.

When the second host inputs a low level to the second terminal of the first switch circuit, the voltage at the first terminal of the first switch circuit is equal to the preset voltage value, and the control terminal of the first switch circuit is connected to the power supply to be high level, So that the voltage difference between the control terminal and the first terminal of the first switch circuit is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit are turned on, so that the potential of the first terminal of the first switch circuit drops to a low level, The low level is transmitted to the first host.

For the system using the capacitive isolation circuit, when testing the load capacitance of the transmission link, the positive pole of the tester is connected to the control end of the second switch circuit, which is high level, and the negative pole of the tester is connected to the first switch circuit through the interface. The second end is low level. When the first host is the device under test and is not powered on, the power supply is not powered on. At this time, the first terminal, the second terminal and the control terminal of the first switch circuit are all low level. Since the control terminal of the second switch circuit is at a high level, the voltage difference between the control terminal of the second switch circuit and the first terminal is greater than the voltage threshold. At this time, the first terminal and the second terminal of the second switch circuit are turned on, so that the first The control terminal and the first terminal of the switch circuit have the same potential, and the first terminal and the second terminal of the first switch circuit are disconnected. At this time, the load link length is the link length from the tester to the first switch circuit, and does not include the link length from the first host to the first end of the first switch circuit. Therefore, the load link length is shortened, thereby enabling Reduce the load capacitance.

In summary, the use of the capacitive isolation circuit provided by the embodiments of the present application can shorten the length of the load link, reduce the load capacitance, and at the same time ensure the quality of signal transmission, the circuit structure is simple, the hardware cost is low, and there is no need to add complex Signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need to increase the software development investment.

The technical solutions in the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.

Circuit embodiment one:

The embodiment of the application provides a capacitive isolation circuit, which can reduce the load capacitance of the link to ensure the signal transmission quality when in use, and is suitable for long signal transmission distances, and the load capacitance requirements cannot be met or the signal driving force cannot be met. Scenes. The following is a detailed description with reference to the drawings.

Refer to FIG. 4A, which is a schematic diagram of a capacitive isolation circuit provided by an embodiment of the application.

The capacitive isolation circuit includes: a first switch circuit 201, a second switch circuit 202, and a first pull-up circuit 203.

The first terminal of the first switch circuit 201 is connected to the first pull-up circuit 203, and the first terminal of the first switch circuit 201 is also connected to the first host 205.

The second end of the first switch circuit 201 is connected to the interface 204, and the interface 204 is used to connect to the second host 206.

In the embodiment of the present application, the type of the interface 204 is not specifically limited, and the type of data transmitted between the first host 205 and the second host 206 and the type of cable used are not specifically limited.

The following is an example.

Refer to FIG. 4B, which is a schematic diagram of an application scenario provided by an embodiment of the application.

Taking the application of the capacitive isolation circuit to a TV playback system as an example, the playback system includes a TV host 101, a Dock box 102, and a TV box 103.

The first host 205 may correspond to the TV host 101, and the second host 206 may correspond to the TV box 103. The capacitive isolation circuit 102a and the HDMI interface provided in the embodiment of the present application may be located in the Dock box 102. At this time, the interface 204 is an HDMI interface, which is connected to the TV box 103 through an HDMI cable, and the CEC signal is transmitted in the HDMI cable.

At this time, the capacitive isolation circuit is used to reduce the link load capacitance during CEC signal transmission and to ensure the signal transmission quality between the TV host 101 and the TV box 103.

It is understandable that the above is only one application scenario of the capacitive isolation circuit, and the capacitive isolation circuit can also be used in other systems with longer signal transmission links, and the embodiments of this application will not repeat them one by one.

Continuing to refer to FIG. 3, the control terminal of the first switch circuit 201 is connected to the power supply 207.

The control terminal of the second switch circuit 202 of the capacitive isolation circuit is grounded, the first terminal of the second switch circuit 202 is connected to the first terminal of the first switch circuit 201, and the second terminal of the second switch circuit 202 is connected to the power supply 207.

It can be understood that the power supply 207 connected to the capacitive isolation circuit can be realized by the power supply on the first host 205, that is, powered by the power supply of the first host.

The voltage difference between the first terminal and the second terminal of the first switch circuit 201 is a preset voltage value, so that the level states of the first terminal and the second terminal of the first switch circuit 201 are consistent, that is, the preset voltage value The value principle of is that the voltages of the first terminal and the second terminal of the first switch circuit 201 can be determined to be the same level, that is, the same high level or the same low level. The embodiment of the present application does not specifically limit the preset voltage value.

In practical applications, the voltage difference between the first terminal and the second terminal of the first switch circuit 201 can be clamped to a preset voltage value through a voltage clamping method. The preset voltage value can be set to a smaller voltage value relative to the range of high and low levels. For example, a signal with a voltage less than 2.5V is uniformly identified as a low level, and a signal with a voltage greater than 2.5V is uniformly identified as a high level. flat. Assuming that the voltage of the first terminal of the first switch circuit 201 is 3.3V, since 3.3V is greater than 2.5V, it will be recognized as a high level. Because the voltage drop between the first terminal of the first switch circuit 201 and the second terminal of the first switch circuit 201 is clamped to the preset voltage value, for example, the value range of the preset voltage value can be set to (0 , 0.8V), assuming that the preset voltage value is set to 0.1V, under the switch-on condition, since the voltage of the first terminal of the first switch circuit 201 is 3.3V, the first switch circuit 201 The voltage at the second terminal of the first switch circuit 201 is clamped to 3.2V. Since 3.2V is higher than 2.5V, the second terminal of the first switch circuit 201 will also be recognized as a high level, that is, the first terminal and the second terminal of the first switch circuit 201 The voltages at both ends are judged to be the same level.

When the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit 201 are turned on.

When the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, the first terminal and the second terminal of the second switch circuit 202 are turned on.

Among them, the voltage threshold is related to the specific implementation of the switch circuit, which is not specifically limited in the embodiment of the present application.

For the convenience of explanation, the working principle of the capacitive isolation circuit will be described in detail below by taking "1" for high level and "0" for low level as an example.

Refer to FIG. 5, which is a schematic diagram of a working principle corresponding to FIG. 4 provided by an embodiment of the application.

Wherein, the first terminal, the second terminal and the control terminal of the first switch circuit 201 correspond to the B terminal, the C terminal and the A terminal, respectively. The first terminal, the second terminal and the control terminal of the second switch circuit 202 correspond to the B'terminal, the C'terminal and the A'terminal, respectively.

When the second host 206 sends a "1" to the first host 205, the second host 206 inputs a "1" to the second terminal of the first switch circuit 201, and the C terminal is high, because the B terminal and the pull-up circuit 203 Connected, so the B terminal is also high. The control terminal of the first switch circuit 201 is connected to the power supply and is also at a high level. At this time, the voltage difference between the A terminal and the B terminal is less than the preset threshold, so the first terminal and the second terminal of the first switch circuit 201 are disconnected.

At this time, the first pull-up circuit 203 has an enhancement effect on the signal at the first end of the first switch circuit 201, and the first host 205 can normally receive the signal "1".

The connection cable between the interface 204 and the second host 206 may be an HDMI cable, or may be a cable used in other scenarios where the load capacitance of the link needs to be reduced, and the embodiment of the present application does not specifically limit it here. .

Refer to FIG. 6, which is a schematic diagram of another working principle corresponding to FIG. 4 provided by an embodiment of the application.

When the second host 206 sends "0" to the first host 205, the second host 206 inputs "0" to the second terminal of the first switch circuit 201. At this time, the potential of the first terminal of the first switch circuit 201 is equal to the preset value. Set the voltage value, and the control terminal of the first switch circuit 201 is connected to the power supply at a high level. Since the preset voltage value is low, the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, The first terminal and the second terminal of the first switch circuit 201 are turned on. At this time, the voltage of the first switch circuit 201 is reduced from the preset voltage value to “0”, and then “0” is transmitted to the first host 205.

Refer to FIG. 7, which is a schematic diagram of another working principle corresponding to FIG. 4 provided in an embodiment of the application.

When the first host 205 sends a "1" to the second host 206, the first host 205 sends a "1" to the first terminal of the first switch circuit 201, and the control terminal of the first switch circuit 201 is connected to the power supply to be high. Since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is less than the voltage threshold, the first terminal and the second terminal of the first switch circuit 201 are disconnected at this time.

In addition, since the voltage difference between the two ends of B and C is a preset voltage value, the second end of the first switch circuit 201 is also at a high level at this time, and the second host 206 can normally receive "1" at this time.

Refer to FIG. 8, which is a schematic diagram of still another working principle provided by an embodiment of the application.

When the first host 205 sends a "0" to the second host 206, the first host 205 sends a "0" to the first terminal of the first switch circuit 201, the first terminal of the first switch circuit 201 is low, and the The control terminal of a switch circuit 201 is connected to the power supply at a high level. Since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit 201 are connected at this time . Since the first terminal of the first switch circuit 201 is at a low level, the second terminal of the first switch circuit 201 is at a low level, and the second host 206 can normally receive "0" at this time.

Refer to Figure 9, which is a schematic diagram of the working principle of the circuit shown in Figure 4 during load capacitance testing.

The RLC tester 208 can be used to test the load capacitance of the signal link to confirm whether the capacitive load circuit meets the certification requirements. The following takes the case when the power supply 207 is not powered on as an example.

The first host 205 is the device under test, which is connected to the test fixture through the interface 204, the positive pole of the RLC tester 208 (+ pole in the figure) is connected to the ground of the first host 205 through the interface 204, and the negative pole of the RLC tester 208 (in the figure) -Pole) Connect the signal link under test. The RLC tester 208 uses the positive pole to send out a voltage sine wave with a DC bias, and measures the voltage and current sine waves received by the negative pole to determine the load capacitance.

At this time, the second end of the first switch circuit 201 is connected to the negative electrode of the RLC tester 208 through the interface 204, and the potential is "0". Since the voltage difference between the two ends of B and C is the preset voltage value, the first switch circuit 201 The first terminal potential is also "0". Since the power supply 207 is not powered on, the control terminal of the first switch circuit 201 is in a floating state.

The control terminal of the second switch circuit 202 shares the ground with the positive pole of the RLC tester 208, that is, the control terminal of the second switch circuit 202 is connected to the positive pole of the RLC tester 208. Under the action of the sine wave output by the RLC tester 208, The potential of the control terminal of the second switch circuit 202 is "1". At this time, the potential of the first terminal (B') of the second switch circuit 202 and the potential of the first terminal (B) of the first switch circuit 201 are both “0”, so the control terminal of the second switch circuit 202 is The voltage difference between one end is greater than the preset threshold, and the first end and the second end of the second switch circuit 202 are turned on. Furthermore, the potentials of the control terminal and the first terminal of the first switch circuit 201 are the same, so that the first terminal and the second terminal of the first switch circuit 201 are disconnected.

The signal link length tested at this time is the link length from the RLC tester 208 to the first switch circuit 201, and does not include the link length from the first host to the first end of the first switch circuit, thus shortening the signal link Length, in turn, can reduce the load capacitance.

It is understandable that when the power supply 207 is powered on, the principle of testing the load capacitance is similar, and the details are not repeated in the embodiment of the present application.

In summary, using the capacitive isolation circuit provided by the embodiments of the present application, by using the two switching circuits described above, the signal link length can be shortened, thereby reducing the load capacitance, and the pull-up circuit can also enhance the signal. Therefore, the transmission quality of the signal can be guaranteed. In addition, compared with the corresponding implementations in Figs. 2 and 3, the circuit structure provided by the embodiment of the present application is simple, the hardware cost is low, and there is no need to add a complex signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need Increase investment in software development.

The working principle of the capacitive isolation circuit will be described below in conjunction with a specific circuit implementation.

Circuit embodiment two:

Refer to FIG. 10, which is a schematic diagram of another capacitive isolation circuit provided by an embodiment of the application.

4 together, FIG. 10 shows specific implementations of the first switch circuit 201, the second switch circuit 202, and the first pull-up circuit 203.

The first switch circuit 201 of the embodiment of the present application includes a first NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) tube Q1. The first end of the first switch circuit 201 is the source of the first NMOS transistor Q1 (indicated by the letter S in the figure), and the second end of the first switch circuit 201 is the drain of the first NMOS transistor Q1 (in the figure with the letter D), the control terminal of the first switch circuit 201 is the gate of the first NMOS transistor Q1 (indicated by the letter G in the figure).

D1 can be the body diode of the first NMOS transistor Q1 or an external diode; D2 can be the body diode of the second NMOS transistor Q2 or an external diode. In the following description, D1 is the body diode of the first NMOS transistor Q1 and D2 is the body diode of the second NMOS transistor Q2 as an example.

The second switch circuit 202 of the embodiment of the present application includes a second NMOS transistor Q2. The first end of the second switch circuit 202 is the source of the second NMOS transistor Q2 (indicated by the letter S'in the figure), and the second end of the second switch circuit 202 is the drain of the second NMOS transistor Q2 (in the figure (Represented by the letter D'), the control terminal of the second switch circuit 202 is the gate of the second NMOS transistor Q2 (represented by the letter G'in the figure).

The first pull-up circuit 203 includes a first pull-up resistor R1. The first end of the first switch circuit 201 is connected to the power supply 207 through the first pull-up resistor R1. The first pull-up circuit can play a role in signal enhancement.

Further, the capacitance isolation circuit further includes a protection circuit, and the control terminal of the second switch circuit 202 is grounded through the protection circuit. The protection circuit is used to filter out interference signals.

In the implementation shown in FIG. 10, the protection circuit includes a grounding resistor R2, that is, the control terminal of the second switch circuit 202 is grounded through the grounding resistor R2.

Further, the capacitive isolation circuit further includes a current-limiting circuit R3, and the current-limiting resistor R3 is used for the protection circuit. The control terminal of the first switch circuit 201 is connected to the power supply 207 through a current limiting resistor R3.

In practical applications, the power source connected to the first terminal of the first switch circuit 201 through the first pull-up circuit 203 and the power source connected to the control terminal of the first switch circuit 201 through the current limiting resistor R3 may be the same power source.

It is understandable that the specific specifications of the first NMOS transistor Q1 and the second NMOS transistor Q2 in practical applications can be the same, and their selection should meet the following conditions:

1. The turn-on threshold voltage Vth of the two NMOS transistors should be less than the voltage of the power supply 207, so that the first NMOS transistor Q1 can be turned on when transmitting "0".

2. When the load capacitance test is performed, the minimum voltage that the positive pole of the RLC tester 208 used to add to the gate of the second NMOS tube Q2 is Vmin, then the turn-on threshold voltage Vth of the NMOS tube also needs to satisfy Vth<Vmin, so that The second NMOS transistor Q2 can be turned on under the load capacitance test state.

3. The turn-on threshold voltage Vth of the NMOS transistor also needs to satisfy Vth>V _S'D' so that the first NMOS transistor Q1 can be turned off during the load capacitance test.

4. Due to the function of the body diode of the NMOS tube (also known as the parasitic diode, the anode is connected to the source of the NMOS tube, and the cathode is connected to the drain of the NMOS tube), the voltage between the source and drain should satisfy V _SD = U (where U is the voltage drop of the body diode), the V _SD is the preset voltage value, which is a smaller voltage value.

In practical applications, the capacitive isolation circuit and the interface 204 can be packaged together as a whole device. For example, referring to FIG. 4 and FIG. 10 together, when the present application is applied to a TV playback system, the 300 including the capacitive isolation circuit and the interface 204 may be the Dock box 102 in FIG. 4. At this time, the first host 205 corresponds to the TV host 101, the second host 206 corresponds to the TV box 103 (also known as the video source host), the interface 204 can be an HDMI interface, and the interface 204 and the second host 206 are connected through an HDMI cable Cable connection. If the Dock box 102 has multiple HDMI interfaces, the CEC signal of each HDMI interface can be connected as a signal before entering the capacitive isolation circuit

At this time, the voltage of the power supply 207 can be 3.3V. When the load capacitance test of the TV playback system is carried out, the minimum voltage Vmin of the positive pole of the RLC tester used to the gate of the second NMOS transistor Q2 is 0.84V, then it is turned on The threshold voltage Vth is less than 0.84V.

The working principle of the capacitive isolation circuit of the embodiment of the present application will be described in detail below.

Refer to FIG. 11, which provides a schematic diagram of a working principle corresponding to FIG. 10 according to an embodiment of the present application.

When the second host 206 sends "1" to the first host 205, the drain potential of the first NMOS transistor Q1 is "1". At this time, the source of the first NMOS transistor Q1 is pulled up to the power supply 207 through the first pull-up resistor. , Therefore the potential is "1", the gate of Q1 is pulled up to the power supply 207 through the current limiting resistor R3, so the gate potential of Q1 is "1".

At this time, for Q1, the voltage between the gate and the source V _GS <Vth, so Q1 is turned off.

Refer to FIG. 12, which is a schematic diagram of another working principle corresponding to FIG. 10 according to an embodiment of the application.

When the second host 206 sends "0" to the first host 205, the second host 206 inputs "0" to the second end of the first NMOS transistor Q1. At this time, due to the body diode of the first NMOS transistor Q1, Q1 _{The voltage difference V SD} between the source and drain of Q1 is low (less than 0.1V), and the source potential of Q1 decreases and approaches the drain.

The gate of the first NMOS transistor Q1 is pulled up to a high level through the current limiting resistor R3. At this time, the voltage between the gate and the source of the first NMOS transistor Q1 is V _GS ≥ Vth, and the first NMOS transistor Q1 is turned on. At this time, the potential of the first NMOS transistor is “0”, and then “0” is transmitted to the first host 205.

Refer to FIG. 13, which is a schematic diagram of another working principle corresponding to FIG. 10 provided by an embodiment of the application.

When the first host 205 sends "1" to the second host 206, the source potential of the first NMOS transistor Q1 is "1", and the gate of the first NMOS transistor Q1 is pulled up to the power supply 207 through the current-limiting resistor R3. Is "1". At this time, the voltage between the gate and source of the first NMOS transistor Q1 is V _GS <Vth, and the first NMOS transistor Q1 is turned off. Due to the body diode, the drain voltage of the first NMOS transistor Q1 is close to the source voltage. Therefore, the drain level is "1", and the second host 206 can normally receive "1" at this time.

Refer to FIG. 14, which is a schematic diagram of still another working principle corresponding to FIG. 10 provided by an embodiment of the application.

When the first host 205 sends "0" to the second host 206, the source potential of the first NMOS transistor Q1 is "0", and the gate of the first NMOS transistor Q1 is pulled up to the power supply 207 through the current limiting resistor R3. Is "1". At this time, the voltage V _GS ≥Vth between the gate and source of the first NMOS transistor Q1, the first NMOS transistor Q1 is closed, and the drain potential of the first NMOS transistor Q1 is "0" at this time, and the second host 206 can "0" is received normally.

Refer to Figure 15, which is a schematic diagram of the working principle of the circuit shown in Figure 10 when the load capacitance is tested.

The first host 205 is the device under test. The positive pole (+ pole in the figure) of the RLC tester 208 is connected to the public ground through the interface 204, and the negative pole (- pole in the figure) of the RLC tester 208 is connected to the signal link under test. .

The drain potential of the first NMOS transistor Q1 is the same as the negative electrode of the RLC tester 208, and both are "0". Due to the action of the body diode, the source and drain potentials of the first NMOS transistor Q1 are the same as "0".

At this time, the gate potential of the second NMOS transistor Q2 and the positive electrode of the RLC tester 208 are the same as "1", then the voltage between the gate and the source of the second NMOS transistor Q2 is V _G'S' ≥ Vth, at this time The second NMOS transistor Q2 is turned on.

The drain potential of the second NMOS transistor Q2 and the source are the same as "0", and the gate potential of the first NMOS transistor Q1 and the drain of the second NMOS transistor Q2 are the same as "0". Therefore, the voltage between the gate and the source of the first NMOS transistor Q1 is V _GS <Vth, and the first NMOS transistor Q1 is turned off at this time.

Referring to FIG. 15, the load link length at this time is the link length between the RLC tester 208 and the drain of the first NMOS transistor Q1, and does not include the length between the first host 205 and the source of the first NMOS transistor Q1. The link length, therefore, shortens the signal link length, which in turn can reduce the load capacitance.

In order to show the beneficial effects of the present application in more detail and accurately, a load capacitance test is performed on the capacitive isolation circuit shown in FIG. 10. Specifically, the voltage of the power supply 207 is 3.3V, the first pull-up resistance R1=4.7kohm, the ground resistance R2=22ohm, the current limiting resistance R3=1kohm, and the interface is the HDMI interface to connect the CEC signal link in the HDMI Perform a load capacitance test. For comparison, the load capacitance test was performed on the direct connection of the first host directly to the second host through the HDMI cable, and the first host was used as the device under test. The test data obtained is shown in the following table.

Table 1: Comparison of load capacitance test data between the application scheme and the pass-through scheme

From the above test data, it can be determined that for each HDMI interface tested, when the device under test is powered on and when the device under test is not powered on, the load capacitance measurement result of the solution of this application is significantly less than the load capacitance measurement result of the pass-through solution .

It can be seen that the use of the capacitive isolation circuit provided by the embodiments of the present application can shorten the length of the signal link, thereby reducing the load capacitance. In addition, compared with the corresponding implementations in Figs. 1 and 2, the circuit structure is simple, the hardware cost is low, and there is no need to add a complex signal processing chip, so the signal response speed is fast, the power consumption is low, and there is no need to increase software development investment.

In the above embodiments, the first switch circuit and the second switch circuit are both an NMOS transistor as an example for description. Another implementation of the first switch circuit and the second switch circuit will be described below.

Circuit embodiment three:

Refer to FIG. 16, which is a schematic diagram of yet another capacitive isolation circuit provided by an embodiment of the application.

The first switch circuit 201 of the capacitive isolation circuit provided by the embodiment of the present application includes a first switch S1 and a first diode D1.

Wherein, the anode of the first diode D1 is connected to the first end of the first switch S1, and the cathode of the first diode D1 is connected to the second end of the first switch S1.

When the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first switch S1 is closed, and the first terminal and the second terminal of the first switch circuit 201 are turned on.

The second switch circuit 202 of the capacitive isolation circuit includes a second switch S2 and a second diode D2.

The anode of the second diode D2 is connected to the first end of the second switch S2, and the cathode of the second diode D2 is connected to the second end of the second switch S2.

When the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, the second switch S2 is closed, and the first terminal and the second terminal of the second switch circuit 202 are turned on.

The working principle of the capacitive isolation circuit will be described in detail below.

When the second host 206 sends "1" to the first host 205, the level of the second terminal of the first switch circuit 201 is "1", due to the voltage between the first terminal and the second terminal of the first switch circuit 201 The difference is a preset voltage value, and at this time, the level of the first terminal of the first switch circuit 201 is “1”. The control terminal of the first switch circuit 201 is pulled up to the power supply through the current limiting resistor R3, and the level is "1". Since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is less than the voltage threshold at this time, the first switch S1 is turned off at this time. The first pull-up circuit 203 has an enhancement effect on the first terminal signal of the first switch circuit 201, so the first host 205 can normally receive "1".

When the second host 206 sends "0" to the first host 205, the level of the second terminal of the first switch circuit 201 is "0", so the first terminal voltage of the first switch circuit is equal to the preset voltage value, that is, the first terminal voltage of the first switch circuit is equal to the preset voltage value. The voltage at one end is a small voltage value, which is a low level. The control terminal of the first switch circuit 201 is pulled up to the power supply through the current-limiting resistor R3, so the control terminal level is "1", so that the voltage difference between the control terminal of the first switch circuit 201 and the first terminal is greater than the voltage threshold. When a switch S1 is turned on, the potential of the first terminal of the first switch circuit 201 drops to "0", so that the first host 205 normally receives "0".

When the first host 205 sends "1" to the second host 206, the levels of the first terminal and the control terminal of the first switch circuit 201 are both "1", because the voltages of the control terminal and the first terminal of the first switch circuit 201 The difference is less than the voltage threshold, and the first switch S1 is turned off at this time. At this time, the level of the second terminal of the first switch circuit 201 is also "1", so the second host 206 can normally receive "1".

When the first host 205 sends "0" to the second host 206, the first terminal level of the first switch circuit 201 is "0", and the control terminal of the first switch circuit 201 is pulled up to the power supply 207 by the current limiting resistor R3 , The level is "1". Since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first switch is closed at this time, so that the second terminal of the first switch circuit 201 has a level of "0", so the second host can "0" is received normally.

For a system using the capacitive isolation circuit, when testing the load capacitance of the transmission link, the first host 205 is the device under test and is not powered on, and the power source 207 is not powered on. The positive pole of the tester is connected to the control terminal of the second switch circuit 202 through the interface 204. At this time, the level of the control terminal of the second switch circuit 202 is "1". The negative pole of the tester is connected to the second end of the first switch circuit 201 through the interface 204, and the level is "0". At this time, the levels of the first terminal, the second terminal and the control terminal of the first switch circuit 201 are all "0". At this time, the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, and the second switch S2 is closed, so that the potential of the control terminal and the first terminal of the first switch circuit 201 are the same, so that the first switch circuit The first switch of 201 is turned off. The load link length at this time is the link length from the tester to the second end of the first switch circuit, and does not include the link length from the first host to the first end of the first switch circuit, thus shortening the load link length , Which in turn can reduce the load capacitance.

In summary, the use of the capacitive isolation circuit provided by the embodiments of the present application can shorten the load link length and reduce the load capacitance. At the same time, the first pull-up circuit can ensure the signal transmission quality, the circuit structure is simple, the hardware cost is low, and There is no need to add a complicated signal processing chip, the signal response speed is fast, the power consumption is low, and there is no need to increase software development investment.

Circuit embodiment three:

In the above circuit embodiment, the first pull-up circuit is connected to the first end of the first switch circuit, and is used to enhance the signal transmitted to the first host and the signal sent by the first host to ensure the signal transmission quality. However, in practical applications, for application scenarios with long signal transmission links, there may still be a problem of insufficient transmission signal level. In order to solve this technical problem, the embodiment of the present application also provides another capacitive isolation circuit. The figure explains in detail.

Refer to FIG. 17, which is a schematic diagram of still another capacitive isolation circuit provided by an embodiment of the application.

The difference between the capacitive isolation circuit provided in the embodiment of the present application and the circuit shown in FIG. 3 is that it also includes a second pull-up circuit 208.

The second pull-up circuit 208 is connected to the second terminal of the first switch circuit 201 and is used to enhance the transmission signal on the second terminal side of the first switch circuit 201 to improve the signal transmission quality.

Further, in specific applications, the second pull-up circuit 201 may be implemented by a resistor, which is described below with reference to the accompanying drawings.

Refer to FIG. 18, which is a schematic diagram of another capacitive isolation circuit provided by an embodiment of the application.

FIG. 18 is based on the implementation shown in FIG. 10, and a second pull-up resistor R4 is added to the second end of the first switch circuit 201. The second terminal of the first switch circuit 201 is connected to the power supply 207 through the second pull-up resistor R4, so as to enhance the signal on the second terminal side of the first switch circuit 201, thereby ensuring the quality of signal transmission.

It can be understood that the first switch circuit and the second switch circuit in the capacitive isolation circuit are not limited to the implementation manners of the above circuit embodiments, but may also be other implementation manners that satisfy logic control. Go into details one by one.

Examples of docking stations:

Based on the capacitive isolation circuit provided by the above circuit embodiments, the embodiment of the present application also provides an expansion dock, which will be described in detail below with reference to the accompanying drawings.

Refer to FIG. 19, which is a schematic diagram of a docking station provided by an embodiment of the application.

The docking station 400 includes a capacitive isolation circuit and an interface 204.

Among them, the capacitive isolation circuit includes a first switch circuit 201, a second switch circuit 202, and a first pull-up circuit 203. For the specific implementation mode and working principle of the capacitive isolation circuit, reference may be made to the relevant description in the above embodiment, and the details are not repeated here in the embodiment of the present application.

One end of the docking station 400 is connected to the first host 205 through a cable, and the other end is connected to the second host through the interface 204, so that the signal sent by the second host 206 is sent to the first host 205 through the capacitive isolation circuit for playback .

It can be understood that when the docking station 400 is connected to the first host 205, the connection can be realized through a cable that comes with the host. At this time, the cable of the host may be detachable or non-detachable. The docking station 400 may also be connected to the host through its own cable, and the own cable may be detachable or non-detachable, which is not specifically limited in the embodiment of the present application.

In addition, in practical applications, the docking station 400 may have multiple interfaces 204, and each interface 204 can perform signal transmission. That is, the docking station 400 may be connected to multiple hosts through the multiple interfaces 204, respectively. The number is not specifically limited. The signals transmitted by each interface 204 can be connected to a signal before entering the second end of the first switch circuit 201 for transmission to the first host.

In an actual application scenario of the docking station 400, the docking station 400 may be the Dock box 102 in the scenario shown in FIG. 3, which is used to implement signal transmission between the TV host and the TV box. At this time, the interface 204 of the docking station 400 may include an HDMI interface. The docking station 400 is connected to the TV box through an HDMI cable, and CEC signals can be transmitted in the HDMI cable. At this time, the capacitive isolation circuit of the docking station 400 is used to reduce the transmission of CEC signals. Time link load capacitance and ensure the signal transmission quality between the TV host and the TV box.

It is understandable that in practical applications, in order to be more compatible, the docking station 400 may also have different types of interfaces 204 to achieve connection with different types of second hosts or to match different types of transmission signals. The specifics of the interface 204 are The types can be determined according to actual application scenario requirements, and the embodiments of the present application will not be described one by one here.

It can be understood that, in practical applications, the docking station 400 itself may not have a power source, and the power source 207 may be provided by the first host.

In summary, the capacitive isolation circuit of the docking station includes a first switch circuit, a second switch circuit and a first pull-up circuit. Wherein, the first end of the first switch circuit is connected to the first pull-up circuit, and the first end of the first switch circuit is also connected to the first host. The second end of the first switch circuit is connected to the interface, the interface is connected to the second host, and the control end of the first switch circuit is connected to the power supply. The control terminal of the second switch circuit is grounded, the first terminal of the second switch circuit is connected to the first terminal of the first switch circuit, and the second terminal of the second switch circuit is connected to the power supply. The voltage difference between the first terminal and the second terminal of the first switch circuit is a preset voltage value, and the principle of the preset voltage value is to enable the voltage of the first terminal and the second terminal of the first switch circuit to be determined The same level, that is, the same high level or the same low level. . When the second host inputs a high level to the second terminal of the first switch circuit, the first terminal of the first switch circuit is also at high level at this time. At this time, the first pull-up circuit signals the first terminal of the first switch circuit. It has an enhancement effect, so the high-level signal can be transmitted to the first host normally.

For the system using the capacitive isolation circuit, when testing the load capacitance of the transmission link, the positive pole of the tester is connected to the control end of the second switch circuit, which is high level, and the negative pole of the tester is connected to the first switch circuit through the interface. The second end is low level. When the first host is the device under test and is not powered on, the power supply is not powered on at this time, and the first terminal, the second terminal and the control terminal of the first switch circuit are all low level. The control terminal of the second switch circuit is connected to the positive terminal of the tester, so it is at a high level. The voltage difference between the control terminal of the second switch circuit and the first terminal is greater than the voltage threshold. At this time, the first terminal and the second terminal of the second switch circuit The terminal is turned on, so that the control terminal of the first switch circuit and the first terminal have the same potential, and the first terminal and the second terminal of the first switch circuit are disconnected. The load link length at this time is the link length between the tester and the second end of the first switch circuit, and does not include the link length between the first host and the first end of the first switch circuit. Therefore, in practical applications, the load link length can be approximated as the link length from the second host to the docking station, and the shortened load link length can be approximated as the link length from the first host to the docking station. The path length is greatly shortened, which in turn can reduce the load capacitance.

Therefore, using the expansion dock provided by the embodiments of the present application can shorten the load link length, reduce the load capacitance and ensure the quality of signal transmission, and the capacitive isolation circuit in the expansion dock has a simple structure, low hardware cost, and no need to add complex Signal processing chip, fast signal response speed, low power consumption, no need to increase software development investment.

Chip embodiment

Based on the capacitive isolation circuit described in the above embodiment, an embodiment of the present application also provides a capacitive isolation chip, which will be described in detail below with reference to the accompanying drawings.

Refer to FIG. 20, which is a schematic diagram of a capacitive isolation chip provided by an embodiment of the application.

The capacitive isolation chip 300 includes: a first input/output IO port IO1, a second IO port IO2, and a third IO port IO3.

Among them, the first IO port is connected to the first host 205, and the second IO port is used to connect to the second host 206 through the interface 204.

The voltage between the first IO port and the second IO port is a preset voltage value, and the principle of the preset voltage value is to enable the voltage of the first IO port and the second IO port to be determined to be the same level, that is, The same high level or the same low level.

When the voltage difference between the first IO port and the third IO port is greater than the voltage threshold, the first IO port and the second IO port are turned on, so that the first host 205 and the second host 206 can transmit signals.

The following description will be given in conjunction with specific implementations.

Refer to FIG. 21, which is a schematic diagram of another capacitive isolation chip provided by an embodiment of the application.

The implementation of the circuit isolation chip 500 corresponds to the capacitive isolation circuit shown in FIG. 10.

Among them, the first IO port is IO1, which is connected to the first host 205, and the first IO port is connected to the source of the first NMOS transistor Q1, the first pull-up resistor R1 and the source of the second NMOS transistor Q2 inside the capacitive isolation chip 500 pole.

The second IO port, IO2, is connected to the second host 206, and the second IO port is connected to the drain of the first NMOS transistor Q1 inside the capacitor isolation chip 500.

The third IO port, IO3, can be used as the power port VCC of the capacitor isolation chip 500 for connecting to the power supply 207. The third IO port is connected to the source of the first NMOS transistor Q1 through the first pull-up resistor R1 inside the capacitive isolation chip 500, and is connected to the gate of the first NMOS transistor Q1 through the current limiting resistor R3.

In addition, the capacitive isolation chip 500 further includes a ground port GND, which is connected to the gate of the second NMOS transistor Q1 through a ground resistor inside the capacitive isolation chip 500.

Refer to FIG. 22, which is a schematic diagram of a packaged capacitive isolation chip provided by an embodiment of the application.

The packaged capacitive isolation chip has four external interfaces, which are the first IO port IO1, the second IO port IO2, the third IO port IO3 (also the power port VCC), and the ground port GND.

It is understandable that the above is only one implementation of the capacitive isolation chip, and the capacitive isolation chip corresponding to the capacitive isolation circuit shown in FIG. 16 and FIG. 18 is similar, and the embodiments of the present application will not be repeated here.

The capacitive isolation chip provided in the embodiments of the present application can be used in scenarios where the signal transmission distance is long, the load capacitance requirement cannot be met, or the signal driving force cannot be met. In a possible application scenario, the capacitive isolation chip can be applied to the Dock box shown in FIG. 4 to reduce the load capacitance of the link between the TV host and the TV box.

In summary, the capacitive isolation circuit of the capacitive isolation chip uses two switching circuits to shorten the signal link length and thereby reduce the load capacitance. At the same time, the pull-up circuit can also play a role in signal enhancement, so it can guarantee the signal Transmission quality. In addition, the capacitive isolation chip has a simple structure and low hardware cost. Compared with a complex signal processing chip, the signal response speed is fast and the power consumption is low, and there is no need to increase software development investment.

Examples of playback system:

The embodiments of the present application also provide a playback system, which will be described in detail below with reference to the accompanying drawings.

Refer to FIG. 23, which is a schematic diagram of a video playback system provided by an embodiment of the application.

The playback system 600 includes a docking station 400 and a first host 205.

The first host 205 is connected to the docking station 400 through a transmission cable. The transmission cable and the first host 205 can be connected in a detachable or non-detachable manner. The transmission cable and the docking station 400 can be connected in a detachable manner. The detachable connection mode may also be a non-detachable connection mode, which is not specifically limited in the embodiment of the present application.

The docking station 400 sends the signal sent by the second host 206 to the first host 205 so that the first host 205 can play corresponding content.

The following takes a TV broadcasting system as an example for specific description.

For the TV playback system, the TV host is connected to the video source host through an HDMI cable. When the HDMI link is long, the link load capacitance of the CEC signal transmitted on the HDMI link cannot meet the link load capacitance specification requirements, which leads to the TV The host cannot receive the signal normally.

Continuing to refer to the scene shown in FIG. 4, when the playback system provided in the embodiment of the present application is applied, the first host is a TV host, and the second host is a video source host, that is, a TV box. At this time, the docking station 400 (that is, the Dock box) is used to send the content sent by the video source host to the TV host, so that the TV host can play.

The expansion dock provided by the present application includes a capacitive isolation circuit. Based on the description of the above embodiment, the load link length after using the capacitive isolation circuit is the link between the second host and the second end of the first switch circuit of the capacitive isolation circuit The length does not include the length of the link between the first host and the first end of the first switch circuit, so the load link length can be shortened, the load capacitance can be reduced, and the signal transmission quality can be guaranteed, thereby ensuring the playback system The TV host can normally play the content sent by the video source host.

It should be understood that in this application, "at least one (item)" refers to one or more, and "multiple" refers to two or more. "And/or" is used to describe the association relationship of the associated objects, indicating that there can be three kinds of relationships, for example, "A and/or B" can mean: only A, only B, and both A and B. , Where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "The following at least one item (a)" or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a). For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ", where a, b, and c can be single or multiple.

The above are only preferred embodiments of the application, and do not limit the application in any form. Although this application has been disclosed as above in preferred embodiments, it is not intended to limit the application. Anyone familiar with the art, without departing from the scope of the technical solution of the present application, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present application, or amend to be equivalent to equivalent changes. Examples. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the application without departing from the content of the technical solution of the application still fall within the protection scope of the technical solution of the application.

Claims

A capacitive isolation circuit, characterized by comprising: a first switch circuit, a second switch circuit, and a first pull-up circuit;

The first end of the first switch circuit is connected to the first pull-up circuit, and the first end of the first switch circuit is also used to connect to a first host;

The second end of the first switch circuit is used to connect to an interface; the interface is used to connect to a second host;

The control end of the first switch circuit is connected to a power source;

The control terminal of the second switch circuit is grounded, the first terminal of the second switch circuit is connected to the first terminal of the first switch circuit, and the second terminal of the second switch circuit is connected to the power supply;

The voltage difference between the first terminal and the second terminal of the first switch circuit is a preset voltage value, and the preset voltage value is used to make the level of the first terminal and the second terminal of the first switch circuit The state is guaranteed to be consistent;

When the voltage difference between the control terminal and the first terminal of the first switch circuit is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit are turned on; the control terminal of the second switch circuit is connected to the first terminal. When the voltage difference between the terminals is greater than the voltage threshold, the first terminal and the second terminal of the second switch circuit are turned on.
The circuit according to claim 1, wherein the first pull-up circuit comprises: a first pull-up resistor;

The first terminal of the first switch circuit is connected to the power supply through the first pull-up resistor.
The circuit according to claim 1, wherein the first switch circuit is a first NMOS transistor, the first terminal of the first switch circuit is the source of the first NMOS transistor, and the first switch circuit is a source of the first NMOS transistor. The second terminal of the switch circuit is the drain of the first NMOS transistor, and the control terminal of the first switch circuit is the gate of the first NMOS transistor.
The circuit according to claim 1, wherein the second switch circuit is a second NMOS transistor, the first terminal of the second switch circuit is the source of the second NMOS transistor, and the second switch circuit is the source of the second NMOS transistor. The second terminal of the switch circuit is the drain of the second NMOS transistor, and the control terminal of the second switch circuit is the gate of the second NMOS transistor.
The circuit according to claim 1, wherein the first switch circuit comprises a first switch and a first diode;

The anode of the first diode is connected to the first end of the first switch, and the cathode of the first diode is connected to the second end of the first switch.
The circuit according to claim 1, wherein the second switch circuit comprises a second switch and a second diode;

The anode of the second diode is connected to the first end of the second switch, and the cathode of the second diode is connected to the second end of the second switch.
The circuit according to any one of claims 1-6, further comprising: a protection circuit;

The control terminal of the second switch circuit is grounded through the protection circuit;

The protection circuit is used to filter out interference signals.
The circuit according to claim 7, wherein the protection circuit comprises: a grounding resistance;

The control terminal of the second switch circuit is grounded through the grounding resistor.
The circuit according to any one of claims 1-6, further comprising: a current limiting resistor;

The control terminal of the first switch circuit is connected to the power supply through the current limiting resistor.
The circuit according to any one of claims 1-6, further comprising: a second pull-up circuit;

The second end of the first switch circuit is connected to the second pull-up circuit.
The circuit according to claim 10, wherein the second pull-up circuit comprises: a second pull-up resistor;

The second end of the first switch circuit is connected to the power supply through the second pull-up resistor.
A docking station, characterized by comprising the capacitive isolation circuit according to any one of claims 1-11, and further comprising: an interface;

The interface is used to connect to a second host, and is used to send a signal sent by the second host to the first host through the capacitive isolation circuit.
The docking station according to claim 12, wherein the interface is a high-definition multimedia interface HDMI interface.
A capacitive isolation chip, characterized by comprising: a first input/output IO port, a second IO port, and a third IO port;

The first IO port is used to connect to a first host;

The second IO port is used to connect to a second host through an interface;

The voltage difference between the first IO port and the second IO port is a preset voltage value, and the preset voltage value is used to make the power between the first IO port and the second IO port Consistent state

When the voltage difference between the first IO port and the third IO port is greater than the voltage threshold, the first IO port and the second IO port are turned on, so that the first host and the second host Transfer signals between hosts.
A playback system, characterized by comprising the docking station according to any one of claims 6-13, and further comprising: a first host;

The first host is connected to the docking station through a transmission cable;

The docking station is used to send a signal sent by the second host to the first host;

The first host is used to play the content.
The system according to claim 15, wherein the first host is a television host;

The second host is a video source host.