KR100733733B1 - Method for forming a semiconductor device - Google Patents

Abstract

A feature with sidewalls is formed on a semiconductor device substrate. Sidewalls of the feature are undercut, and an optional epitaxial semiconductor layer having a first portion and a second portion is formed on the semiconductor device substrate. A first portion of the optional epitaxial semiconductor layer is formed between the undercut sidewall and the semiconductor device substrate and has a surface covered by portions of the sidewall. The second portion of the optional epitaxial semiconductor layer is formed on the semiconductor device substrate and adjacent the sidewalls and includes a surface portion that is exposed and substantially parallel to the major surface of the semiconductor device substrate.

Epitaxial semiconductor layer, undercut, semiconductor device substrate, source / drain regions

Description

Method for forming a semiconductor device

1 is a cross-sectional view (prior art) showing a portion of a semiconductor device substrate having an elevated source / drain region with facets.

2 is a cross-sectional view of a portion of a semiconductor device substrate after forming patterned features on the semiconductor device substrate and doped regions in the semiconductor device substrate.

3 illustrates a cross-sectional view of the semiconductor device substrate of FIG. 2 after forming a liner layer and spacers.

4 illustrates a cross-sectional view of the semiconductor device substrate of FIG. 3 after removing portions of the liner layer and undercutting portions of the spacers.

FIG. 5 is a plot showing facet ratio versus etch time and undercutting versus etch time. FIG.

FIG. 6 is a cross-sectional view of the semiconductor device substrate of FIG. 4 after forming elevated source / drain regions in accordance with one embodiment of the present invention. FIG.

FIG. 7 illustrates a cross-sectional view of the semiconductor device substrate of FIG. 6 after forming heavily doped source / drain regions. FIG.

8 illustrates a cross-sectional view of the semiconductor device substrate of FIG. 7 after forming silicide regions.

9 illustrates a cross-sectional view of the semiconductor device substrate of FIG. 8 after forming a substantially completed device.

Explanation of symbols on the main parts of the drawings

10, 20: semiconductor device substrate 22, 36: features

24, 112: gate dielectric layer 26: gate electrode layer

28: antireflective layer 29, 116: extended area

32, 122: liner layers 34, 124: spacer

62: selective epitaxial semiconductor region

64, 1262, 1264: facet 66: optional polysilicon region

68, 69: surface

74, 126, 128: source / drain area

82: silicide region 90: ILD layer

92 contact opening 96 interconnect

98 passivation layer 114 gate electrode

1266: upper surface 1282: junction cross-sectional area

Related Applications
This application is directed to Agent No. SC90882A, filed on the same date and assigned to the current assignee, "How to Form a Semiconductor Device," which is incorporated herein by reference.
Field of invention

The present invention relates generally to methods of forming semiconductor devices, and more particularly to methods of forming semiconductor devices comprising selectively deposited epitaxial semiconductor layers.

Background of the Invention

The size of the features of the semiconductor device continues to challenge the processing capabilities of conventional implantation and silicide methods to form very shallow source / drain structures. Elevated source / drain structures, formed using selectively deposited epitaxial silicon, have been proposed as one possible alternative to meet the size requirements of future device generations. The elevated source / drain regions can serve as a sacrificial silicide layer and post-implant out diffusion source in the formation of the source / drain regions of the transistor. However, the benefits of elevated source / drain structures can be limited by process integration problems resulting from facets formed in selectively deposited epitaxial silicon.

1 includes an exemplary cross-sectional view of a portion of a semiconductor device having elevated source / drain regions with facets. More specifically, FIG. 1 includes a gate dielectric layer 112 and a gate electrode 114 formed on a semiconductor device substrate 10. Doped extension regions 116 are formed in the semiconductor substrate 10. The doped extension regions 116 are similar to lightly doped drain (LDD) regions, but they generally have a higher doping concentration than that of the LDD region.

The oxide liner layer 122 and the spacers 124 are formed along the sidewalls of the gate electrodes 114. After forming the spacers 124, a selective epitaxial deposition process is used to form the elevated source / drain regions 126. Facets 1262 and 1264, which are an artifact of the selective epitaxial deposition process, are formed at the edges of the elevated source / drain regions 126 near the spacer 124. In this particular embodiment, facets 1262 substantially lie along {111} crystal planes, facets 1264 lie along {311} crystal planes, and top 1261 lie along {100} crystal planes. The {100} crystal plane is also the crystal plane of the main surface of the semiconductor substrate 10. Doped source / drain regions 128 are formed in the semiconductor substrate 10. Doped source / drain regions 128 are formed using conventional ion implantation methods.

As shown in FIG. 1, the doped junction cross-section associated with the source / drain regions 128 is varied by facets formed in the elevated source / drain regions 126. The junction doping cross section is affected by the change in thickness of the elevated source / drain regions 126 associated with the facets 1262 and 1264. Those portions of elevated source / drain regions 126 having facets generally correspond to portions of elevated source / drain regions 126 that are non-uniform and thinner. Thinner portions of elevated source / drain regions 126 similarly correspond to regions in substrate 10 that are non-uniform in junction doping cross-section and extend deeper within substrate 10. Deeper, non-uniform bond doping cross-sections are undesirable for several reasons. First, this enlarges the area between the source / drain area and the substrate and increases the overall junction capacity. Second, locally deeper junctions result in a locally lower impurity concentration in the regions between the center of the source / drain regions 128 and the expansion regions 116. Since the distribution of impurity species is not optimal for the semiconductor device, the resistance between the source / drain regions 128 and the expansion regions 116 can be large. Larger resistance can affect the speed of operation of the device and is generally undesirable. Finally, locally deeper junction regions are also drain-induced-barrier because locally deeper junctions can extend source / drain regions laterally just below the spacer to move them closer to the gate edge. short channel effects, such as -lowering, which reduces the effective diffusion length.

One of the advantages is that the embodiments can be composed of existing treatments without the need to use or complicated materials. Standard preclean and etch can be used to remove the liner layer 32 and undercut the spacers, and the deposition process to form the selective epitaxial semiconductor layer is conventional. Thus, existing treatments can be used to form facet-selective epitaxial semiconductor layers with minimal risk of added contamination or scrap caused by new or additional processing steps.

The invention includes other alternative embodiments. According to the embodiments described in FIGS. 1-9, the gate electrode is formed before depositing the selective epitaxial semiconductor layer. In alternative embodiments, the gate electrode may be formed after forming the selective epitaxial semiconductor layer. According to this embodiment, the features are then dummy features of the formed gate electrodes, and an optional epitaxial semiconductor layer is formed after forming the dummy features. The dummy features have a shape similar to the features 36 shown in FIG. 3. After forming the optional epitaxial semiconductor layer, dummy features are removed and appropriate gate electrode materials are formed in place. According to this embodiment, the selective epitaxial semiconductor layer may be formed such that the facets are completely covered by the spacers (ie, formed between the spacer and the substrate) or, alternatively, the selective epitaxial semiconductor layer may have the facets of the spacer. It may be formed to extend beyond the range and be exposed (ie, the facets are only partially covered by the spacers). Extending the facets beyond the range of the spacer can be accomplished by making the angle of the facet small. Smaller angles of the facets can be advantageous because they reduce the vertical height of the selective epitaxial semiconductor layer adjacent to the gate edge, which can thus have a beneficial effect of reducing Miller capacitance effects.

In another alternative embodiment, instead of forming a shallowly doped extension region before forming deep source / drain regions, doped extension regions may be formed later. This embodiment may be advantageous because doped extension regions are not affected by the high temperatures typically required during source / drain annealing. This can be done by omitting the processing steps originally used to form the extended area 29 shown in FIG. The semiconductor device substrate is then processed to form a gate electrode, an optional epitaxial semiconductor layer and source / drain regions, similar to that shown in FIG. Spacers adjacent the gate electrode are then removed, and expansion implantation is then performed to form doped extensions in regions of the substrate between the selective epitaxial semiconductor layer and the gate electrode. If necessary, a short annealing is performed to properly activate and diffuse the doped extension regions. The spacers are then reformed adjacent to the gate electrode and processing continues to form a suitable semiconductor device substrate.

In another alternative embodiment, the present invention can be used to form bipolar transistors. In this particular embodiment, instead of forming a gate electrode, an outer base is formed that electrically contacts the doped regions (unique base) within the substrate. Liners, spacers or other insulating features may then be formed adjacent to the outer base similar to those shown in FIG. 3. The liner layer is then removed and undercut similar to the removal and undercutting of the liner layer 32 described in FIG. 4. An optionally deposited epitaxial semiconductor layer without facets is then formed similar to that described in FIG. 6. Finally, an ion implantation step and annealing are performed to dope the selectively deposited epitaxial semiconductor region and form an emitter to remove impurities from the selectively deposited epitaxial semiconductor region into the substrate, similar to those described in FIGS. 7 and 8. send. This embodiment has similar advantages to the embodiments described in FIGS. 1 to 9 in that the emitter junction can be formed without creating the non-uniform and deep junction cross-sectional areas observed in FIG. 1 of the prior art. Therefore, the possibility of causing junction spikes through the base to the collector or to the draft region of the collector is reduced.

An additional advantage of the embodiments described herein is that when the selective epitaxial silicon region is doped, it can be used as an external diffusion source of impurities in the substrate. It may be particularly advantageous to further dope the source / drain extension regions under the gate electrode using portions of the selective epitaxial silicon region extending below the spacer as an impurity external diffusion source.

The invention has been described by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

Those skilled in the art will recognize that the components in the drawings are shown briefly and clearly and are not necessarily drawn to scale. For example, the dimensions of some of the components in the figures may be exaggerated relative to other components to improve the understanding of embodiments of the present invention.

In accordance with one embodiment of the present invention, a feature having sidewalls is formed on a semiconductor device substrate. Sidewalls of the feature are undercut, and an optional epitaxial semiconductor layer having a first portion and a second portion is formed on the semiconductor device substrate. The first portion is formed between the undercut sidewall and the semiconductor device substrate and has a surface covered by the portions of the sidewall. The second portion is formed adjacent the sidewall and has a surface that is exposed and substantially parallel to the major surface of the semiconductor device substrate.

Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. 2 shows a cross-sectional view of the semiconductor device substrate 20. As used herein, a semiconductor device substrate includes a single crystal semiconductor wafer, a semiconductor wafer on an insulating substrate, or any other substrate used to form semiconductor devices. According to one embodiment, the partially formed features 22 are formed on portions of the semiconductor device substrate 20. In this particular embodiment, the partially formed features 22 are formed by subsequently forming a gate dielectric layer 24, a gate electrode layer 26 and an antireflective layer 28 on the semiconductor device substrate 20. The semiconductor device substrate 20 is then patterned and etched to define the partially formed features 22 shown in FIG. In this particular embodiment, the partially formed features 22 are gate electrode stacks. A thin oxide layer (not shown) is then formed on the exposed surfaces of the substrate 20 and the partially formed features 22, with the extension regions 29 using a ion implantation treatment step. It is formed in 20.

The antireflective layer 28 is then removed using a conventional thermal phosphoric acid solution. Liner layer 32 is then formed on substrate 20 and partially formed features 22, as shown in FIG. 3. In general, the liner layer is formed by thermal oxidation or by using other conventional deposition processes. In one embodiment, the liner layer 32 is a monolayer comprising an oxide. In another embodiment, the liner layer 32 may be formed using a plurality of layers or any material or combination of materials that may be selectively etched with respect to the spacers 34 and the underlying substrate 20 formed next. have. In this particular embodiment, the liner layer 32 is an oxide formed using a deposition process using tetraethylorthosilicate (TEOS) as the source gas. In general, the thickness of the liner layer is in the range of approximately 10-30 nm.

According to one embodiment, after the liner layer 32 is formed, spacers 34 are formed to define the substantially formed features 36 shown in FIG. 3. Generally, the spacers 34 are formed of silicon nitride and have a base width size 38 in the range of approximately 50-100 nm. Silicon nitride is generally deposited to an initial thickness in the range of approximately 50-120 nm and then etched back to form spacers 34. Etching processes for forming spacers are conventional, and those skilled in the art will appreciate that the cross section of the spacers may be affected by the etching process used to form the spacers.

After forming the spacers 34, etching is performed to remove portions of the liner layer 32 and to expose portions of the substrate 20. In addition, the etch also undercuts and removes portions of the liner layer below the spacers 34. The undercut amount is indicated by the size 42 shown in FIG. The amount of undercut is typically in the range of approximately 20-50 nm. However, those skilled in the art will appreciate that the amount of undercut can additionally be determined by the width of the spacers at the base. In this particular embodiment, the amount of undercut is 75% or less of the spacer 34 width at the base. However, the distance between the edge of the liner layer 32 and the gate electrode 26 is at least 15 to reduce the excessive increase in Miller capacitance effect between the elevated source / drain regions and gate electrode 26 formed next. Should be -20 nm. In addition, the amount of undercut may also be limited by the mechanical support requirements of the spacer 34. Too much undercut can increase the risk of spacer delamination.

According to one embodiment of the present invention, a preclean process is performed prior to etching the liner layer 32. Pre-cleaning treatments include conventional sulfuric acid and hydrogen-peroxide cleaning treatments followed by ammonium hydroxide and hydrogen-peroxide cleaning treatments. The liner layer 32 is then etched using a deionized water / hydrofluoric acid (HF) solution having a concentration of approximately 100 deionized water (100: 1) relative to HF 1. Other concentrations, other etchants, and isotropic plasma etch processes may also alternatively be used to etch liner layer 32 and form an undercut. For example, deionized water / HF solutions with concentrations of 50: 1 or 10: 1 can be used or buffered oxide etch (BOE) containing hydrofluoric acid and ammonium fluoride Can be used. Those skilled in the art can determine which etching treatments and chemicals should be used to acceptably control the undercut.

5 includes a plot of facet rate versus etch time and amount of undercut versus etch time using a 100: 1 deionized water / HF solution. For the purposes of this specification, the facet rate is the length of the {111} facet not covered by the spacer (ie not between the spacer 34 and the substrate 20) divided by the total length of the {111} facets. . Therefore, if the entire length of the {111} facet is covered by the spacer 34, the facet rate is zero. When the {111} facet is exposed (ie, not covered by the spacer 34), the facet rate increases. Therefore, FIG. 5 shows that the {111} facet amount is decreasing to approximately zero after approximately 170 seconds of etching time, or alternatively, after forming an undercut of approximately 30 nm in this particular embodiment.

Prior to forming the subsequently formed selective epitaxial film on the substrate, the substrate may be baked in a hydrogen environment using hydrogen (H 2) or hydrogen chloride (HCl) as the hydrogen source. A selective epitaxial deposition process is then used to form the selective epitaxial semiconductor regions 62 and the optional polysilicon regions 66 as shown in FIG. According to one embodiment of the present invention, the selective epitaxial semiconductor regions 62 are formed as selective epitaxial silicon regions. The thickness of the selective epitaxial silicon regions is typically in the range of approximately 10-100 nm. According to embodiments of the present invention, the epitaxial semiconductor regions 62 may be selective epitaxial silicon regions that are doped or undoped. The previously formed undercutting causes the facets 64 of the selective epitaxial semiconductor regions 62 to be formed between the spacers 34 and the substrate 20. Therefore, those portions of the selective epitaxial region 62 with facets are covered by the spacer and not exposed. This is in contrast to the exposed portions of the selective epitaxial region 62. The exposed portions of the optional epitaxial region 62 have a surface 68 that lies substantially along the {100} crystal plane and is substantially parallel to the major surface 69 of the semiconductor device substrate 20. In addition, in regions associated with surface 68, the thickness of the selective epitaxial region is substantially uniform. Selective polysilicon regions 66 are formed over the gate electrode 26. Regions 66 generally have a polycrystalline structure and usually have a "bread loaf" form.

Selective epitaxial deposition process parameters are conventional. For example, silicon sources such as trichlorosilane, dichlorosilane, silane, disilane, brominated silane, and the like can be used. The degree of selective deposition typically depends on the silicon source drug and the deposition temperature. Bromine-based silicon compounds show improved selectivity over chlorine-based compounds. Increasing the number of halogen atoms in the silicon source gas also improves selectivity. Therefore, hydrogen chloride or molecular chlorine may flow during some or all of the deposition cycle. When using dichlorosilane as the source gas, the deposition temperature is typically in the range of approximately 800-900 ° C. Those skilled in the art will appreciate that the deposition temperature can be controlled by increasing or decreasing the number of halogen atoms in the halogenated silicon source gas. For example, the deposition temperature for dichlorosilane is expected to be lower than the temperature for trichlorosilane. In addition to using selectively deposited epitaxial silicon to form the selective epitaxial semiconductor regions 62, the selective epitaxial regions 62 also include other optional materials including silicon germanium, silicon carbide, silicon germanium carbide, and the like. Can be formed using deposited films. In these cases, corresponding suitable source gases are used.

Next, an ion implantation step, indicated by arrow 72 in FIG. 7, is performed to form source / drain regions 74. The facetless deposition process described herein allows the doped source / drain regions 74 to be formed without creating the non-uniform and deeper junction cross-sectional regions 1282 observed in the prior art of FIG. 1. Therefore, unlike in the prior art, the junction formed by the ion implantation step is substantially constant and has an overall depth parallel to the main surface of the semiconductor device substrate 20. The change in depth across the junction is reduced so that the amount of junction region between the doped source / drain regions 74 and the substrate 20 is also reduced, thus reducing the overall junction capacity. In addition, the distribution of impurity species in the substrate after ion implantation is generally at the same depth over the entire length of the source / drain regions and more tightly distributed in the regions adjacent the extension regions 29. This reduces the resistance between the source / drain and extension regions and can reduce short channel effects, for example DIBL, as compared to the prior art. In addition, since the depth of the joint can be more tightly controlled, the device can be manufactured using tighter tolerances or reduced dimensions. This can improve the overall reliability and performance of the semiconductor device. After implanting impurities into the selectively deposited epitaxial silicon region 62 and the substrate 20, the substrate is then annealed to diffuse and activate the impurities, whereby the source / drain regions and extension regions of the substrate are Junctions are defined.

A self-aligned silicide process is then performed as shown in FIG. 8 to convert portions of the optional epitaxial layer to silicide regions 82. In this particular embodiment, cobalt is deposited on the substrate to react to form cobalt silicide regions 82. Cobalt that does not react is then removed from the sides of the spacers 34. This allows the silicide regions 82 to be formed without shorting the source / drain regions 74 to the gate electrodes. The thickness of the silicide regions 82 may vary. In this particular embodiment, the silicide regions 82 have thicknesses approximating the thickness of the selectively grown epitaxial regions 62 shown in FIGS. 6 and 7. In this manner, selectively grown epitaxial regions 62 are advantageously used as a sacrificial silicide layer.

The substantially completed device is then formed as shown in FIG. An interlevel dielectric (ILD) layer 90 is formed on silicide regions 82 and patterned to form contact openings 92. Conductive plug 94 and interconnect 96 are then formed for electrical connection with one of the silicide regions 82. The passivation layer 98 is then formed to lie at the best level of interconnects. Although not shown, other electrical connections may be made of gate electrodes 26 and other source / drain regions 74. Additionally, other ILD layers and interconnect levels may be formed to form more simplified semiconductor devices as needed.

One of the advantages is that the embodiments can be composed of existing treatments without the need to use or complicated materials. Standard preclean and etch can be used to remove the liner layer 32 and undercut the spacers, and the deposition process to form the selective epitaxial semiconductor layer is conventional. Thus, existing treatments can be used to form facet-selective epitaxial semiconductor layers with minimal risk of added contamination or scrap caused by new or additional processing steps.

The invention includes other alternative embodiments. According to the embodiments described in FIGS. 1-9, the gate electrode is formed before depositing the selective epitaxial semiconductor layer. In alternative embodiments, the gate electrode may be formed after forming the selective epitaxial semiconductor layer. According to this embodiment, the features are then dummy features of the formed gate electrodes, and an optional epitaxial semiconductor layer is formed after forming the dummy features. The dummy features have a shape similar to the features 36 shown in FIG. 3. After forming the optional epitaxial semiconductor layer, dummy features are removed and appropriate gate electrode materials are formed in place. According to this embodiment, the selective epitaxial semiconductor layer may be formed such that the facets are completely covered by the spacers (ie, formed between the spacer and the substrate) or alternatively, the selective epitaxial semiconductor layer may be formed by the facets of the spacer. It may be formed to extend beyond the range and be exposed (ie, the facets are only partially covered by the spacers). Extending the facets beyond the range of the spacer can be accomplished by making the angle of the facet small. Smaller angles of the facets can be advantageous because they reduce the vertical height of the selective epitaxial semiconductor layer adjacent to the gate edge, which can thus have a beneficial effect of reducing Miller capacitance effects.

In another alternative embodiment, instead of forming a shallowly doped extension region before forming deep source / drain regions, doped extension regions may be formed later. This embodiment may be advantageous because doped extension regions are not affected by the high temperatures typically required during source / drain annealing. This can be done by omitting the processing steps originally used to form the extended area 29 shown in FIG. The semiconductor device substrate is then processed to form a gate electrode, an optional epitaxial semiconductor layer and source / drain regions, similar to that shown in FIG. Spacers adjacent the gate electrode are then removed, and expansion implantation is then performed to form doped extensions in regions of the substrate between the selective epitaxial semiconductor layer and the gate electrode. If necessary, a short annealing is performed to properly activate and diffuse the doped extension regions. The spacers are then reformed adjacent to the gate electrode and processing continues to form a suitable semiconductor device substrate.

In another alternative embodiment, the present invention can be used to form bipolar transistors. In this particular embodiment, instead of forming a gate electrode, an outer base is formed that electrically contacts the doped regions (unique base) within the substrate. Liners, spacers or other insulating features may then be formed adjacent to the outer base similar to those shown in FIG. 3. The liner layer is then removed and undercut similar to the removal and undercutting of the liner layer 32 described in FIG. 4. An optionally deposited epitaxial semiconductor layer without facets is then formed similar to that described in FIG. 6. Finally, an ion implantation step and annealing are performed to dope the selectively deposited epitaxial semiconductor region and form an emitter to remove impurities from the selectively deposited epitaxial semiconductor region into the substrate, similar to those described in FIGS. 7 and 8. send. This embodiment has similar advantages to the embodiments described in FIGS. 1 to 9 in that the emitter junction can be formed without creating the non-uniform and deep junction cross-sectional areas observed in FIG. 1 of the prior art. Therefore, the possibility of causing junction spikes through the base to the collector or to the draft region of the collector is reduced.

An additional advantage of the embodiments described herein is that when the selective epitaxial silicon region is doped, it can be used as an external diffusion source of impurities in the substrate. It may be particularly advantageous to further dope the source / drain extension regions under the gate electrode using portions of the selective epitaxial silicon region extending below the spacer as an impurity external diffusion source.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. However, benefits, advantages, solutions to problems, and any component (s) that can be or assert any benefit, advantage, or solution are important and essential to some or all of the claims. It is not to be construed as an integral feature or component.

One of the advantages is that the embodiments can be composed of existing treatments without the need to use or complicated materials. Standard preclean and etch can be used to remove the liner layer 32 and undercut the spacers, and the deposition process to form the selective epitaxial semiconductor layer is conventional. Thus, existing treatments can be used to form facet-selective epitaxial semiconductor layers with minimal risk of added contamination or scrap caused by new or additional processing steps.

The invention includes other alternative embodiments. According to the embodiments described in FIGS. 1-9, the gate electrode is formed before depositing the selective epitaxial semiconductor layer. In alternative embodiments, the gate electrode may be formed after forming the selective epitaxial semiconductor layer. According to this embodiment, the features are then dummy features of the formed gate electrodes, and an optional epitaxial semiconductor layer is formed after forming the dummy features. The dummy features have a shape similar to the features 36 shown in FIG. 3. After forming the optional epitaxial semiconductor layer, dummy features are removed and appropriate gate electrode materials are formed in place. According to this embodiment, the selective epitaxial semiconductor layer may be formed such that the facets are completely covered by the spacers (ie, formed between the spacer and the substrate) or alternatively, the selective epitaxial semiconductor layer may be formed by the facets of the spacer. It may be formed to extend beyond the range and be exposed (ie, the facets are only partially covered by the spacers). Extending the facets beyond the range of the spacer can be accomplished by making the angle of the facet small. Smaller angles of the facets can be advantageous because they reduce the vertical height of the selective epitaxial semiconductor layer adjacent to the gate edge, which can thus have a beneficial effect of reducing Miller capacitance effects.

In another alternative embodiment, instead of forming a shallowly doped extension region before forming deep source / drain regions, doped extension regions may be formed later. This embodiment may be advantageous because doped extension regions are not affected by the high temperatures typically required during source / drain annealing. This can be done by omitting the processing steps originally used to form the extended area 29 shown in FIG. The semiconductor device substrate is then processed to form a gate electrode, an optional epitaxial semiconductor layer and source / drain regions, similar to that shown in FIG. Spacers adjacent the gate electrode are then removed, and expansion implantation is then performed to form doped extensions in regions of the substrate between the selective epitaxial semiconductor layer and the gate electrode. If necessary, a short annealing is performed to properly activate and diffuse the doped extension regions. The spacers are then reformed adjacent to the gate electrode and processing continues to form a suitable semiconductor device substrate.

In another alternative embodiment, the present invention can be used to form bipolar transistors. In this particular embodiment, instead of forming a gate electrode, an outer base is formed that electrically contacts the doped regions (unique base) within the substrate. Liners, spacers or other insulating features may then be formed adjacent to the outer base similar to those shown in FIG. 3. The liner layer is then removed and undercut similar to the removal and undercutting of the liner layer 32 described in FIG. 4. An optionally deposited epitaxial semiconductor layer without facets is then formed similar to that described in FIG. 6. Finally, an ion implantation step and annealing are performed to dope the selectively deposited epitaxial semiconductor region and form an emitter to remove impurities from the selectively deposited epitaxial semiconductor region into the substrate, similar to those described in FIGS. 7 and 8. send. This embodiment has similar advantages to the embodiments described in FIGS. 1 to 9 in that the emitter junction can be formed without creating the non-uniform and deep junction cross-sectional areas observed in FIG. 1 of the prior art. Therefore, the possibility of causing junction spikes through the base to the collector or to the draft region of the collector is reduced.

An additional advantage of the embodiments described herein is that when the selective epitaxial silicon region is doped, it can be used as an external diffusion source of impurities in the substrate. It may be particularly advantageous to further dope the source / drain extension regions under the gate electrode using portions of the selective epitaxial silicon region extending below the spacer as an impurity external diffusion source.

Claims (5)

In the method of forming a semiconductor device: Forming a gate electrode 22 on the substrate 20; Forming spacers (34) adjacent the gate electrode (22); Forming an exposed substrate 20 surface area, including exposing the substrate 20 surface area under the spacers 34 by undercutting the spacers 34; Forming an optional epitaxial semiconductor layer 62 on the exposed substrate 20 surface regions, wherein the optional epitaxial semiconductor layer 62 includes a first portion and a second portion, wherein the first portion Has a first surface 64 covered by the spacers 34, the second portion has a second surface 68 not covered by the spacers 34, and the second surface ( 68) forming the selective epitaxial semiconductor layer (62), parallel to the major surface (69) of the substrate (20); Implanting impurity species (72) into the selective epitaxial semiconductor layer (62); And Annealing the substrate 20, annealing the substrate 20 diffuses the impurity species, defines a source / drain region 74 junction within the substrate 20, and after annealing, the source Bonding / drain region 74 junctions have a depth that is the same depth along the entire portion below the selective epitaxial semiconductor layer 62 with respect to the major surface 69 of the substrate 20. And annealing the semiconductor device. In the method of forming a semiconductor device: Forming a gate electrode 22 having sidewalls on the substrate 20; Undercutting (42) portions of the sidewalls; Forming a doped selective epitaxial semiconductor layer 62 on the substrate 20, wherein the doped selective epitaxial semiconductor layer 62 comprises a first portion and a second portion, the first portion Has a first surface 64 covered by the sidewalls, the second portion has a second surface 68 which is not covered by the sidewalls, and the second surface 68 has the substrate ( Forming the doped selective epitaxial semiconductor layer (62), parallel to the major surface (69) of 20); And Annealing the doped selective epitaxial semiconductor layer 62 to diffuse impurities from the first portion to the substrate 20, wherein diffusing impurities from the first portion to the substrate 20 Annealing the doped selective epitaxial semiconductor layer (62) which forms doped extension regions (29) in a substrate (20). In the method of forming a semiconductor device: Forming a gate electrode 22 on the substrate 20; Forming an insulating layer (32) along sidewalls of the gate electrode (22) and on the substrate (20); Forming spacers 34 on the insulating layer 32, the spacers 34 having sidewall portions adjacent to the sidewalls of the gate electrode 22, the spacers 34 having the substrate 20 Forming said spacers having a bottom portion adjacent to; Removing the first portion of the insulating layer (32) to expose the first portion of the substrate (20); Removing a second portion (42) of the insulating layer (32) between the bottom portion and the substrate (20) to expose a second portion of the substrate (20); And Depositing an optional epitaxial semiconductor layer 62 selected from the group consisting of silicon, silicon carbide and silicon germanium on the first portion of the substrate 20 and on the second portion of the substrate 20, the Selective epitaxial semiconductor layer 62 includes a first optional epitaxial semiconductor layer portion and a second optional epitaxial semiconductor layer portion, wherein the first selective epitaxial semiconductor layer portion is the first portion of substrate 20. Formed on, covered by the spacers 34, the second selective epitaxial semiconductor layer portion is formed on the second portion of the substrate 20, and the second selective epitaxial semiconductor layer portion Has a surface 68 lying along the same crystal plane as the major surface 69 of the substrate 20, the second selective epitaxial semiconductor layer portion being the main table of the substrate 20. Depositing the selective epitaxial semiconductor layer 62, having a surface 68 parallel to 69, on the first portion of the substrate 20 and the second portion of the substrate 20. The method of forming a semiconductor device. In the method of forming a semiconductor device: Forming gate electrodes 22 on the substrate 20; Forming spacers (34) adjacent the gate electrodes (22); Removing portions of the insulating layer (32) formed prior to forming the spacers (34) to undercut the spacers (34) and to define exposed surface regions of the substrate (20); And Depositing an optional epitaxial semiconductor layer 62 on the exposed surface regions of the substrate 20, the epitaxial semiconductor layer comprising a first portion, a second portion, and a third portion, wherein The first portion has a first surface portion 64 covered by the spacers 34, and the third portion is not covered by the spacers 34 and has a major surface of the substrate 20. 69, having a third surface portion 68 parallel to the major surface 69 of the substrate 20, the second portion being between the first portion and the third portion. Disposed on and having a second surface portion, the inclination of the second surface portion relative to the major surface 69 of the substrate 20 is greater than the third surface relative to the major surface 69 of the substrate 20. The selective epitaxial semiconductor layer 62, which is greater than the slope of the portion 68, is exposed to the substrate 20. Depositing on the surface regions. In the method of forming a semiconductor device: Forming a dummy feature on the first region of the substrate 20; Forming an insulating layer (32) over the dummy feature and the substrate (20); Forming spacers (34) over the insulating layer (32) and adjacent sidewalls of the dummy feature; Undercutting the spacers (34) by removing portions of the insulating layer (32) between the spacers (34) and the substrate (20); Forming an optional epitaxial semiconductor layer 62 on the substrate 20, the selective epitaxial semiconductor layer 62 comprising a first portion and a second portion, wherein the first portion comprises the spacer ( 34 has a first surface 64 covered by the second and the second portion has a second surface 68 not covered by the spacers 34, the second surface 68 being the substrate. Forming the selective epitaxial semiconductor layer (62) on the substrate (20), parallel to the major surface (69) of (20); Removing portions of the dummy feature; And Forming a gate electrode (22) on said first region.

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