KR100487527B1 - Semiconductor device having elevated source/drain and method of the same - Google Patents

Abstract

A semiconductor device having an elevated source / drain and a method of manufacturing the same are provided. A semiconductor device having an elevated source / drain is provided. In this device, an active region is defined in a predetermined region of a semiconductor substrate, and a gate electrode crosses an upper portion of the active region. A first insulating film pattern and a second insulating film pattern are sequentially stacked on each of the sidewalls of the gate electrode. Silicon epitaxial layers adjacent the edges of the first and second insulating film patterns are formed on the active region. The edge of the first insulating film pattern protrudes from the edge of the second insulating film pattern and is covered with the silicon epitaxial layer, and the predetermined region of the silicon epitaxial layer is silicided. In this device manufacturing method, an active region is defined on a semiconductor substrate, and a gate electrode is formed across the active region. Subsequently, a first insulating film pattern and a second insulating film pattern that are sequentially stacked on the active regions on both sides of the gate electrode are formed, and a silicon epitaxial layer adjacent to the edges of the first and second insulating film patterns is formed on the active region. An edge of the first insulating film pattern in contact with the active region is formed to protrude from an edge of the second insulating film pattern, and a silicon epitaxial layer is formed to cover the protruding edge of the first insulating film pattern. Subsequently, at least a portion of the recon epitaxial layer is silicided.

Description

Semiconductor device with elevated source / drain and method for manufacturing same {SEMICONDUCTOR DEVICE HAVING ELEVATED SOURCE / DRAIN AND METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an elevated source / drain and a method of manufacturing the same.

As the semiconductor device is highly integrated, the length of the gate effective channel is reduced. Accordingly, punch through and short channel effects may occur in the transistor. In order to solve this problem, an elevated source / drain has been proposed in which a source / drain height is increased above a surface of a semiconductor substrate by using a selective epitexial growth (SEG) process. According to this method, a source / drain region having a shallow impurity diffusion layer can be formed in the semiconductor substrate to prevent short channel effects and punchthrough. In addition, the silicon epitaxial layer is silicided to form a silicide layer, thereby reducing contact resistance and improving conductivity.

Elevated source / drain formed by silicidating epitaxial layers grown on semiconductor substrates has some challenges to be solved. First, the silicon epitaxial layer grows in a constant direction on the surface of the semiconductor substrate. As a result, a facet is formed in which the edge of the silicon epitaxial layer becomes thinner. In the process of silicidating the silicon epitaxial layer, the relatively thin semiconductor substrate under the facet is silicided to form a silicide layer deeply toward the inside of the semiconductor substrate at the edge of the source / drain region. As a result, an electric field may be concentrated at the edge of the source / drain region so that a leakage current may flow into the semiconductor substrate.

Second, the transistors connected to the input and output terminals of the semiconductor device may be subjected to an electric shock by electrostatic discharge. Accordingly, an ESD protection curcuit is disposed at an input and an output terminal, and the ESD protection circuit includes transistors capable of withstanding high current and high voltage. As the silicide layer formed in the source / drain regions of these transistors is closer to the gate electrode, local thermal damage may occur at the junction of the transistor, which may destroy the transistor. In order to prevent this, the silicide layer formed on the source / drain may be spaced apart from the gate electrode by a predetermined distance, thereby providing a ballasting effect and preventing breakage of the transistor.

1 to 4 are process cross-sectional views for explaining the problems of the prior art.

Referring to FIG. 1, an isolation layer 102 is disposed in a predetermined region of a semiconductor substrate 100 to define an active region. The gate pattern 110 is formed in the active region. The gate pattern 110 includes a gate oxide layer 104, a gate electrode 106, and a gate capping insulating layer 108 that are sequentially stacked. Impurities are implanted into active regions on both sides of the gate pattern 110 to form a low concentration diffusion layer 112.

Referring to FIG. 2, a first insulating film and a second insulating film are conformally formed on the entire surface of the resultant product. The second insulating film, the first insulating film, and the gate capping insulating film 108 are sequentially anisotropically etched to form a first insulating film pattern 114 and a second insulating film pattern 116 that sequentially cover sidewalls of the gate electrode 106. do.

Referring to FIG. 3, impurities are formed in active regions on both sides of the gate electrode 106 by using the gate electrode 106, the first insulating layer pattern 114, and the second insulating layer pattern 116 as an ion implantation mask. Injecting to form a high concentration diffusion layer 120. As a result, source / drain regions 127 having an LED structure are formed in the active regions of both gate electrodes 106. Subsequently, the silicon epitaxial layer 118 is grown on the upper surface of the gate electrode 106 and the semiconductor substrate 100 exposed to both sides of the gate electrode 106. In this case, a facet 119 having a thin thickness is formed at an edge of the epitaxial layer 118 adjacent to the device isolation layer 102 or the first insulating layer pattern 114.

Referring to FIG. 4, the silicon epitaxial layer 118 is silicided to form a gate silicide layer 118a and a source / drain silicide layer on the gate electrode 106 and on the source / drain regions 127, respectively. 118b is formed. In this case, due to the facet 119 at the edge of the silicon epitaxial layer 118, the edge of the source / drain silicide layer 118b is adjacent to the first insulating layer pattern 114 in the region of the semiconductor substrate 100. ) Has a protrusion 122 facing toward the inside. When a voltage is applied to the source / drain regions 127, an electric field is concentrated on the protrusion 122. As a result, leakage current may flow from the source / drain regions 127 into the semiconductor substrate. This deteriorates the characteristics of the semiconductor device and causes the semiconductor device to not operate normally. By forming the silicon epitaxial layer 118 thickly, the protrusion 122 may be prevented from being formed in the source / drain silicide layer 118b. However, in general, since the silicon epitaxial layer is grown using a sputtering method, silicon particles may adhere to the outer sidewall of the second insulating layer pattern 116 during the growth of the silicon epitaxial layer 118. The silicon particles adhered to the outer sidewall of the second insulating layer pattern 116 undergo a silicidation process and then electrically connect the gate silicide layer 118a and the source / drain silicide layer 118b. Can be. This problem becomes more serious as the silicon epitaxial layer 118 is formed thicker.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having a silicide layer having a flat surface in contact with a source / drain region, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a low resistance of a source / drain and a gate, and a method of manufacturing the same.

Furthermore, the present invention provides a semiconductor device and a method for manufacturing the same, which can prevent the transistor from being destroyed by thermal damage by uniformly distributing heat generated in the transistor in the ESD protection circuit.

In order to achieve the above objects, the present invention provides a semiconductor device having an elevated source / drain. The apparatus includes an active region defined in a predetermined region of a semiconductor substrate, and a gate electrode crossing the upper portion of the active region. A first insulating film pattern and a second insulating film pattern are sequentially stacked on each of the sidewalls of the gate electrode. Silicon epitaxial layers adjacent to edges of the first and second insulating layer patterns are formed on the active region. An edge of the first insulating film pattern protrudes from the edge of the second insulating film pattern and is covered with the silicon epitaxial layer, and a predetermined region of the silicon epitaxial layer is silicided.

In one embodiment of the present invention, the first insulating film pattern and the second insulating film pattern may have an 'L' shape. The 'L' shaped first and second insulating layer patterns have vertical and horizontal portions, respectively. The vertical portion of the 'L' shaped first insulating layer pattern is formed on the sidewall of the gate electrode, and the horizontal portion extends from the vertical portion and is formed on the active region. The 'L' shaped second insulating film pattern is formed on the first insulating film pattern in the form of the first insulating film pattern. The horizontal edge of the first 'L' shaped insulating layer pattern protrudes from the horizontal edge of the second 'L' shaped insulating layer pattern to cover the source / drain silicide layer.

In another embodiment of the present invention, the semiconductor device may further include a barrier insulating layer pattern conformally covering the predetermined regions of the 'L' shaped first and second insulating layers and the silicon epitaxial layer. At this time, the silicon epitaxial layer exposed next to the barrier insulating film is silicided.

In another embodiment of the present invention, a sidewall insulating film pattern is formed on each of the sidewalls of the gate electrode, and the first insulating film pattern and the second insulating film pattern are sequentially stacked on the sidewall insulating film and a predetermined region of the active region. Covered with foam. A source / drain silicide layer adjacent to the first and second insulating layer patterns is formed on the active region. The source / drain silicide layer is a silicided silicon epitaxial layer.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having an elevated source / drain. The method includes defining an active region in a semiconductor substrate and forming a gate electrode across the active region. A first insulating layer pattern and a second insulating layer pattern are sequentially formed on active regions on both sides of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating film pattern in contact with the active region is formed to protrude from the edge of the second insulating film pattern, and the silicon epitaxial layer covers the protruding edge of the first insulating film pattern. Form. Subsequently, at least a portion of the silicon epitaxial layer is silicided.

In the present invention, the first and second insulating layer patterns may be formed to have an 'L' shape. A gate that selectively grows a silicon epitaxial layer on the active region and the gate electrode exposed next to the 'L' shaped first and second insulating layer patterns, and silicides the silicon epitaxial layer to cover an upper portion of the gate electrode A silicide layer and a source / drain silicide layer covering the active region are formed.

Specifically, the first insulating film, the second insulating film, and the third insulating film are sequentially formed on the entire surface of the semiconductor substrate on which the gate electrode is formed to form the 'L' shaped first and second insulating film patterns. It is preferable that the second and third insulating films have a high etching selectivity with the first insulating film, and the second insulating film and the third insulating film also preferably have some etching selectivity. Subsequently, the third insulating film, the second insulating film, and the first insulating film are sequentially anisotropically etched to form first and second insulating film patterns and a third pattern, which are sequentially stacked. The first and second insulating layer patterns sequentially stacked have an 'L' shape structure composed of vertical and horizontal portions, respectively. Vertical portions of the 'L' shaped first and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and horizontal portions are sequentially stacked on the active region. The third insulating layer pattern is formed on the 'L' shaped second insulating layer pattern and has a curved sidewall. The third insulating film pattern is isotropically etched to expose the second insulating film pattern. At this time, the second insulating film pattern has an etching selectivity with the third insulating film pattern, but the portion of the vertical and horizontal edges of the second insulating film pattern is also etched while the isotropic etching is performed. Accordingly, the horizontal edge of the first insulating layer pattern protrudes out of the second insulating layer pattern.

Alternatively, the silicon epitaxial layer is formed and sequentially stacked to form the 'L' shaped first and second insulating film patterns and the first and second barrier insulating film patterns conformally covering a portion of the silicon epitaxial layer. It may further include doing. The first and second insulating layer patterns prevent the silicon epitaxial layer from being silicided so that the source / drain silicide layers are aligned with edges of the first and second barrier insulating layer layers that are sequentially stacked on the active region. Is formed.

Alternatively, the present invention includes forming a gate insulating film across the active region and forming a sidewall insulating film pattern on the sidewalls of the gate electrode. The first barrier insulation layer pattern and the second barrier insulation layer pattern are sequentially stacked on the sidewall insulation layer pattern and the predetermined region of the active region to conformally cover the sidewall insulation layer pattern and the active region. The edge of the first barrier insulating film pattern is formed to protrude from the edge of the second barrier insulating film pattern. A silicon epitaxial layer is grown on the gate electrode and the active region exposed to both sides of the barrier insulating layer patterns, and the silicon epitaxial layer is silicided to form a source / drain silicide layer. The silicon epitaxial layer is grown to cover an edge of the protruding first insulating layer pattern, and the source / drain silicide layer is formed on the active region adjacent to edges of the first and second insulating layer patterns.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be 'on' another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

5 is a perspective view for explaining the structure of a semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 5, the device isolation layer 202 is disposed in a predetermined region of the semiconductor substrate 200. The device isolation layer 202 defines an active region. A gate electrode 206 intersects the active region, and a gate oxide film 204 is interposed between the gate electrode 206 and the active region. The first insulating layer pattern 214a and the second insulating layer pattern 216a sequentially cover the sidewalls of the gate electrode 206. The first and second insulating layer patterns 214a and 216a have at least a vertical portion 220 sequentially covering sidewalls of the gate electrode 206 and a horizontal portion 222 sequentially covering the semiconductor substrate. Therefore, the first and second insulating layer patterns 214a and 216a have an 'L'-shaped cross section along a direction crossing the gate pattern 210. In the horizontal part 222, the first insulating layer pattern 214a has a protrusion 217 extending outwardly of the second insulating layer pattern 216a. A gate silicide layer 224a is present on the gate electrode 206, and a source / drain silicide layer 224b is present on an active region next to the first insulating layer pattern 216a. The source / drain silicide layer 224b covers the protrusion 217 of the first insulating layer pattern 214a. Accordingly, the source / drain silicide layer 224b has a structure in which the top surface thereof is wider than the width of the bottom surface in contact with the semiconductor substrate 200. Source / drain regions 227 are present in active regions on both sides of the gate pattern 210. The source / drain regions 227 may be formed of, for example, an LED structure. That is, the source / drain region 227 may be composed of a lightly doped diffusion layer 212 and a heavy doped diffusion layer 226. The low concentration diffusion layer 212 is present under the edge of the gate oxide layer 204 and under the vertical portion 220 of the first and second insulating layer patterns 214a and 216a, and the high concentration diffusion layer 226 The first and second insulating layer patterns 214a and 216a may be disposed under the horizontal portion 222 and under the source / drain silicide layer 224b. The high concentration diffusion layer 226 may have a structure deeper under the source / drain silicide layer 224b than under the first and second insulating layer patterns 214a and 216a.

As shown, unlike the prior art, the source / drain silicide layer 224b of the semiconductor device of the present invention has no protrusion (122 in FIG. 4) at its edge. That is, the source / drain silicide layer 224b is in flat contact with the semiconductor substrate 200. Therefore, concentration of the electric field can be prevented when a voltage is applied to the source / drain regions. As a result, leakage current flowing from the source / drain into the semiconductor substrate can be prevented as compared with the prior art, and stable operation characteristics of the device can be obtained.

6 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 6, an isolation region 202 is formed in a predetermined region of the semiconductor substrate 200 to define an active region. A gate pattern 210 is formed across the active region. The gate pattern 210 may include a gate electrode 206 crossing the active region and a gate oxide layer 204 interposed between the gate electrode 206 and the active region. In addition, the gate capping insulating layer 208 may be further included on the gate electrode 206. The gate oxide film 204 is preferably formed of a silicon oxide film. Subsequently, impurities are implanted into active regions on both sides of the gate pattern 210 to form a low concentration diffusion layer 212.

Referring to FIG. 7, first to third insulating layers 214, 216, and 218 are conformally formed on the entire surface of the resultant light having the low concentration diffusion layer 212 formed thereon. The first insulating layer 214 may be formed of a material having an etching selectivity with respect to the second and third insulating layers 218. For example, the first insulating film 214 may be formed of a silicon oxide film having a thickness of 100 to 500 Å, and the second insulating film 216 and the third insulating film 218 may be formed of a silicon nitride film or a silicon oxynitride film. Do. When both the second insulating film 216 and the third insulating film 218 are formed of a silicon nitride film, the second insulating film 216 is formed at a temperature of 770 ° C. to 850 ° C. and 0.1 to 0.5 Torr. High Temperature Nitride and the third insulating film 218 are formed of low temperature silicon nitride (LTN; Low Temperature Nitride) formed at 660 ° C to 700 ° C and 1 to 100 Torr so as to have etching selectivity with each other. desirable. Alternatively, the second insulating film 216 may be formed of a silicon nitride film, and the third insulating film 218 may be formed of a silicon oxynitride film.

Referring to FIG. 8, a first insulating layer pattern sequentially anisotropically etching the third insulating layer 218, the second insulating layer 216, and the first insulating layer 214 to cover sidewalls of the gate pattern 210. 214a, the second insulating film pattern 216a, and the third insulating film pattern 218a are formed. The first insulating layer pattern 214a and the second insulating layer pattern 216a have a 'L' shaped cross section along a direction crossing the gate electrode 210. That is, the first insulating layer pattern 214a and the second insulating layer pattern 216a have a vertical portion 200 covering sidewalls of the gate pattern 210. In addition, the first insulating layer pattern 214a and the second insulating layer pattern 216a extend from a lower portion of the vertical portion 200 in a direction crossing the gate pattern 210 to cover the active region ( horizontal portion; 222. The third insulating layer pattern 218a may have a spacer shape covering a sidewall of the vertical portion 220 and an upper surface of the horizontal portion 222.

9, the first and second insulating layer patterns 214a and 216a sequentially isotropically etch the third insulating layer pattern 218a and the gate capping insulating layer 208 to cover the sidewalls of the gate electrode 206. The gate electrode 206 is exposed. The third insulating layer pattern 218a may be isotropically etched using a phosphoric acid solution. While the third insulating layer pattern 218a is etched, the second insulating layer pattern 216a at the edge of the vertical portion 220 and the horizontal portion 222 is also etched. As a result, the first insulating layer pattern 214a protrudes outward from the second insulating layer pattern 216a at the edges of the vertical portion 220 and the horizontal portion 222. Subsequently, a selective epitaxial growth (SEG) process is applied to the semiconductor substrate from which the third insulating layer pattern 218a has been removed, and is formed on the upper surface of the gate electrode 206 and both sides of the gate electrode 206. The silicon epitaxial layer 224 is grown on the exposed active region. As illustrated, the silicon epitaxial layer 224 is formed on an upper portion of the protrusion 217 of the first insulating layer pattern 214a protruding out of the second insulating layer pattern 216a from the edge of the horizontal portion 222. Form to cover. For example, when the first insulating film 214 is formed to have a thickness of 100 kV, the silicon epitaxial layer 224 may be formed to have a thickness of about 300 kW. In addition, before the silicon epitaxial layer 224 is formed, it is preferable to remove the native oxide film formed on the exposed active region and the surface of the gate pattern 210. For example, hydrogen may be flowed onto the surface of the semiconductor substrate 200, and then subjected to a heat treatment at 900 ° C. for about 1 minute, and then the SEG process may be performed immediately. Subsequently, impurities are injected into the active regions of both the gate electrodes 206 through the silicon epitaxial layer, the first insulating layer pattern 214a, and the second insulating layer pattern 216a to form a high concentration diffusion layer 226. do. As a result, a source / drain 227 having an LED structure including a low concentration diffusion layer 212 and a high concentration diffusion layer 226 is formed in the active regions of both gate electrodes 206.

The high concentration diffusion layer 226 may be formed prior to forming the silicon epitaxial layer 224. In this case, since impurities are injected through the horizontal portions of the first insulating film pattern 214a and the second insulating film pattern 216a, high concentrations are formed below the first insulating film pattern 214a and the second insulating film pattern 216a. The depth of the diffusion layer 226 is formed relatively low. Accordingly, the high concentration diffusion layer 226 is formed shallower in the lower portion of the horizontal portion 222 to prevent the occurrence of punchthrough, and is formed deeper in the lower portion of the epitaxial layer 224 to resist the source / drain regions 227. Can be lowered.

Referring to FIG. 10, a metal film 228 is conformally formed on the entire surface of the semiconductor substrate on which the silicon epitaxial layer 224 and the source / drain 227 are formed. The metal layer 228 is a material capable of forming silicide by reacting with silicon in the silicon epitaxial layer 224. For example, the metal layer 228 may be formed of nickel (Ni), cobalt (Co), or titanium (Ti). Do. It is preferable to remove the native oxide film grown on the surface of the silicon epitaxial layer 224 before forming the metal film 228. The natural oxide film may be removed using isotropic etching. During the removal of the natural oxide layer, the first insulating layer pattern 214a protruding from the edge of the vertical portion 220 over the second insulating layer pattern 216a is also removed to remove the upper sidewall of the gate electrode 206. sidewall) is exposed.

Subsequently, a first heat treatment process is performed on the semiconductor substrate 200 on which the metal film 228 is formed to diffuse metal atoms constituting the metal film 228 into the silicon epitaxial layer 224. Similarly, metal atoms are also diffused on the gate electrode 206 through the exposed upper side wall of the gate electrode 206. The first heat treatment process is preferably performed for about 45 seconds at 450 ℃ to 500 ℃. The metal atoms diffused into the silicon epitaxial layer 224 are partially bonded to silicon to form silicides, and some of them are unbonded between the silicon atoms. Subsequently, the metal film 228 remaining without diffusion into the epitaxial layer 224 is removed. The remaining metal film 228 is preferably removed using isotropic etching using, for example, sulfuric acid solution (H ₂ SO ₄ ). The epitaxial layer 224 is completely silicided by performing a second heat treatment process on the semiconductor substrate 200 from which the metal film 228 is removed. As a result, a gate silicide layer 224a and a source / drain silicide layer 224a are formed on the top of the gate electrode 206 and on the active regions on both sides of the gate electrode 206. The second heat treatment step is preferably performed for about 30 seconds at 800 ℃ to 900 ℃.

Before performing the second heat treatment process, an etch stop layer 230 may be formed on the entire surface of the semiconductor substrate from which the metal layer 228 is removed. The etch stop layer 230 prevents the silicide layer 224a from being over-etched in a subsequent contact hole forming process. In addition, the etch stop layer 230 may serve to help the epitaxial layer 224 to be silicided evenly in the process of performing the second heat treatment process by applying a constant stress to the epitaxial layer 224. do. The etch stop layer 230 may be formed of silicon oxynitride. As shown, the protrusion 217 of the first insulating layer pattern 214a serves to prevent the diffusion of metal elements during the first and second heat treatment processes. Accordingly, the metal diffused below the facet of the edge of the epitaxial layer 224 is not diffused into the semiconductor substrate 200 by the protrusion 217 of the first insulating layer 214a. As a result, the contact surfaces of the source / sill silicide layer 224a and the semiconductor substrate 200 can be flat to significantly reduce the concentration of the electric field compared to the prior art.

Subsequently, although not shown, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 200 on which the silicide layer 224a is formed by using a conventional method, and wiring is formed.

12 is a perspective view illustrating a structure of a semiconductor device according to a second exemplary embodiment of the present invention.

Referring to FIG. 12, an isolation layer 302 is disposed in a predetermined region of a semiconductor substrate 300. The device isolation layer 302 defines a first active region 10 and a second active region 20. The first active region 10 is a reverse region where transistors of a cell transistor or a peripheral circuit of a memory device such as DRAM and SRAM are formed, and the second active region 20 includes an electrostatic discharge protection curcuit (ESD). protection curcuit). The first gate electrode 306a and the second gate electrode 306b cross the upper portions of the first active region 10 and the second active region 20, respectively. A gate oxide film 304 is interposed between the first gate electrode 306a and the first active region 10 and between the second gate electrode 306b and the second active region 20. The first insulating layer pattern 314a and the second insulating layer pattern 316a sequentially cover sidewalls of the first and second gate electrodes 306a and 306b. The first and second insulating layer patterns 314a and 316a have an “L” shaped cross section having a vertical portion 320 and a horizontal portion 322. The vertical portion 320 is formed on sidewalls of the first and second gate electrodes 306a and 306b, and the horizontal portion 322 is the first active region 10 or the second active region 20. Is formed on the phase. A first gate silicide layer 324c is formed on the first gate electrode 306a, and horizontal edges of the first and second insulating layer patterns 314a and 316a are formed on the first active region 10. The first source / drain silicide layer 324a adjacent to the lateral edge is formed. A silicon epitaxial layer 324 is formed on the second gate electrode 306b, and silicon adjacent to side edges of the first and second insulating layer patterns 314a and 314b is formed on the second active region 20. An epitaxial layer 324 is formed. First and second barrier insulating layer patterns 332a and 334a sequentially conform to cover the 'L' shaped first and second insulating layer patterns 314a and 316a formed on both sides of the second gate electrode 306b. The first and second barrier insulating layer patterns 332a and 334a extend laterally to cover a predetermined region of the silicon epitaxial layer 324. A second source / drain silicide layer 324b is formed on the second active region 20 at the horizontal edges of the first and second barrier insulating patterns 332a and 334a. The second source / drain silicide layer 324b is a silicide of the silicon epitaxial layer 324. A predetermined region of the silicon epitaxial layer 324 on the second gate electrode 306b is silicided to form a second gate silicide layer 324d. The second gate silicide layer 324d is disposed between the barrier insulating layer patterns formed on both sides of the second gate electrode 306b.

An impurity diffusion layer 327 adjacent to the first gate electrode 306a is formed in the first active region 10, and a source / drain adjacent to the second gate electrode 306b in the second active region 20 is formed. 327 is formed. The source / drain may be formed of a low concentration diffusion layer 312 formed under the horizontal portion 320 of the first and second insulating layer patterns 332a and 334a and a high concentration diffusion layer formed on sidewalls of the second insulating layer pattern 334a. 326. The high concentration diffusion layer 326 is formed shallower below the horizontal portion 322 of the first and second insulating layer patterns 332a and 334a, and the silicon epitaxial layer 324 and the source / drain silicide layer 324a, It may be deeply formed at the bottom of 324b). That is, the source / drain 327 may have an LED structure.

In the present invention, the first and second gate silicide layers 324c and 324d contact the first and second gate electrodes 306a and 306b, respectively, and the first and second source / drain silicide layers 324a are respectively. And 324b are in flat contact with the semiconductor substrates of the first and second active regions 10 and 20, respectively. The first source / drain silicide layer 324a is a silicide of the selective epitaxially grown silicon layer. Since the facet of the silicon epitaxial layer grown on the first active region 10 is located on the 'L' shaped first insulating layer pattern 314a, the first source / drain silicide layer 324a is formed. May be in flat contact with the semiconductor substrate of the first active region 10. In addition, since the second source / drain silicide layer 324b is formed in alignment with the horizontal edges of the first and second barrier insulating layer patterns 332a and 334a, Can be in flat contact.

13 to 20 are cross-sectional views illustrating a second embodiment of the present invention.

Referring to FIG. 13, an isolation layer 302 is formed in a predetermined region of a semiconductor substrate to define a first active region 10 and a second active region 20. The second active region 20 is a region in which a transistor connected to an input / output terminal of a semiconductor device is to be formed. For example, the second active region 20 includes a transistor forming an electrostatic discharge protection curcuit. Can be formed. A first gate electrode 306a is formed to cross the upper portion of the first active region 10, and a second gate electrode 306b is formed to cross the upper portion of the second active region 20. A gate insulating layer 304 is interposed between the first gate electrode 306a and the first active region 10 and between the second gate electrode 306b and the second active region 20, respectively. A low concentration diffusion layer 312 is formed in each of the first and second active regions 10 and 20 to be aligned with sidewalls of the first gate electrode 306a and the second gate electrode 306b. A gate capping insulating layer (not shown) may be further included on the first gate electrode 306a and the second gate electrode 306b.

Referring to FIG. 14, first to third insulating layers 314, 316, and 318 are conformally formed on the entire surface of the resultant lightly formed diffusion layers 312. The first to third insulating layers 314, 316, and 318 may be formed in the same manner as in the first embodiment.

Referring to FIG. 15, anisotropic etching of the third insulating layer 318, the second insulating layer 316, and the first insulating layer 314 is performed to sequentially form sidewalls of the first and second gate patterns 306a and 306b. The first insulating film pattern 314a, the second insulating film pattern 316a, and the third insulating film pattern 318a which are sequentially stacked on the substrate are formed. The first to third insulating layer patterns 314a, 316a, and 318a stacked in this order have an 'L' shaped cross section including the vertical portion 320 and the horizontal portion 322 in the same form as the first embodiment described above.

Referring to FIG. 16, the third insulating layer pattern 318a is isotropically etched to expose the second insulating layer pattern 316a. The third insulating layer pattern 318a may be isotropically etched using a phosphoric acid solution. While the third insulating layer pattern 318a is etched, the edges of the second insulating layer pattern 316a are also etched so that the horizontal edges of the first insulating layer pattern 314a are horizontal portions of the second insulating layer pattern 316a. It protrudes from the edge (317 in FIG. 16). Subsequently, a selective epitaxial growth (SEG) process is applied to the semiconductor substrate, and the upper surfaces of the first and second gate electrodes 306a and 306b and the first and second active regions 10, 20. A silicon epitaxial layer 324 is grown on. As shown, the silicon epitaxial layer 324 on the first and second active regions 10 and 20 covers the edges of the horizontal portions of the first insulating layer pattern 314a to form facets of the silicon epitaxial layer. facet) is positioned on the first insulating layer pattern 314a. Similar to the first embodiment, the surfaces of the exposed first and second active regions 10 and 20 and the first and second gate patterns 306a and 306b before forming the silicon epitaxial layer 324. It is preferable to remove the natural oxide film formed in the. For example, hydrogen may be flowed onto the surface of the semiconductor substrate 300, and the heat treatment process may be performed at 900 ° C. for about 1 minute, and then the SEG process may be immediately performed.

Vertical sidewalls of the second insulating layer pattern 316a in the first and second active regions 10 and 20 using the first gate electrode 306a and the second gate electrode 306b as ion implantation masks. To form a highly concentrated diffusion layer 326. As a result, a source having an LED structure including a low concentration diffusion layer 312 and a high concentration diffusion layer 326 in the first and second active regions 10 and 20 of both the first and second gate electrodes 306a and 306b. / Drain 327 is formed. The high concentration diffusion layer 326 may be formed prior to forming the silicon epitaxial layer 324. In this case, the depth of the high concentration diffusion layer 326 under the first and second insulating layer patterns 314a and 316a may be formed to be shallower than the depth of the high concentration diffusion layer under the silicon epitaxial layer 324.

Referring to FIG. 17, a first barrier insulating film 332 and a second barrier insulating film 334 are sequentially formed on the entire surface of the semiconductor substrate. The first barrier insulating film 332 may be formed of a silicon oxide film having a thickness of about 100 GPa, and the second barrier insulating film 334 may be formed of a silicon nitride film having a thickness of about 100 GPa.

Referring to FIG. 18, the first and second barrier insulating layers 332 and 334 are sequentially patterned to form 'L'-shaped first and second insulating layer patterns 314a and 316a of sidewalls of the second gate electrode 306b. The first barrier insulating film pattern 332a and the second barrier insulating film pattern 334a that conformally cover the same are formed. The first and second barrier insulating layer patterns 332a and 334a extend laterally to cover a predetermined region of the silicon epitaxial layer 324.

Referring to FIG. 19, a metal film 328 is conformally formed on the entire surface of the semiconductor substrate. The metal film 328 may be formed of the same metal as in the first embodiment. In addition, the native oxide film grown on the surface of the silicon epitaxial layer 324 is removed before the metal film 328 is formed. As a result, the upper sidewall of the first gate electrode 306a is exposed. do.

Referring to FIG. 20, the silicon epitaxial layer 324 is silicided as in the first embodiment described above. As a result, a first gate silicide layer 324c and a second gate silicide layer 324d are formed on the first and second gate electrodes 306a and 306b, respectively, and on the first active region 10. First source / drain silicide layers 324a and 324b adjacent to edges of the first and second insulating layer patterns 314a and 316a are formed, and a second source / drain silicide is formed on the second active region 20. Layer 324b is formed. The first and second barrier insulating layer patterns 332a and 334a may prevent metal elements from being diffused into the silicon epitaxial layer 324 during the silicidation process. Accordingly, sidewalls of the second source / drain silicide layer 324b are aligned with edges of the first and second barrier insulating layer patterns 332a and 334a. In addition, the second gate silicide layer 324d is formed to be aligned with sidewalls of the first and second barrier insulating layer patterns 332a and 334a. As a result, the first source / drain silicide layer 324a on the first active region 10 and the second source / drain silicide layer 324b on the second active region 20 may be formed on the semiconductor substrate 300. The flat contact can significantly reduce the concentration of the electric field.

21 is a perspective view illustrating a semiconductor device according to a third exemplary embodiment of the present invention.

Referring to FIG. 21, an isolation layer 402 is disposed in a predetermined region of a semiconductor substrate 400. The device isolation layer 402 defines a first active region 30 and a second active region 40. A transistor of an electrostatic discharge protection curcuit (ESD) may be formed in the second active region 40. The first gate electrode 406a and the second gate electrode 406b cross the upper portions of the first active region 30 and the second active region 40, respectively. A gate oxide film 404 is interposed between the first gate electrode 406a and the first active region 30 and between the second gate electrode 406b and the second active region 40. 'L' shaped first and second insulating layer patterns 414 and 416 are sequentially formed on sidewalls of the first gate electrode 406a, and sidewall insulating layer patterns are formed on sidewalls of the second gate electrode 406b. The sidewall insulating layer pattern may include a 'L' shaped first and second insulating layer patterns 414 and 416, and a third insulating layer pattern 418 having curved sidwalls. The sidewall insulating layer pattern is covered with a first barrier insulating layer pattern 432a and a second barrier insulating layer pattern 434a that are sequentially stacked. The first and second barrier insulating layer patterns 432a and 434a are extended to cover a predetermined region of the second active region 40 adjacent to the sidewall insulating layer pattern. The first and second barrier insulating layer patterns 432a and 434a are conformally formed. The 'L' shaped first and second insulating layer patterns 414 and 416 sequentially stacked have a vertical portion 420 and a horizontal portion 422. The horizontal edge of the 'L' shaped first insulating film pattern 414 protrudes from the horizontal edge of the 'L' shaped second insulating film pattern 416, and the edge of the first barrier insulating film pattern 414a is formed. The second barrier insulating layer pattern 434a protrudes from an edge.

A first gate silicide layer 424c is formed on the first gate electrode 406a, and horizontal edges of the first and second insulating layer patterns 414 and 416 are formed on the first active region 30. A first source / drain silicide layer 424a adjacent to is formed. A second source / drain silicide layer 424b is formed on the second active region 40 adjacent to edges of the first and second barrier insulating layer patterns 432a and 434a. A second gate silicide layer 424d is formed on the second gate electrode 406b. The second gate silicide layer 424d is disposed between the first and second barrier insulating layer patterns 432a and 434a on both sides of the second gate electrode 406b.

An impurity diffusion layer 427 is formed in the first active region 30 and aligned with sidewalls of the first gate electrode 406a, and a sidewall of the second gate electrode 406b is formed in the second active region 40. An impurity diffusion layer 427 is formed to be aligned. The impurity diffusion layer 427 corresponds to a source / drain of the transistor. The impurity diffusion layer 427 is aligned with the low concentration diffusion layer 412 aligned with the sidewall of the first gate electrode 406a or the second gate electrode 406b and the horizontal edge of the first insulating layer pattern 414. High concentration diffusion layer 426 is formed.

In the present invention, the first and second gate silicide layers 424c and 424d are in contact with the first and second gate electrodes 406a and 406b, respectively, and the first and second source / drain silicide layers 424a. , 424b contacts the semiconductor substrates of the first and second active regions 30 and 40, respectively. The first and second source / drain silicide layers 424a and 424b are silicides of a selective epitaxially grown silicon layer. A facet of the silicon epitaxial layer grown on the first active region 30 is disposed on the 'L' shaped first insulating layer pattern 414 and grown on the second active region 40. Since the facet of the silicon epitaxial layer is disposed on the first barrier insulating layer pattern 432a, the first source / drain silicide layer 424a may be in flat contact with the semiconductor substrate. In addition, since the second source / drain silicide layer 424b is formed in alignment with the edges of the first and second barrier insulating layer patterns 432a and 434a, the second source / drain silicide layer 424b is in flat contact with the semiconductor substrate of the second active region 40. can do.

22 to 25 are process cross-sectional views illustrating a third embodiment of the present invention.

Referring to FIG. 22, the device isolation layer 402 is formed on the semiconductor substrate 400 in a similar manner to the second embodiment described with reference to FIGS. 13 to 15 to form the first and second active regions 30,. 40 and first and second gate electrodes 406a and 406b crossing the upper portions of the first and second active regions 30 and 40, respectively, and the first and second active regions 30, A lightly doped diffused layer 412 is formed in each of the sidewalls of the second and second gate electrodes 406a and 406b, respectively. In addition, 'L' shaped first through third insulating layer patterns 414, 416, and 418 are sequentially formed on sidewalls of the first and second gate electrodes 406a and 406b. Subsequently, high concentration diffusion layers 426 aligned with edges of the first insulating layer patterns 432 are formed in the first and second active regions 30 and 40. The low concentration diffusion layer 412 and the high concentration diffusion layer 426 adjacent to each active region correspond to the source / drain 427 of the transistor. A first barrier insulating film 432, a second barrier insulating film 434, and a sacrificial insulating film 436 are conformally formed on the entire surface of the semiconductor substrate on which the high concentration diffusion layer 426 is formed. The first barrier insulating layer 432 is a silicon oxide layer, the second barrier insulating layer 434 is a high temperature nitride (HTN) layer, and the sacrificial insulating layer 436 is a low temperature silicon nitride layer (LTN). It is preferable to form into).

Referring to FIG. 23, the sacrificial insulating layer 436, the second barrier insulating layer 434, and the first barrier insulating layer 431 are sequentially patterned to form the first to third insulating layers on the second active region 40. A first barrier insulation layer pattern 432a, a second barrier insulation layer pattern 434a, and a sacrificial insulation layer pattern 436a are sequentially formed on the patterns 414, 416, and 418. In this case, the first to third insulating layer patterns 414, 416, and 418 sequentially stacked on the second active region 40 are exposed. The first and second barrier insulating layer patterns 432a and 434a and the sacrificial insulating layer pattern 436a extend laterally to cover a predetermined region of the second active region 40.

Referring to FIG. 24, the third insulating layer pattern 418 and the sacrificial insulating layer pattern 436a exposed on the first active region 30 are isotropically etched. The third insulating layer pattern 418 and the sacrificial insulating layer pattern 436a may be isotropically etched using a phosphoric acid solution. While the third insulating layer pattern 418 and the sacrificial insulating layer pattern 436a are etched, the edges of the 'L'-shaped second insulating layer pattern 416 and the edges of the second barrier insulating layer pattern 434a are etched together. The edge of the 'L' shaped first insulating film pattern 414 protrudes from the edge of the second insulating film pattern 416, and the edge of the first barrier insulating film pattern 432a is the second barrier insulating film pattern 434a. Protrude from the edge of). Subsequently, a selective epitaxial growth (SEG) process is applied to the semiconductor substrate to form upper surfaces of the first and second gate electrodes 406a and 406b and the first and second active regions 30, respectively. A silicon epitaxial layer 424 is grown on 40. As shown, the silicon epitaxial layer 424 on the first active region 30 covers the edge of the horizontal portion 422 of the first insulating layer pattern 414 and is disposed on the second active region 40. The silicon epitaxial layer 424 covers the lateral edge of the first barrier insulating layer pattern 432a. Accordingly, a facet of the silicon epitaxial layer is disposed on the 'L' shaped first insulating layer pattern 414 or on the first barrier insulating layer pattern 432a.

Referring to FIG. 25, the silicon epitaxial layers () may be silicided by applying a silicide process in the same manner as in the above-described first and second embodiments. As a result, first and second gate silicide layers 424c and 424d are formed on the first and second gate electrodes 406a and 406b, respectively, and on the first and second active regions 30 and 40. The first source / drain silicide layer 424a and the second source / drain silicide layer 424b are formed in each. As a result, the first source / drain silicide layer 424a on the first active region 30 and the second source / drain silicide layer 424b on the second active region 40 are in flat contact with the semiconductor substrate. This can significantly reduce the concentration of the electric field. In addition, the second source / drain silicide layer 424b is formed to be spaced apart from the second gate electrode 406b by a predetermined interval. Therefore, by dissipating heat in the transistor when electrostatic discharge occurs, it is possible to prevent the transistor from being partially destroyed.

As described above, according to the present invention, the source / drain silicide layer may be formed to be in flat contact with the semiconductor substrate by using an 'L' type insulating film pattern. As a result, the concentration of the electric field in the source / drain region can be prevented and the leakage current flowing from the source / drain to the semiconductor substrate can be significantly reduced.

It is also possible to form a silicide layer having an upper area larger than the area in contact with the source / drain along the direction across the gate electrode. Therefore, an increase in resistance due to misalignment of the contact plugs connected to the source / drain can be prevented.

In addition, since the thickness of the silicide layer formed on the gate electrode may be increased, the signal delay of the gate electrode may be reduced.

Furthermore, it is possible to manufacture a semiconductor device having excellent resistance to external electric shock by preventing local thermal damage from occurring at the junction of the transistor of the ESD protection circuit.

1 to 4 are process cross-sectional views for explaining the problems of the prior art.

5 is a schematic perspective view illustrating a structure of a semiconductor device according to a preferred embodiment of the present invention.

6 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

※ Explanation of code about main part of drawing ※

200: semiconductor substrate 202: device isolation film

204: gate oxide film 206: gate electrode

208: gate capping insulating film 210: gate pattern

212: low concentration diffusion layer 214: first insulating film

216: second insulating film 218: third insulating film

214a: first insulating film pattern 216a: second insulating film pattern

218a: third insulating film pattern 217: protrusion

220: vertical portion 224: epitaxial layer

222: horizontal portion 224 a: gate silicide layer

224b: source / drain silicide layer 226: high concentration diffusion layer

227: source / drain regions 228: metal film

230: etch stop film

Claims (83)

delete delete delete delete delete An active region defined in a predetermined region of the semiconductor substrate; A gate electrode across the active region; A 'L' shaped first insulating layer pattern having a vertical portion and a horizontal portion, wherein the vertical portion is formed on sidewalls of the gate electrode, and the horizontal portion extends from the vertical portion and is formed on the active region; A second 'L' shaped second insulating layer pattern formed on the first insulating layer pattern according to the shape of the first insulating layer pattern; A source / drain silicide layer formed on the active region adjacent to horizontal edges of the 'L'-shaped first and second insulating layer patterns and flatly contacting the semiconductor substrate; A low concentration diffusion layer formed in an active region under the vertical portion of the first and second insulating layer patterns; And A high concentration diffusion layer formed in an active region below the horizontal portion of the first and second insulating layer patterns and under the source / drain silicide layer; The horizontal edge of the first insulating film pattern protrudes from the horizontal edge of the second insulating film pattern and is covered with the source / drain silicide layer, and the high concentration diffusion layer is lower than the horizontal portions of the first and second insulating film patterns. And formed deeper under the source / drain silicide layer, wherein the source / drain silicide layer is a silicided epitaxial layer. The method of claim 6, The first insulating film pattern is a semiconductor device, characterized in that the silicon oxide film. The method of claim 6, And the second insulating film pattern is a silicon nitride film. delete The method of claim 6, And a gate silicide layer covering an upper portion of the gate electrode. The method of claim 10, And the gate silicide layer is a silicided silicon epitaxial layer. delete delete An active region defined in a predetermined region of the semiconductor substrate; A gate electrode across the active region; An 'L' shaped first insulating layer pattern having a vertical portion covering the sidewall of the gate electrode and a horizontal portion extending from a lower portion of the vertical portion in a direction crossing the gate electrode to cover the active region; An 'L' shaped second insulating layer pattern covering an outer wall of the vertical portion and an upper surface of the horizontal portion of the first insulating layer pattern according to the shape of the first insulating layer pattern; A silicon epitaxial layer formed on the active region adjacent to the horizontal edges of the 'L'-shaped first and second insulating layer patterns and flatly contacting the semiconductor substrate; and A barrier insulating film pattern conformally covering the predetermined regions of the epitaxial layer around the first and second insulating film patterns and the first insulating film layer, which are sequentially stacked, The horizontal edge of the first insulating layer pattern may protrude from the horizontal edge of the second insulating layer pattern to be covered with the silicon epitaxial layer, and the silicon epitaxial layer exposed around the barrier insulating layer pattern may be silicided. A semiconductor device. The method of claim 14, The first insulating film pattern is a semiconductor device, characterized in that the silicon oxide film. The method of claim 14, And the second insulating film pattern is a silicon nitride film. The method of claim 14, The barrier insulating film pattern, Including the first barrier insulating film pattern and the second barrier insulating film pattern which are sequentially stacked, And the first barrier insulating film pattern is a silicon oxide film, and the second barrier insulating film pattern is a silicon nitride film. The method of claim 14, And a silicided silicon epitaxial layer formed on said gate electrode. The method of claim 14, Further comprising a silicon epitaxial layer formed on the gate electrode, And the barrier insulating layer pattern extends to cover a predetermined region of the silicon epitaxial layer on the gate electrode, and the silicon epitaxial layer between the barrier insulating layers on both sides of the gate electrode is silicided. The method of claim 14, And a dopant diffusion layer formed in active regions on both sides of the gate electrode. The method of claim 20, The impurity diffusion layer, A low concentration diffusion layer formed in an active region under the vertical portion of the first and second insulating layer patterns; And And a high concentration diffusion layer formed in an active region below the horizontal portion of the first and second insulating layer patterns and below the silicon epitaxial layer on both sides of the gate electrode. And wherein the high concentration diffusion layer is deeper under the silicon epitaxial layer than under the horizontal portions of the first and second insulating layer patterns. An active region defined in a predetermined region of the semiconductor substrate; A gate electrode across the active region; A sidewall insulating layer pattern formed on sidewalls of the gate electrode; A first barrier insulation layer pattern and a second barrier insulation layer pattern that are sequentially stacked to cover the sidewall insulation pattern and extend to an upper portion of the active region around the sidewall insulation pattern; and A source / drain silicide layer formed on an active region exposed around the first and second barrier insulating patterns; An edge of the first barrier insulating film pattern adjacent to the source / drain silicide or the like protrudes from an edge of the second barrier insulating film pattern and is covered with the source / drain silicide layer, and the source / drain silicide layer is a surface of the semiconductor substrate. Semiconductor device, wherein the semiconductor device is in flat contact with the semiconductor device. The method of claim 22, And the first barrier insulating film pattern is a silicon oxide film. The method of claim 22, And the second barrier insulating film pattern is a silicon nitride film. The method of claim 22, And the source / drain silicide layer is a silicided silicon epitaxial layer. The method of claim 22, And a gate silicide layer covering an upper portion of the gate electrode. The method of claim 26, And the gate silicide layer is a silicided silicon epitaxial layer. The method of claim 22, A gate silicide layer formed on the gate electrode, wherein the first and second barrier insulating layer patterns extend to cover a predetermined region of the gate electrode, and the gate silicide layer includes the barrier insulating layer patterns on both sides of the gate electrode. A semiconductor device, characterized in that formed in the gap region between. The method of claim 22, And a dopant diffusion layer formed in active regions on both sides of the gate electrode. The method of claim 29, The impurity diffusion layer, A low concentration diffusion layer formed in an active region under the sidewall insulating layer pattern; And And a high concentration diffusion layer formed in said active region near said sidewall insulating film pattern. The method of claim 22, The sidewall insulating film pattern, A 'L'-shaped first insulating layer pattern, a' L'-shaped second insulating layer pattern, and a third insulating layer pattern covering the sidewalls of the first gate electrode may be included, wherein the third insulating layer pattern has a curved sidewall. A semiconductor device, characterized in that. The method of claim 31, wherein The 'L' shaped first insulating film pattern is a semiconductor device, characterized in that the silicon oxide film. The method of claim 31, wherein The 'L'-shaped second insulating film pattern and the third insulating film pattern is a semiconductor device, characterized in that the silicon nitride film. delete delete delete delete delete delete delete Defining an active region in a predetermined region of the semiconductor substrate; Forming a gate electrode across the active region; Forming a low concentration diffusion layer in an active region on both sides of the gate electrode; The 'L' shaped first and second insulating film patterns are sequentially stacked on sidewalls of the gate electrode and have vertical and horizontal portions, respectively, and the horizontal edges of the 'L' shaped first insulating film pattern are the 'L'. Forming protruding from the horizontal edge of the male second insulating layer pattern; Impurities are injected into the semiconductor substrates on both sides of the gate electrode to form a high concentration diffusion layer in the active region below the horizontal portion of the first and second insulating film patterns and outside the first insulating film pattern. Forming a depth deeper than a depth under the first insulating layer pattern; A silicon epitaxial layer is selectively grown on the active region and the gate electrode exposed next to the first and second insulating layer patterns, wherein the silicon epitaxial layer is a horizontal portion of the protruding 'L' shaped first insulating layer pattern. Growing to cover the edges; Silicifying the silicon epitaxial layer to form a source / drain silicide layer on the active region and simultaneously forming a gate silicide layer on the gate electrode, wherein the source / drain silicide layer is formed in the active region. The semiconductor device manufacturing method characterized in that it is formed to be in flat contact with the surface of the semiconductor substrate. delete 42. The method of claim 41 wherein Forming the 'L' shaped first and second insulating film patterns, Sequentially forming a first insulating film, a second insulating film, and a third insulating film on the entire surface of the semiconductor substrate on which the gate electrode is formed; Anisotropically etching the third insulating film, the second insulating film, and the first insulating film, the L-shaped first insulating film pattern, the 'L' shaped second insulating film pattern, and the third insulating film pattern sequentially covering the sidewalls of the gate electrode. Forming; and Isotropically etching the third insulating film pattern to expose the second insulating film pattern and simultaneously etching edges of the horizontal portion of the second insulating film pattern. 44. The method of claim 43, And the first insulating film is formed of a silicon oxide film. The method of claim 44, The second insulating film may be formed of a high temperature nitride (HTN) film, and the third insulating film may be formed of a low temperature nitride (LTN) film deposited at a lower temperature than the second insulating film. A method for manufacturing a semiconductor device. The method of claim 44, And the second insulating film is formed of a silicon nitride film, and the third insulating film is formed of a silicon oxynitride film. 42. The method of claim 41 wherein Before silicidating the silicon epitaxial layer, Exposing an upper sidewall of the gate electrode, wherein the upper sidewall of the exposed gate electrode is also silicided in forming the silicide layer. 42. The method of claim 41 wherein Forming a first barrier insulating film and a second barrier insulating film in order on the entire surface of the semiconductor substrate on which the silicon epitaxial layer is formed, and forming the first and second barrier insulating films conformally; The second barrier insulating film and the first barrier insulating film are sequentially patterned to form a first barrier insulating film pattern and a second barrier insulating film pattern, which are sequentially stacked, wherein the first and second barrier insulating film patterns are the 'L' shaped first And covering the second insulating layer pattern to expose a predetermined region of the silicon epitaxial layer on both sides of the gate electrode and a predetermined region of the silicon epitaxial layer on the gate electrode. And in the silicifying the silicon epitaxial layer, the first and second barrier insulating film patterns prevent silicide of the silicon epitaxial layer underneath. delete delete 42. The method of claim 41 wherein Before forming the silicon epitaxial layer, Removing the exposed gate electrode and the native oxide film on the exposed surface of the active region. 42. The method of claim 41 wherein Forming the gate silicide layer and the source / drain silicide layer, Forming a metal film on an entire surface of the semiconductor substrate on which the silicon epitaxial layer is formed; Performing a first heat treatment process on the semiconductor substrate on which the metal film is formed to diffuse metal elements into the epitaxial layer; Removing the metal film remaining without diffusion in the epitaxial layer; Performing a second heat treatment process on the semiconductor substrate to silicide the epitaxial layer. 42. The method of claim 41 wherein And removing the metal film using isotropic etching. Defining an active region in a predetermined region of the semiconductor substrate; Forming a gate electrode across the active region; Forming a sidewall insulating layer pattern on sidewalls of the gate electrode; A first barrier insulating layer pattern and a second barrier insulating layer pattern are formed to be sequentially stacked to cover the sidewall insulating layer pattern and the predetermined region of the active region, and the edge of the first barrier insulating layer pattern on the active region is the second layer. Forming protruding from an edge of the barrier insulating film pattern; Growing an epitaxial layer on the gate electrode and the active region exposed to both sides of the barrier insulating layer patterns, wherein the epitaxial layer is grown to cover an edge of the protruding first insulating layer pattern; and Silicifying the epitaxial layer to form a source / drain silicide layer in flat contact with the semiconductor substrate of the active region and a gate silicide layer in flat contact with the gate electrode, wherein the source / drain silicide layer comprises And a first barrier layer and a second barrier insulating layer pattern spaced apart from the sidewall insulating layer pattern. 55. The method of claim 54, Forming the first barrier insulating film pattern and the second barrier insulating film pattern, Conformally forming a first barrier insulating film, a second barrier insulating film, and a sacrificial insulating film on an entire surface of the semiconductor substrate on which the sidewall insulating film pattern is formed; The sacrificial insulating layer, the second barrier insulating layer, and the first barrier insulating layer are sequentially patterned to form a first barrier insulating layer pattern, a second barrier insulating layer pattern, and a sacrificial insulating layer pattern, which are sequentially stacked. Forming a second barrier insulation layer pattern and a sacrificial insulation layer pattern to cover the sidewall insulation layer pattern and a predetermined region of the active region; and Isotropically etching the sacrificial insulating pattern and simultaneously etching the edges of the second barrier insulating pattern to expose the edges of the first barrier insulating pattern. The method of claim 55, And the first barrier insulating film is formed of a silicon oxide film, and the second barrier insulating film and the sacrificial insulating film are formed of a silicon nitride film. The method of claim 55, The second barrier insulating film is formed of high temperature silicon nitride (HTN), And the sacrificial insulating film is formed of a low temperature silicon nitride film (LTN) deposited at a lower temperature than the second barrier insulating film. The method of claim 57, And the second barrier insulating film is deposited at a lower pressure than the sacrificial insulating film. The method of claim 55, And the second barrier insulating film is formed of silicon nitride and the sacrificial insulating film is formed of silicon oxynitride. 55. The method of claim 54, In the step of forming the silicon epitaxial layer, And forming a silicon epitaxial layer in a predetermined region on the gate electrode. 55. The method of claim 54, And forming an impurity diffusion layer in active regions on both sides of the gate electrode. 62. The method of claim 61, The impurity diffusion layer, A low concentration diffusion layer formed in an active region under the sidewall spacers; and And a high concentration diffusion layer formed in the active region under the first barrier insulating layer pattern and the source / drain silicide layer adjacent to the low concentration diffusion layer. Defining a first active region and a second active region in the semiconductor substrate; Forming a first gate electrode across the first active region and a second gate electrode across the second active region; Form 'L' shaped first and second insulating film patterns sequentially stacked on sidewalls of the first and second gate electrodes, respectively, wherein the 'L' shaped first and second insulating film patterns have vertical and horizontal portions, respectively. And forming a horizontal edge of the 'L' shaped first insulating layer pattern in contact with the first and second active regions so as to protrude from the horizontal edge of the 'L' shaped second insulating film pattern; A silicon epitaxial layer is grown on the first and second gate electrodes and the first and second active regions exposed by the 'L'-shaped first insulating layer pattern, wherein the silicon epitaxial layer is formed by the protruding' Growing to cover the horizontal edge of the L′-shaped first insulating layer pattern; 'L' shaped first and second insulating layer patterns sequentially stacked on the second active region, and a first barrier insulating layer pattern conformally covering a predetermined region of the silicon epitaxial layer on the second active region. And forming a second barrier insulating film pattern; and The silicon epitaxial layer is silicided using the stacked first and second barrier insulating layer patterns as masks, so that the first active region, a part of the second active region, the first gate electrode, and the second gate electrode Forming a first source / drain silicide layer, a second source / drain silicide layer, a first gate silicide layer, and a second gate silicide layer, respectively, wherein the first source / drain silicide layer comprises: the first insulating layer And a second source / drain silicide layer spaced apart from the first and second insulating film patterns by the first and second barrier insulating film patterns. Manufacturing method. The method of claim 63, wherein After forming the first and second gate electrodes, And forming a low concentration diffusion layer in active regions on both sides of the first and second gate electrodes. The method of claim 63, wherein Forming the 'L' shaped first and second insulating film patterns, Sequentially forming a first insulating film, a second insulating film, and a third insulating film on an entire surface of the semiconductor substrate on which the first and second gate electrodes are formed; A third having an 'L' shaped first insulating film pattern, an 'L' shaped second insulating film pattern, and a curved surface, which sequentially anisotropically etch the third insulating film, the second insulating film, and the first insulating film to cover sidewalls of the gate electrode Forming an insulating film pattern; Isotropically etching the third insulating film pattern to expose the second insulating film pattern, and simultaneously etching a portion of the horizontal edge of the second insulating film pattern. 66. The method of claim 65, And the first insulating film is formed of a silicon oxide film. 66. The method of claim 65, The second insulating film may be formed of a high temperature nitride (HTN) film, and the third insulating film may be formed of a low temperature nitride (LTN) film deposited at a lower temperature than the second insulating film. A method for manufacturing a semiconductor device. 66. The method of claim 65, And the second insulating film is formed of a silicon nitride film, and the third insulating film is formed of a silicon oxynitride film. 65. The method of claim 64, Before silicidating the silicon epitaxial layer, The method may further include exposing an upper sidewall of the first gate electrode, wherein in forming the silicide layer, the upper part of the exposed first gate electrode is also silicided. Way. 65. The method of claim 64, And the first barrier insulating film pattern is formed of a silicon oxide film, and the second barrier insulating film pattern is formed of a silicon nitride film. The method of claim 63, wherein Before forming the silicon epitaxial layer, And injecting impurities into the semiconductor substrates on both sides of the first and second gate electrodes to form a high concentration diffusion layer. The method of claim 63, wherein After forming the silicon epitaxial layer, And implanting impurities into the semiconductor substrates on both sides of the first and second gate electrodes to form a high concentration diffusion layer in the semiconductor substrate under the first insulating film pattern and under the epitaxial layer. Manufacturing method. Defining first and second active regions in a predetermined region of the semiconductor substrate; Forming first and second gate electrodes across the first and second active regions, respectively; A sidewall insulating layer pattern is formed to cover each sidewall of the first and second gate electrodes, and the sidewall insulating layer pattern is a 'L' shaped first insulating layer pattern that sequentially covers each sidewall of the first and second gate electrodes. Forming a third insulating film pattern having a 'shaped second insulating film pattern and a curved surface'; Forming first, second, and third barrier insulating film patterns sequentially stacked so as to conformally cover the sidewall insulating film patterns on both sides of the second gate electrode and the predetermined area of the second active area; Isotropically etching the third insulating film pattern on both sides of the first gate electrode, the third barrier insulating film pattern on both sides of the second gate electrode, and at the same time, a portion of the second insulating film pattern edge and the second barrier insulating film pattern edge Etching a portion of the; Selective epitaxial growth processes are applied to the semiconductor substrate to form silicon epitaxy on the top surfaces of the first and second gate electrodes and the first and second active regions exposed on both sides of the first and second gate electrodes. Forming an ice layer; and Silicifying the epitaxial layer to form a first source / drain silicide layer, a second source / drain silicide layer, respectively, on the first active region, the second active region, the first gate electrode, and the second gate electrode; Forming a first gate silicide layer and a second gate silicide layer, wherein the first source / drain silicide layer is formed to cover the horizontal edge of the L-shaped first insulating layer pattern, and the second source / drain silicide layer is formed. The drain silicide layer is formed by being spaced apart from the sidewall insulating film pattern by the first and second barrier insulating films. The method of claim 73, Forming the first barrier insulating film pattern and the second barrier insulating film pattern, Conformally forming a first barrier insulating film, a second barrier insulating film, and a sacrificial insulating film on the entire surface of the semiconductor substrate on which the sidewall spacers are formed; The sacrificial insulating layer, the second barrier insulating layer, and the first barrier insulating layer are sequentially patterned to form a first barrier insulating layer pattern, a second barrier insulating layer pattern, and a sacrificial insulating layer pattern, which are sequentially stacked. Forming a second barrier insulation layer pattern and a sacrificial insulation layer pattern to cover the sidewall insulation layer pattern and a predetermined region of the active region; and Isotropically etching the sacrificial insulating pattern and simultaneously etching the edges of the second barrier insulating pattern to expose the edges of the first barrier insulating pattern. The method of claim 74, wherein And the first barrier insulating film is formed of a silicon oxide film, and the second barrier insulating film and the sacrificial insulating film are formed of a silicon nitride film. The method of claim 74, wherein The second barrier insulating film is formed of high temperature silicon nitride (HTN), And the sacrificial insulating film is formed of a low temperature silicon nitride film (LTN) deposited at a lower temperature than the second barrier insulating film. 76. The method of claim 75, And the second barrier insulating film is deposited at a lower pressure than the sacrificial insulating film. The method of claim 74, wherein And the second barrier insulating film is formed of silicon nitride and the sacrificial insulating film is formed of silicon oxynitride. The method of claim 73, And forming an impurity diffusion layer in active regions on both sides of the gate electrode. 80. The method of claim 79 wherein The impurity diffusion layer, A low concentration diffusion layer formed in an active region under the sidewall spacers; and And a high concentration diffusion layer formed in the active region under the first barrier insulating layer pattern and the source / drain silicide layer adjacent to the low concentration diffusion layer. The method of claim 73, And the first insulating film pattern is formed of a silicon oxide film. The method of claim 73, The second insulating layer pattern is formed of high temperature nitride (HTN), and the third insulating layer pattern is formed of low temperature nitride (LTN) deposited at a lower temperature than the second insulating layer. The manufacturing method of a semiconductor device characterized by the above-mentioned. The method of claim 73, And the second insulating film pattern is formed of a silicon nitride film, and the third insulating film pattern is formed of a silicon oxynitride film.