KR100698074B1 - Method for manufacturing of model using the optical proximity correction - Google Patents

Abstract

A method for manufacturing a proximity effect correcting model is provided to restrain the degradation of yield by preventing the bridge between adjacent patterns. CD(Critical Dimension) data are measured from an exact sample pattern(S100). A predetermined model is manufactured by modulating optical parameters and resist parameters using the measured CD data(S200). The degree of precision is checked by overlapping a print image of the predetermined model with an SEM(Scanning Electron Microscope) image of the sample pattern(S300). The optical parameters include a defocus, an NA, an aperture type and a sigma.

Description

Method for manufacturing of model using the optical proximity correction

1 is a view illustrating a bridge phenomenon generated due to lack of margin during process progress

2 shows 160 nm photo process margin results using a reticle

FIG. 3 is a graph showing a result of simulation to determine a space size rule of the SRAM line end of FIG. 1.

4A and 4B are diagrams illustrating the results of observing a CD change using an image threshold value with a calibration device that is an OPC model simulation tool.

5 and 6 show the results of the SRAM BIST test on the SA5028 route.

7 is a flowchart showing a method of manufacturing a model for OPC according to the present invention.

8 and 9 are graphs showing simulation results of small (ISO) line accuracy and pitch accuracy.

10 is a view showing the results of comparison of the conventional 180nm model with the results of the 160nm OPC DI model made by overlapping the SEM image and the print image of the model

11 illustrates three sigma values of target CD and PI CD for each step size;

12 is a test of OPC CD change according to the number of iterations

FIG. 13 is a diagram showing values measured in a DI state by exposing with a mask subjected to OPC with a 180 nm OPC model. FIG.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a model for proximity effect correction (OPC).

In general, as devices and design rules integrated in semiconductor chips become smaller, current lithography techniques make it difficult to implement desired circuit shapes on a wafer.

The pattern distortion phenomenon occurs at the resolution limit, and this problem is overcome by process equipment in the semiconductor manufacturing technology of 200 nm or more, but the limit of the part that can be improved by the equipment is achieved in the technology of 180 nm or less.

In the early 1970s, an Optical Proximity Correction (OPC) technology was developed that approached from a design perspective and corrected optical proximity effects (OPE) as part of Resolution Enhancement Technology (RET).

The OPC is a task of correcting a pattern so that an image that matches a target is implemented using an OPC simulation model.

On the other hand, OPC is becoming more and more useful as the design rule of the device becomes smaller.

As the relative size of the pattern becomes smaller compared to the wavelength of the light source of the exposure equipment, the pattern distortion phenomenon is expected to become more serious as the design rule becomes smaller, and performance and yield without OPC are improved. It is hard to expect.

OPC predicts OPE due to reticle pattern fidelity and diffraction of light, biases in resist and etching processes, and reflects them in the reticle in advance.

On the other hand, as a method of performing OPC, a rule-based OPC and a lithography system, which reflect various patterns of rules obtained through experiments and experiences in a mask design, are converted into mathematical models to change the shape and size of the entire pattern. It is largely divided into compensating model-based OPC.

First, since the rule-based OPC does not perform iterative calculations, it is difficult to expect an optimal design while processing a large design in a short time.

In addition, the model-based OPC can reduce the error between the simulation value and the actual measurement value of the shape and size of the pattern to be implemented on the wafer if the accuracy of the model is made.

However, the process must be stabilized in order to make a model, and when the process is changed, it is necessary to check the OPC model and generate a new model.

In addition, logic devices have more non-repetitive patterns than repeating patterns, making it difficult to fit all patterns into one model.

Therefore, the hybrid OPC (hybrid OPC) that applies rule-based OPC and model-based OPC together is currently used.

The development of new devices often uses the same process as an extension of previous technology.

In particular, OPC models have the same application of the existing models primarily due to limitations such as temporal limitations and test mask preparation, which can include fatal errors in technologies below 180nm.

For example, in the case of the 160 nm gate layer, the 180 nm gate design is 90% shrinked, and the OPC model made at 180 nm is used as it is, and thus, the pattern bridge is used. bridge phenomenon has resulted in a fatal yield of 0%.

An object of the present invention is to provide a method for manufacturing a model for proximity effect correction (OPC: Optical Proximity Correction) to prevent the reduction of yield by preventing the pattern bridge phenomenon.

In order to achieve the above object, the method for manufacturing a proximity effect correction model according to the present invention includes measuring CD data of an accurate sample pattern, and adjusting the optical parameters and the resist parameters with the measured CD data to obtain a model. And manufacturing accuracy, and detecting accuracy by overlapping the SEM image of the print pattern and the sample pattern of the model.

First, the SH51A multi product wafer (MPW) includes two chips with different design rules, designed to simultaneously implement 180nm devices and 160nm devices with 90% shrinkage of 180nm devices.

The SA5014 route is the MPW mask applied, and Table 1 shows the results of yield analysis of the SA5014 route.

As shown in Table 1, the results show that the yield of the 180nm device is 89.70%, while the shrinking yield is 0%.

That is, in the SA5014 route, no significant difference was found between defects during defect inspection and there was no problem during the process.

On the other hand, 0% yield was caused by memory failure, which prevented the chip from working at all, and caused by gate shortening.

1 is a diagram illustrating a bridge phenomenon generated due to a lack of margin during the process.

In general, the process margin and design rule checking method first verifies whether a layout is drawn according to a design rule using a rule table made based on a design rule.

This verification method simply takes a look at the distance between the minimum and maximum linewidth and the linewidth in the design rule and warns if it is broken.

As such, verifying by a numerical value such as a distance value has a drawback that the process margin cannot be accurately identified.

In addition, in the case of under exposure in the patterning process due to the limitation of the manufacturing process, even if the layout is drawn according to the design rule, the margin is insufficient during the process, and in severe cases, a bridge as shown in FIG. Since a phenomenon occurs, the layout has to be modified to remake the mask.

Here, underexposure is a method of weakening the exposure to make the patterning large, for example, performed on the patterning to be equal to the line width designed by the designer after the final etch due to the photo / etch bias.

2 is a graph showing a 160 nm photo process margin result using a reticle.

As shown in FIG. 2, the cause of the bridge of the gate line and space portion was an error of the OPC.

Incorrect OPC models can include pattern bridges, reduced pattern fidelity, and line shortening. 160nm OPCs that 90% shrink an OPC model made for a 180nm process. The same applies to line and space bridges.

Therefore, if the design rules change, the OPC model must also be changed or verified to prevent yield loss.

The troublesome line end is a two-dimensional pattern that the model is difficult to correct correctly, which causes the problem first if the model's accuracy is not high.

Therefore, in OPC of 2D pattern, minimum space rule and minimum line rule should be applied as well as correction through model.

FIG. 3 is a graph illustrating a result of simulation to determine a space size rule of the SRAM line end of FIG. 1.

As shown in FIG. 3, when the line width is 180 nm, the end gap is split at 10 nm intervals to compare the expected space CD. As a result, the simulation is performed at a space of about 130 nm. You can see that the CD is 180nm.

4A and 4B show a result of observing a CD change using an image threshold value with a calibration device that is an OPC model simulation tool.

Table 2 also shows the line CD change versus the space CD change from the image threshold.

As shown in FIGS. 4A and 4B and Table 2, in the simulation results, the line end space was estimated to be about 130 nm, but the line and space portion was larger than the line for the threshold value, that is, the change in intensity. If the sensitivity is 130nm, it is difficult to secure process margins.

Therefore, a minimum space of 140nm is determined and applied to all patterns.

After applying the minimum space rule as described above and checking the bridge problem in another pattern by the intensity log slope (Optical rule check) to produce a correction reticle (revision reticle).

As a result of the OPC confirmation with the reticle, there was no bridge problem, and the process margin can secure a depth of focus (DOF) of 0.27 μm at an exposition latitude (EL) of 5%.

5 and 6 show the results of the SRAM BIST test on the SA5028 route.

As shown in FIGS. 5 and 6, the SRAM BIST test at the SA5028 route passed an average of 93% die per wafer and yield was about 25%.

This confirms that OPC has a direct relationship to the chip's behavior when compared to the 0% pass results of the SA5014 route, which used the 180nm OPC model, and yields only when OPC is in place.

Therefore, the reason for the low yield is not a problem of OPC but a problem with other processes.

On the other hand, although the problem areas of the SH51B gate reticle were corrected by applying a space rule, fundamentally applying the 180nm OPC model to the 160nm device can cause many problems.

Therefore, an OPC model setup is required for the 160nm process.

That is, FIG. 7 is a flowchart showing a method of manufacturing a model for OPC according to the present invention.

As shown in FIG. 7, in order to make a model, the process must be stabilized and CD data of an accurate sample pattern is measured (S100).

Next, an optical parameter and a resist parameter are tuned with the measured CD data to prepare a model (S200).

Then, the model is checked as a confirmation process of how well the model is predicted and corrected (S300).

Here, the optical parameters include defocus, NA, aperture type, sigma, etc., and after optimizing them, the simulation value and the measured value are once again maximized (Imax) and minimum (Imin). ), To adjust the intensity log slope.

On the other hand, in the 130nm device or less, the bias polynomial is adjusted to the portion of the etching bias.

The OPC model applied to the 180nm device is an after development inspection (ADI) model, which is optimized for optical and resist parameters according to the procedure of FIG.

Table 3 shows the OPC model results.

The OPC model, which will be applied at 160nm, was also loaded with a test pattern on the SH52A MPW reticle to get DI data by gathering CD data under fixed process conditions.

Process progress conditions are shown in Table 4 below, model 1 was made of VTR-E and the results are shown in Table 5.

Process Condition Equip. ASML5500 Lamda 248 NA 0.6 Aperture Annular Sigma 0.75 / 0.45 PR GKR5115N PR Thick. 4100 yen BARC DUV44 BARC Thick. 600Å

The line CD error spec between the measured CD and the simulated CD is ± 10 nm.

As shown in Figs. 8 and 9, both the ISO line and the 160 nm line pitch CD error are within the specification, and the correction value between the measured value and the simulation value is 99.8%, which is a very good model.

Model validation was conducted to ascertain how well this model predicted and corrected it.

The model verification is shown in FIG. 10 comparing the results of the 160 nm OPC DI model and the existing 180 nm model, which are made by overlapping the SEM image of the complex pattern and the print image of the model, rather than a simple line or space.

Two checks were performed to make the yellow print image (PI) on the right better match corner rounding, line CD size, and more.

That is, in the case of Model 1 located at the upper side in FIG. 10, the SEM image and the printed image cannot be used properly, and in the case of Model 2 below, the SEM image and the printed image are well aligned. Can be used as

The 160nm OPC model is expected to have higher accuracy than the existing 180nm OPC model.

So far, the model has been considered, and the factors that can cause errors in the model-based OPC include edge placement moving step size and repetition.

These two factors that need to be considered when applying the optimized model to the GDS to be OPC have a big impact on the OPC results as the design rule gets smaller.

The edge moving step size is a value required when moving the edge by the CD correction value predicted by the model, and is usually based on a database unit.

However, in the case of the 180nm OPC model applied to the 160nm OPC, the step size was 5nm, which was not a big influence at 180nm, but could cause problems at 160nm.

Table 6 and Figure 11 are the data supporting this.

Table 6 shows the results of OPC by splitting the edge movement step size from 1nm to 7nm, which is a database unit, in OPC that fits various target CDs. Shows something different.

Also, the smaller the step size, the better the expected PI CD fits, which is applied equally to the pattern of various targets.

Table 6 shows three sigma values of target CD and PI CD for each step size for four patterns in FIG. 11.

As shown in FIG. 11, it can be seen that as the step size is larger, the three sigma value is increased, which is directly related to the OPC accuracy.

When the 1 nm grid, which is a database unit, is used as the step size, it can be seen that all four patterns show an expectation that matches the target (TG) CD.

If the step size of the edge movement is set too large, it is impossible to move the edge size that can be the value of EPE 0 regardless of the number of repetitions.

After all, even if a high accuracy model is applied, if the step size is increased, the step size is an important factor because the model cannot move as much as the correction value even when an error value is expected at the edge.

On the other hand, the 180nm OPC model uses four OPC iterations, which, like the step size, can cause OPC errors at 160nm.

In applying OPC to various target CDs, repetition refers to the number of times the edge is repeatedly moved to match the condition of the surrounding edge and the state of the other edges touching one edge.

12 is a view of testing OPC CD change according to the number of iterations.

As shown in Figure 12, the number 1 to 4 can be seen that the CD change width is up to 50nm, after 6 it was observed that the CD value is stabilized.

Even if the edge movement step is a 1nm grid, the number of repetitions only once does not reflect the result of the contact pattern, so that it is not accurate OPC.

We created a new model and fixed the factors used when running OPC to complete the OPC run setup.

For comparison of the final accuracy of the results, the difference between the simulated value and the measured pitch linearity of the 180nm OPC model and the 160nm OPC model was confirmed.

As a result, as shown in Fig. 13, the actual blue CD is measured in DI state by exposing with a mask of OPC with 180nm OPC model.

The 180nm OPC model predicts CD target 180nm within ± 5nm at all pitches, as seen on a lime green print image (PI) CD.

However, this shows a lot of difference from the actual blue line, which means that the OPC model does not fit at all.

On the other hand, the newly created 160nm OPC model has been shown to predict the actual CD value well within the margin of error within ± 3nm. This proves that the newly created OPC model is excellent in accuracy. Applying the model to the OPC is expected to yield more than 85% chip yield.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The manufacturing method of the model for proximity effect correction by this invention demonstrated above has the following effects.

In other words, if the design rule is made smaller by shrinking the existing device, when the OPC model is used as an existing one, it can be seen that the OPC accuracy may be lowered, resulting in pattern bridging of the pattern, which may directly affect the yield. there was.

The most important thing in model-based OPC is to create and apply a highly accurate model. If the design changes or the process changes, the existing model will not fit.

When you want to correct the parts of the model where the prediction falls, the first approach is to rebuild the model, and the second is to apply the rules specific to the specific pattern.

Both methods must be determined after investigating the impact of new models and rules on other patterns.

As discussed in the SH51B MPW, the minimum space rule was applied to the 180nm model in consideration of the effect on other patterns, but it was found that the OPC accuracy of applying the 180nm model to the 160nm design ultimately decreased.

Therefore, remodeling is the ideal way.

Even if the accuracy of the OPC model is good, if the unit of the edge moving step size is large or the number of iterations is insufficient during OPC execution, the OPC will not be able to match the simulation results. Failure to compensate for equal values between the two can adversely affect yield.

As a result, OPC must be stabilized in a series of processes, and the OPC process should be considered in relation to yield to increase OPC accuracy.

Claims (3)

A first step of measuring CD data of an accurate sample pattern; A second step of tuning an optical parameter and a resist parameter with the measured CD data to produce a model; And a third step of detecting accuracy by overlapping the print image of the model and the SEM image of the sample pattern; The optical parameters include defocus, NA, aperture type, and sigma, and in the third step, tuning the optical parameters comprises optimizing the defocus, NA, window type, sigma and then again A method of manufacturing a model for proximity effect correction, characterized in that the simulation value and the measured value are adjusted to the intensity log slope. delete delete

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