KR100684328B1 - Link apparatus using low voltage differential signal - Google Patents

Abstract

A link apparatus using an LVDS(Low Voltage Differential Signal) is provided to be adapted to transceiving of frame data having a limited length or frame data having a wide width by using the LVDS. A link apparatus using an LVDS includes an upper serial-parallel conversion unit(110), and a lower serial-parallel conversion unit(120). The upper serial-parallel conversion unit(110) includes a first serial conversion unit(111), and a first parallel conversion unit(112). The first serial conversion unit(111) converts first parallel data transmitted from one side into serial data, and outputs the converted data to the other side through a first LVDS signal. The first parallel conversion unit(112) converts first serial data received from the other side through a second LVDS signal into parallel data, and outputs the converted data to the one side. The lower serial-parallel conversion unit(120) includes a second serial conversion unit(121), and a second parallel conversion unit(122). The second serial conversion unit(121) converts second parallel data transmitted from one side into serial data, and outputs the converted data to the other side through a third LVDS signal. The second parallel conversion unit(122) converts second serial data received from the other side through a fourth LVDS signal into parallel data, and outputs the converted data to the one side.

Description

LINK APPARATUS USING LOW VOLTAGE DIFFERENTIAL SIGNAL

1 is a view schematically showing a link device using a low voltage differential signal according to an embodiment of the present invention.

2 is a diagram illustrating in detail a link device using a low voltage differential signal according to an exemplary embodiment of the present invention.

3 is a diagram illustrating signal timing of transmission data, EoF flag data, and valid data.

The present invention relates to a link device capable of transmitting and receiving a frame using a low voltage differential signal.

Transmitting and receiving data using Low Voltage Differential Signal (LVDS) is more resistant to noise than conventional methods of transmitting and receiving data using single-ended signals, and is more effective than using data from pECL (pseudo-ECL) signals. Signal termination is easier than the transmit / receive method. In addition, since high-speed transmission and reception of Gbps or more is possible, even when serializing and transmitting relatively low-speed parallel data at high speed and then parallelizing the serial data received at the receiving side, the link speed does not have a long delay from transmission to reception. Due to these characteristics, the LVDS method is particularly suitable for serializing and transmitting parallel data such as bus signals.

However, when the width of parallel data to be transmitted is large, the delay time for serialization at the transmitter and parallelism at the receiver is increased, so most LVDS devices have a relatively small parallel data width, for example, 8 bits or more. 16-bit data is serialized and deserialized. In order to implement a bus signal having a data width of 32 bits or more using an LVDS device in which the 8-bit or 16-bit data is serialized in parallel, one parallel data must be divided into 8 bits or 16 bits and transmitted. However, it requires additional logic to distinguish the boundaries of individual parallel data in the stage, and increases the time taken for deserialization, resulting in a long transmission delay time. In addition, when sending frame data having a finite length rather than stream data, a method such as bit stuffing that adds separate control data to distinguish the beginning and end of a frame is required. There is also the difficulty of requiring additional control logic circuits.

An object of the present invention is to provide a link device using a low voltage differential signal suitable for transmission and reception of finite length frame data or wide frame data.

According to one aspect of the present invention, there is provided a link device for transmitting and receiving data using a Low Voltage Differential Signal (LVDS) between parallel data and serial data. The link device serializes the first parallel data transmitted from one side and serializes the first parallel data received from the other side by using a first LVDS signal and a second LVDS signal from the other side. A higher serialization unit including a first parallelization unit outputting to one side of the upper parallelizing unit; And a second serializer for serializing the second parallel data transmitted from one side and outputting the second parallel data to the other side using a third LVDS signal, and parallelizing the second serial data received using the fourth LVDS signal from the other side. And a lower serialization unit including a second parallelization unit outputting to one side, wherein the first and second parallel data are serialized at the same time, and the first and second serial data are simultaneously parallelized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification. In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

Now, a link device using a low voltage differential signal according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view schematically showing a link device using a low voltage differential signal according to an embodiment of the present invention. 1 illustrates data input and output to two link devices 100 and 20.

As shown in FIG. 1, each of the link devices 100 and 200 is connected to four low voltage differential signal pairs LVDS_0 ±, LVDS_1 ±, LVDS_2 ±, and LVDS_3 ±, respectively, and each of two serialization units 110 and 120 internally. , 210, 220). Hereinafter, the two link devices 100 and 200 will be referred to as first and second link units 100 and 200, respectively, and will be described based on data input and output based on the first link unit 100.

The first link unit 100 includes an upper serialization unit 110 and a lower serialization unit 120. The upper deserialization unit 110 is responsible for serializing the upper predetermined bits of the transmission / reception data, and the lower deserialization unit 120 is responsible for the serialization of the lower predetermined bits of the transmission / reception data.

Specifically, the upper serialization unit 110 includes a serialization unit 111 and a parallelization unit 112, and the serialization unit 111 serializes the inputted parallel transmission data of the predetermined upper order bits by using its own transmission clock. After serialization), it is output as low voltage differential signal (LVDS_0 +, LVDS_0-). The parallelizer 112 deserializes the serially received data of the upper predetermined bits received as the low voltage differential signals LVDS_1 + and LVDS_1− and outputs the parallel data of the predetermined bits.

The lower serialization unit 120 also includes a serialization unit 121 and a parallelization unit 122 similarly to the upper serialization unit 110, and the serialization unit 121 transmits the parallel transmission data of the predetermined lower predetermined bits. After serialization using a clock, the low voltage differential signals LVDS_2 + and LVDS_2- are output. The parallelizer 112 outputs the serial data of the lower predetermined bits received as the low voltage differential signals LVDS_3 + and LVDS_3- in parallel.

Like the first link unit 100, the second link unit 200 includes an upper serialized parallel unit 210 and a lower serialized parallel unit 220. The upper deserialization unit 210 is responsible for serializing the upper predetermined bits of the transmission / reception data, and the lower deserialization unit 220 is responsible for the serialization of the lower predetermined bits of the transmission / reception data.

Specifically, the upper serialization unit 210 includes a serialization unit 211 and a parallelization unit 212, and the serialization unit 211 serializes the inputted parallel transmission data of the predetermined upper order bits using its own transmission clock. After serialization, the signal is output as low voltage differential signals LVDS_1 + and LVDS_1-. The parallelization unit 212 parallelizes and outputs parallel transmission data of the upper predetermined bits received as the low voltage differential signals LVDS_0 + and LVDS_0-.

The lower serialization unit 220 also includes a serialization unit 221 and a parallelization unit 222. The serialization unit 221 serializes the parallel transmission data of the lower predetermined bits inputted using its own transmission clock. The low voltage differential signals LVDS_2 + and LVDS_2- are then output. The parallelization unit 222 parallelizes and outputs serial data of the lower predetermined bits received as the low voltage differential signals LVDS_3 + and LVDS_3-.

That is, the 32-bit frame data transmission / reception between the first and second link units 100 and 200 connected to four low voltage differential signal pairs LVDS_0 ±, LVDS_1 ±, LVDS_2 ±, LVDS_3 ± is performed by the first link unit ( The serial link unit 110 of the upper serialized serialization unit 110 of the upper parallel serialization unit 110 serializes the upper 16 bits of parallel transmission data using its own transmission clock, and then uses the second link unit as the low voltage differential signals LVDS_0 + and LVDS_0-. The data is transmitted to the parallelization unit 212 of the higher serialization unit 210 of 200. In addition, the serialization unit 121 of the lower serialization unit 120 of the first link unit 100 also serializes the lower 16-bit parallel transmission data using its own transmission clock and then uses the low voltage differential signals LVDS_2 + and LVDS_2-. ) To the parallelization unit 222 of the lower serialization unit 220 of the second link unit 200. In this manner, the first link unit 100 transmits the input 32-bit parallel data to the second link unit 200 on the other side.

In addition, the parallelization unit 112 of the upper-parallel parallelization unit 110 of the first link unit 100 is connected to the low-voltage differential signal from the serialization unit 211 of the upper-parallel parallelization unit 210 of the second link unit 200. Parallel data of upper 16 bits received by LVDS_1 + and LVDS_1-) is output in parallel. In addition, the parallelization unit 122 of the lower serialization unit 120 of the first link unit 100 also receives the low voltage differential signal LVDS_3 + from the serialization unit 221 of the lower serialization unit 220 of the second link unit 200. , And outputs the serial data of the lower 16 bits received by LVDS_3-) in parallel. In this way, the first link unit 100 receives the 32-bit parallel data by parallelizing the 32-bit serial data transmitted from the second link unit 200.

Meanwhile, the upper serialization unit 110 and 210 and the lower serialization unit 120 and 220 are devices of the same type, and referring to FIG. 1 again, the upper serialization unit 110 of the first link unit 100 may be used. More specifically, the serialization unit 111 transmits the transmission data of the upper predetermined bit as a low voltage differential signal based on its own transmission clock, but the parallelization unit 112a recovers the clock from the received low voltage differential signal. After that, the paralleled data is output based on the restored clock. In order to restore such a clock, the serialization unit 211 of the upper-parallel serialization unit 210 of the second link unit 200 that is the other side should continuously send specific link test data to the parallelization unit 112 for a predetermined time. Therefore, the serialization unit 211 should apply specific link test data for clock recovery until the time before the clock recovery is possible, and apply actual transmission data from the time after the clock recovery is possible.

On the other hand, the serializer 211 is the clock of the parallelizer 112 in order for the serializer 211 of the second link unit 200, which is the opposite side, to apply the actual transmission data after the parallelizer 112 can recover the clock. Know the restorable state. To this end, when the parallelizing unit 112 becomes the clock restorable state, the serialization unit 111 in the same serialization unit 110 may set other constant test data for the state transmission for a predetermined time, not specific test data for clock restoration. 2 is transmitted to the parallelization unit 212 of the link unit 200. The deserialization unit 210 to which the parallelization unit 212 is received controls the serialization unit 211, and the serialization unit 211 applies actual transmission data instead of specific test data for clock recovery. Hereinafter, such a detailed control signal and components added by the control signal will be described in detail with reference to FIG. 2.

2 is a diagram illustrating in detail a link device using a low voltage differential signal according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating signal timing of transmission data, EoF flag data, and valid data. As described with reference to FIG. 1, the first link unit is described with reference to 32 bits of transmit / receive data and each of the serializers 110, 120, 210, and 220 transmits and receives 18 bits of data.

As shown in FIG. 2, the first link unit 100 includes an upper transmit multiplexer 131, a lower transmit multiplexer 132, an upper receive demultiplexer 141, a lower receive demultiplexer 142, and an upper rank. The first-in first-out unit 151, the first-in first-out unit 152, the first-in first-out unit 160, and the link control unit 170 are further included.

The upper transmission multiplexer 131 transmits the upper 16 bits of the 32-bit transmission data to be actually transmitted or the test data generated by the link control unit 170 to the serialization unit 111 of the higher serialization unit 110. Output In this case, the test data may be specific link test data for clock recovery or other constant test data for transmission of a clock recovery state.

The lower transmission multiplexer 132 transmits the lower 16-bit transmission data or the test data generated by the link control unit 170 among the 32-bit transmission data to be actually transmitted to the serialization unit 121 of the lower serialization unit 120. Output

The upper reception demultiplexer 141 may link the link control unit 170 or the upper level 17-bit data including one bit of control data and 16 bits of data among the parallel data output from the parallelization unit 112 of the upper deserialization unit 110. Output to the first-in, first-out unit 151. In this case, the upper reception demultiplexer 141 outputs the 17-bit data to the upper-in first-out unit 151 when the 17-bit data includes the actual received data, and links the 17-bit data when the 17-bit data includes the test data. Output to the controller 170.

The lower reception demultiplexer 142 may transmit 16-bit data excluding one bit of control data among the parallel data output from the parallelization unit 122 of the lower serialization unit 120 to the link control unit 170 or the lower first-in-first-out unit ( 152). In this case, like the upper receiving demultiplexing unit 141, the lower receiving demultiplexer 142 outputs the 16-bit data to the lower first-in first-out part 152 when the 16-bit data includes the actual receiving data. If the test data is included, it is output to the link control unit 170.

The upper first-in first-out part 151 stores 17 bits of data including one bit of control data output from the upper receiving demultiplexer 141.

The lower first-in-first-out unit 152 stores 16-bit data output from the lower reception demultiplexer 142.

The final first-in first-out unit 160 receives the 17-bit output of the first-in first-out unit 151 and the 16-bit output of the lower first-in first-out unit 152 and stores 33 bits of data including one bit of control data.

The link control unit 170 is an essential part of controlling all parts of the first link unit 100. The link control unit 170 controls transmission and reception of test data for clock recovery of the parallelization units 112 and 122, and controls frame data and garbage value ( The garbage is classified and the first-in first-out unit 151, the first-in first-out unit 152, and the last-in first-out unit 160 are controlled.

In more detail, the function of each component is as follows.

The upper transmission multiplexing unit 131 transmits the upper 16 bits of the transmission data TxData [31:16] from the 32 bits of transmission data TxData [31: 0] input to the first link unit 100 for transmission. The 16-bit test data from the link control unit 170 is multiplexed to output 16-bit data TxD [33:18] under the control of the link control unit 170. In this case, the 16-bit test data input by the link control unit 170 to the upper transmission multiplexer 131 is connected to the serialization unit 111 of the upper serialization unit 110 by low voltage differential signals LVDS_0 + and LVDS_0-. 2 When the test data for the clock restoration of the parallelization unit 212 of the upper serialization unit 210 of the link unit 200 or the clock restoration restoration state becomes available in the parallelization unit 122 of the upper serialization unit 110. Test data for informing the second link unit 200.

Meanwhile, one-bit control data TxD [35] of the two-bit control data TxD [35:34] output from the link control unit 170 is data of 16 bits output from the upper transmission multiplexer 131. (TxD [33:18]) is valid data indicating whether it is test data or actual transmission data, and one-bit control data TxD [34] is a 16-bit output from the upper transmission multiplexer 131. The data TxD [33:18] and the 16-bit data TxD [15: 0] output from the lower transmission multiplexer 132 are End of Frame (EoF) flag data indicating that they are the last data of the frame. As shown in FIG. 3, valid data is set and output, and EoF flag data is set and output at the end of the transmission data. 3 illustrates a case in which the frame length is 7x32 bits. 18-bit input data (TxD [35:18]) in which the 16-bit data (TxD [33:18]) output from the upper transmission multiplexer 131 and the two-bit control data (TxD [35:34]) are combined. ]) Is input to the serialization unit 111 of the upper serialization unit 110 of the first link unit 100. The serialization unit 111 serializes the 18-bit input data TxD [35:18] and transmits the low-voltage differential signal to the parallelization unit 212 of the higher-order serialization unit 210 of the second link unit 200 as a low voltage differential signal. do.

The lower transmission multiplexer 132 and the lower 16 bits of the transmission data (TxData [15: 0]) from the 32-bit transmission data (TxData [31: 0]) input to the first link unit 200 for transmission. 16-bit test data from the link control unit 170 is multiplexed to output 16-bit data TxD [15: 0] under the control of the link control unit 170. In this case, the 16-bit test data input by the link control unit 170 to the lower transmission multiplexer 132 is connected to the serialization unit 111 of the lower serialization unit 110 by low voltage differential signals LVDS_0 + and LVDS_0-. 2 When the test data for the clock restoration of the parallelization unit 222 of the lower serialization unit 220 of the link unit 200 or the clock restoration possible state of the parallelization unit 122 of the lower serialization unit 120 is changed. Test data for informing the second link unit 200.

Meanwhile, one bit of control data TxD [17] of the two bits of control data TxD [17:16] output from the link control unit 170 is data of 16 bits output from the lower transmission multiplexer 131. (TxD [15: 0]) is a valid bit indicating whether it is test data or actual transmission data, and one-bit control data TxD [16] is the final first-in-first-out part of the first link unit 100 ( Full flag data indicating a state in which the 160 is full of received data and can no longer be received. 18-bit input data (TxD [17: 0) in which the 16-bit data TxD [15: 0] output from the lower transmission multiplexer 132 and the two-bit control data TxD [17:16] are combined. ]) Is input to the serialization unit 121 of the lower serialization unit 120 of the first link unit 100. The serialization unit 121 serializes the 18-bit input data TxD [17: 0] and parallelizes the lower deserialization unit 220 of the second link unit 200 with the low voltage differential signals LVDS_2 + and LVDS_2-. Transmit to unit 222.

The upper receiving demultiplexer 141 parallelizes the data received as the low voltage differential signals LVDS_1 + and LVDS_1- by the parallelizing unit 112 of the upper deserializing unit 110 and outputs the data RxD [35:18]. Demultiplexes the 17-bit data RxD [34:18] into the link control unit 170 in the case of test data under the control of the link control unit 170, and in the case of the actual received data, the first-in first-out unit 151 ) At this time, one bit of control data RxD [34] of the 17-bit data RxD [34:18] is received EoF flag data.

On the other hand, one bit of control data RxD [35] is applied to the link control unit 170 as received valid data, and the link control unit 170 is set to 17 bits only when valid data is set. The upper receiving demultiplexer 141 is controlled to output the data RxD [34:18] to the upper first-in first-out unit 151. By doing so, the garbage value between the frame and the frame is prevented from being stored in the upper first-in first-out part 151.

The lower receiving demultiplexer 142 parallelizes the data received as the low voltage differential signals LVDS_3 + and LVDS_3- by the parallelizing unit 122 of the lower deserializing unit 120 and outputs the data RxD [17: 0]. Demultiplexes the 16-bit data RxD [15: 0] into the link control unit 170 in the case of test data under the control of the link control unit 170, and the lower first-in first-out unit 152 in the case of actual received data. )

On the other hand, the data RxD [17] is applied to the link control unit 170 as received valid data, and the link control unit 170 only uses 16-bit data RxD [when valid data is set. 15: 0]) to control the lower reception demultiplexer 142 to output the first-in first-out unit 152. This prevents garbage between the frame and the frame from being stored in the lower first-in, first-out unit 152. The data RxD [16] is a signal indicating when the final first-in, first-out of the second link unit 200 connected to the first link unit 100 and the low voltage differential signal as full flag data can no longer store data. . This data RxD [16] is applied to the link control unit 170. When the full control flag data is set, the link control unit 170 sets the full flag data for the last-in first-out unit of the second link unit 200. Data transmission from the first link unit 100 to the second link unit 200 is stopped until is cleared.

The final first-in first-out unit 160 includes 17 bits of data RxD [34:18] output from the first-in first-out unit 151 and the 16-bit data RxD [15: output from the first-in first-out unit 152. 0]) are combined to store 33 bits of data. At this time, the output of the last-in first-out unit 160 is output as 32-bit received data (RxData [31: 0]) and 1-bit EoF flag data, and 32-bit received data (RxData [31: 0]) is output. If there is data in the final first-in, first-out unit 160, the reading apparatus can read data one frame at a time until the EoF flag signal is set. Also, the final first-in first-out unit 160 notifies the link control unit 170 when there is no more space to store data output from the first-in first-out unit 151 and the lower first-in first-out unit 152 and the link control unit 170 lowers. Set the full flag data RxD [16] input to the deserialization unit 120 so as not to send any more data to the second link unit 200 connected to the first link unit 100 through the low voltage differential signal. Inform.

As such, the signal input to the first link unit 100 from the transmitter connected to the first link unit 100 includes 32-bit transmission data (TxData [31: 0]), EoF flag data, and valid data. The signal received from the first link unit 100 in the receiving device connected to the first link unit 100 includes 32-bit received data RxData [31: 0] and EoF flag data.

Meanwhile, in the embodiment of the present invention, the deserialization of 32-bit data has been described. However, the deserialization of 64-bit data can be easily performed.

The embodiments of the present invention described above are not implemented only through an apparatus and a method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. From the description of the above-described embodiment can be easily implemented by those skilled in the art.

The above embodiments are intended to illustrate the present invention, the scope of the present invention is not limited to the embodiments, it can be modified or modified by those skilled in the art within the scope of the invention defined by the appended claims.

According to the above configuration, the signal termination process is easier than the conventional method of transmitting / receiving data using a single-ended signal and the method of transmitting / receiving data using a pELC signal. It is also suitable for ultra-fast transmission and reception of parallel data of Gbps or more, and is suitable for link devices connecting data processing devices having a finite length.

Claims (12)

In a link device for transmitting and receiving data using a low voltage differential signal (LVDS) between parallel data and serial data, The first serializer serializes the first parallel data transmitted from one side and outputs it to the other side using the first LVDS signal, and parallelizes the first serial data received from the other side using the second LVDS signal and outputs the same to the one side. A higher serialization unit including a first parallelization unit; And A second serializer for serializing the second parallel data transmitted from the one side and outputting the second parallel data to the other side by using a third LVDS signal and parallelizing the second serial data received from the other side using a fourth LVDS signal; Lower serialization unit including a second parallelization unit for outputting Including; And the first and second parallel data are serialized simultaneously and the first and second serial data are paralleled simultaneously. The method of claim 1, And the first and second parallel data and the first and second serial data are 18 bits of data. The method of claim 2, The first parallel data includes one of a clock recovery related test data and transmission data of an upper predetermined bit and first control data; The second parallel data includes one of the test data and the lower predetermined bits of transmission data and second control data, The first serial data includes one of the test data and received data of upper predetermined bits and third control data, And the second serial data includes one of the test data and received data of a lower predetermined bit and a fourth control data. The method of claim 3, Each of the upper / lower transmit / receive data is a 16-bit data link device using a low voltage differential signal. The method of claim 4, wherein An upper transmission multiplexer which outputs the test data or the transmission data of the upper predetermined bit to the first serializer; A lower transmission multiplexer which outputs the test data or the lower predetermined bit transmission data to the second serializer; An upper first-in first-out unit configured to store and output a part of the received data of the upper predetermined bit and the third control data among the output data of the first parallelization unit; A lower first-in first-out unit that stores and outputs received data of the lower predetermined bits among the output data of the second parallelization unit; An upper reception demultiplexer for outputting a part of the upper predetermined bit received data and the second control data to the upper first-in first-out part; A lower reception demultiplexer for outputting received data of the lower predetermined bit to the lower first-in first-out part; A final first-in first-out unit for storing and outputting data output from the upper first-in first-out unit and the lower first-in first-out unit; And Link control unit for controlling the upper / lower transmission multiplexer, upper / lower first-in first-out, upper / lower receiving demultiplexer and the final first-in first-out Link device using a low voltage differential signal further comprising. The method of claim 5, And the control data stored in the last-in first-out part is a low voltage differential signal which is End of Frame (EoF) flag data indicating the end of a frame. The method of claim 6, The first control data includes valid data indicating whether an output of the upper transmission multiplexer is the transmission data and the end of frame (EoF) flag data, The second control data includes valid data indicating whether the output of the first parallelization unit is the received data and the EoF flag data. The third control data includes valid data indicating whether an output of the lower transmission multiplexer is the transmission data and full flag data indicating a memory state of the last-in first-out section; And the fourth control data includes valid data indicating whether the output of the second parallelizing unit is the received data and full flag data indicating the interruption of data transmission from the other side. The method of claim 7, wherein And the link control unit uses a low voltage differential signal to respectively control the upper / lower first-in first-out unit based on the valid data of the third and fourth data. The method of claim 7, wherein And the link control unit uses the low voltage differential signal to transmit the full flag data to the other side based on the memory state of the last-in first-out unit. The method according to any one of claims 3 to 9, The clock recovery related test data includes a clock recovery test data used for clock recovery and a link device using a low voltage differential signal including a state transmission test data for transmitting a clock recovery state. The method of claim 10, And the link control unit outputs the state transmission test data to the first and second serialization units based on the clock recovery states of the first and second parallelization units. The method of claim 11, And the link control unit outputs transmission data of the upper and lower predetermined bits to the first and second serialization units, respectively, according to whether the test data for status transmission is received from the other side.

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