CN114564441B

CN114564441B - System on chip, data processing method and computer equipment

Info

Publication number: CN114564441B
Application number: CN202210432754.9A
Authority: CN
Inventors: 李纪先; 朱青山; 张璐; 高鹏飞
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2022-07-05
Anticipated expiration: 2042-04-24
Also published as: CN114564441A

Abstract

The embodiment of the application provides a system on chip, a data processing method and computer equipment, wherein the system on chip comprises a sending unit; the transmission unit includes: the device comprises a plurality of first storage units and an alignment control unit, wherein each first storage unit is respectively connected with the alignment control unit; the first storage unit includes: a first de-skew cache; the first deskew cache is used for storing data to be transmitted, and the data to be transmitted includes: load data and alignment data, wherein the alignment data comprises a starting identifier and an ending identifier; the alignment control unit is configured to identify a start identifier and an end identifier of the alignment data in each first deskew cache, and read and send the data to be transmitted from each first deskew cache after identifying the start identifier and the end identifier of the alignment data. By the method and the device, the data are firstly aligned once at the sending unit side, so that the efficiency of data alignment can be ensured.

Description

System on chip, data processing method and computer equipment

Technical Field

The present application relates to the field of chip technologies, and in particular, to a system on chip, a data processing method, and a computer device.

Background

Devices may communicate with each other via multiple communication links, and thus there may be situations where multiple links are transmitting data simultaneously. Skew may occur between links due to different wiring lengths, different impedance variations, different temperature variations, different voltage variations, etc. between different links. Wherein skew may refer to that even if bitstream data is transmitted simultaneously on the transmitting side, there may be a difference in arrival time of the bitstream data on each link on the receiving side. Skew between links can cause problems such as reduced link performance. Therefore, how to correct the skew between the links is an urgent problem to be solved.

In the prior art, an elastic First-in First-out queue (FIFO for short) is arranged on each link of a receiving side, and is used for aligning data between different links.

However, the prior art approach may affect the efficiency of data alignment.

Disclosure of Invention

An object of the present application is to provide a system on chip, a data processing method, and a computer device, so as to solve the problem that the efficiency of data alignment is affected due to aligning data between different links on a receiving side in the prior art.

In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

in a first aspect, an embodiment of the present application provides a system on a chip, including: a transmitting unit; the transmission unit includes: the device comprises a plurality of first storage units and an alignment control unit, wherein each first storage unit is respectively connected with the alignment control unit; the first storage unit includes: a first de-skew cache; the first deskew cache is used for storing data to be transmitted, and the data to be transmitted includes: load data and alignment data, wherein the alignment data comprises a starting identifier and an ending identifier;

the alignment control unit is configured to identify a start identifier and an end identifier of the alignment data in each first deskew cache, and read and send the data to be transmitted from each first deskew cache after identifying the start identifier and the end identifier of the alignment data.

The method comprises the steps that a plurality of first de-skew caches and an alignment control unit are arranged in a sending unit of the system on chip, the first de-skew caches can cache load data and alignment data special for data alignment, the alignment control unit can judge whether the sending unit side achieves data alignment or not by identifying a starting mark and an ending mark of the alignment data in each first de-skew cache, and if yes, the alignment control unit reads and sends data to be transmitted from each first de-skew cache. Through the processing, the data is firstly aligned once on the sending unit side, so that the efficiency of data alignment can be ensured.

As a possible implementation manner, the system on chip further includes: a receiving unit;

the receiving unit includes: the buffer memory comprises a plurality of second storage units and a plurality of elastic buffer memory control units connected with the second storage units; each of the second storage units includes: elastic caching;

the elastic buffer is used for storing received data, the elastic buffer control unit is used for adjusting alignment data in the received data of the elastic buffer according to the data read-write speed of the receiving unit, and the received data comprises: the device comprises load data and alignment data, wherein the alignment data comprises a starting mark and an ending mark.

By storing the received data into the elastic buffer and adjusting the alignment data in the received data of the elastic buffer according to the data read-write speed of the receiving unit, data alignment can be realized for different communication links.

As a possible implementation manner, each of the second storage units further includes: a second de-skew cache coupled to the elastic cache;

the receiving unit further includes: the second deskew cache in each second storage unit is respectively connected with the deskew control unit;

the second de-skew buffer is used for reading and storing received data from the elastic buffer;

the deskew control unit is configured to identify a start identifier and an end identifier of the alignment data in each of the second deskew buffers, and read the received data from each of the second deskew buffers after identifying the start identifier and the end identifier of the alignment data.

The receiving unit is additionally provided with a plurality of second de-skew buffers and de-skew control units, the second de-skew buffers read and store the received data from the elastic buffers, and the de-skew control units identify the start marks and the end marks of the aligned data in the second de-skew buffers, so that the read control of the second de-skew buffers by the de-skew control units is realized, and further the dynamic de-skew correction in the receiving side is realized.

As a possible implementation manner, the receiving unit further includes: a plurality of load control units; each load control unit is respectively connected with the elastic buffer and the second de-deflection buffer;

the load control unit is used for controlling the second de-skew cache to read from the elastic cache and store the received data when detecting that the alignment data in the elastic cache has a start mark and an end mark and the depth information of the second de-skew cache is smaller than a first preset threshold value.

The load control unit can read and store the received data from the corresponding elastic buffer memory through the corresponding second de-skew buffer memory, so that the dynamic writing of the received data into the second de-skew buffer memory is realized, the safety of data writing is ensured, and the dynamic reading of the data of the subsequent second de-skew buffer memory is further ensured to realize the dynamic de-skew correction in the receiving side.

As a possible implementation manner, the load control unit is specifically configured to: when detecting that the alignment data in the elastic cache has a start identifier and an end identifier and the depth information of the second de-skew cache is smaller than the first preset threshold, adjusting the value of a write enable flag, and controlling the second de-skew cache to read and store the received data from the elastic cache;

the second deskew cache is specifically configured to: and reading and storing the received data from the elastic cache when the value of the write enabling mark is a second preset value.

By adjusting the write enable flag, the load control unit can quickly determine whether to allow the second de-skew buffer to read and store the received data from the elastic buffer according to the value of the write enable flag, the control efficiency is high, and no additional resource is occupied while the dynamic skew correction is realized.

As a possible implementation, the deskew control unit is specifically configured to: and when the alignment data in each second de-skew cache is identified to have a start identifier and an end identifier, adjusting the value of a read enable flag, and when the value of the read enable flag is a second preset value, reading the received data from each second de-skew cache.

By adjusting the read enable flag, the deskew control unit can quickly determine whether to read data from the second deskew cache according to the value of the read enable flag, the control efficiency is high, and no additional resource is occupied while dynamic skew correction is realized.

As a possible implementation, the deskew control unit is further configured to: and determining whether a data transmission link is abnormal or not by taking the start identifier and the end identifier of the alignment data in each second deskew cache as judgment bases, and performing retraining processing, reinitialization processing or link recovery processing on the data transmission link when the data transmission link is abnormal.

And the fast recovery of the communication link can be realized by utilizing the judgment of the deskew control unit on the alignment data in the second deskew buffer.

As a possible implementation manner, the receiving unit further includes: a plurality of ordered set control units; each ordered set control unit is respectively connected with the de-deflection control unit and the load control unit;

the ordered set control unit is used for receiving an ordered set control instruction of the de-skew control unit and correspondingly sending an ordered set control signal to the load control unit, wherein the ordered set control signal is used for indicating whether the load control unit is allowed to write an alignment symbol into the second de-skew cache or not;

the load control unit is further configured to write an alignment symbol to the second deskew buffer when the ordered set control signal indicates that the load control unit is allowed to write an alignment symbol to the second deskew buffer, the alignment symbol comprising: the ordered set symbols and/or idle frames may be ignored.

The on/off of the alignment symbol writing function of the load control unit can be flexibly controlled by arranging the order set control unit, and when the alignment symbol writing function of the load control unit is on, the load control unit can write the alignment symbol into the second de-skew cache so as to further ensure the data alignment effect.

As a possible implementation manner, the receiving unit further includes: a second user logic unit; the second user logic unit is connected with the de-skew control unit;

the deskew control unit is further configured to control attribute information of each second deskew cache according to configuration information sent by the second user logic unit, where the attribute information includes at least one of the following: cache size, data processing bit width.

As a possible implementation manner, the alignment control unit is specifically configured to: and after the initial identification and the end identification of the aligned data in each first de-skew cache are identified, if the depth information of each first de-skew cache is greater than a second preset threshold, reading and sending the data to be transmitted from each first de-skew cache.

As a possible implementation manner, the sending unit further includes: a first user logic unit; the first user logic unit is connected with each first de-skew cache;

the first user logic unit is configured to control attribute information of each first deskew cache according to preset configuration information, where the attribute information includes at least one of: cache size, data processing bit width.

By setting the first user logic unit and the second user logic unit, flexible configuration of the first de-skew buffer and the second de-skew buffer can be achieved.

In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a system on chip, where the system on chip includes: a transmission unit, the transmission unit including: the device comprises a plurality of first storage units and a first control unit, wherein each first storage unit is connected with the first control unit; the first storage unit includes: a first de-skew buffer to store data to be transmitted, the data to be transmitted comprising: load data and alignment data, wherein the alignment data comprises a starting identifier and an ending identifier; the method comprises the following steps:

the first control unit identifies the start mark and the end mark of the alignment data in each first de-skew cache, and reads and sends the data to be transmitted from each first de-skew cache after identifying the start mark and the end mark of the alignment data.

As a possible implementation manner, the system on chip further includes: a receiving unit; the receiving unit includes: a plurality of second storage units and a second control unit, the second storage unit including: elastic caching; the elastic buffer is used for storing the received data; the method further comprises the following steps:

the second control unit adjusts the alignment data in the received data of the elastic cache according to the data read-write speed of the receiving unit, wherein the received data comprises: the device comprises load data and alignment data, wherein the alignment data comprises a starting mark and an ending mark.

As a possible implementation manner, each of the second storage units further includes: a second de-skew buffer connected to the elastic buffer, the second de-skew buffer configured to read and store received data from the elastic buffer; the method further comprises the following steps:

the second control unit identifies a start identifier and an end identifier of the alignment data in each second deskew cache, and reads the received data from each second deskew cache after identifying the start identifier and the end identifier of the alignment data.

As a possible implementation, the method further includes:

and the second control unit controls the second de-skew cache to read and store the received data from the elastic cache when detecting that the alignment data in the elastic cache has a start mark and an end mark and the depth information of the second de-skew cache is smaller than a first preset threshold value.

As a possible implementation manner, when detecting that the alignment data in the elastic buffer has a start identifier and an end identifier, and the depth information of the second de-skew buffer is smaller than a first preset threshold, the second control unit controls the second de-skew buffer to read and store the received data from the elastic buffer, including:

and when detecting that the alignment data in the elastic cache has a start identifier and an end identifier and the depth information of the second de-skew cache is smaller than the first preset threshold value, the second control unit adjusts the value of a write enable identifier and controls the second de-skew cache to read and store the received data from the elastic cache, so that when the value of the write enable identifier of the second de-skew cache is a second preset value, the second control unit reads and stores the received data from the elastic cache.

As a possible implementation manner, the second control unit identifies a start identifier and an end identifier of the alignment data in each second deskew buffer, and reads the received data from each second deskew buffer after identifying the start identifier and the end identifier of the alignment data, including:

the second control unit adjusts a value of a read enable flag when recognizing that the alignment data in each of the second deskew caches has a start flag and an end flag, and reads the received data from each of the second deskew caches when the value of the read enable flag is a second preset value.

As a possible implementation, the method further includes:

and the second control unit determines whether the data transmission link is abnormal or not by taking the start identifier and the end identifier of the aligned data in each second de-skew cache as a judgment basis, and performs retraining processing, reinitialization processing or link recovery processing on the data transmission link when the data transmission link is abnormal.

As a possible implementation, the method further includes:

the second control unit determines whether to write an alignment symbol to the second deskew cache;

if yes, writing an alignment symbol into the second de-skew cache, wherein the alignment symbol comprises: the ordered set symbols and/or idle frames may be ignored.

As a possible implementation, the method further includes:

the second control unit controls attribute information of each second deskew cache according to configuration information, wherein the attribute information comprises at least one of the following items: cache size, data processing bit width.

As a possible implementation manner, the first control unit identifies a start identifier and an end identifier of the alignment data in each first deskew cache, and reads and sends the data to be transmitted from each first deskew cache after identifying the start identifier and the end identifier of the alignment data, including:

the first control unit identifies a start identifier and an end identifier of the aligned data in each first de-skew cache, and reads and sends the data to be transmitted from each first de-skew cache after identifying the start identifier and the end identifier of the aligned data and if the depth information of the first de-skew cache is greater than a second preset threshold.

As a possible implementation, the method further includes:

In a third aspect, an embodiment of the present application provides a computer device, including the system on chip described in the first aspect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic view of a scene corresponding to a system on chip and a data processing method provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a system on chip according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a transmitting unit of a system on chip according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another configuration of a system on a chip according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another structure of a system-on-chip according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another embodiment of a system on a chip;

FIG. 7 is a schematic diagram of a system-on-chip according to an embodiment of the present application;

fig. 8 is a flowchart illustrating a data processing method according to an embodiment of the present application.

Detailed Description

For the purpose of making the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustration and description only and are not used to limit the protection scope of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.

The existing method for correcting link skew is to arrange an elastic FIFO on each link on the receiving side to align data between different links. However, this approach focuses all the processing of data alignment on the receiving side, which may affect the efficiency of data alignment when the processing resources of the receiving side are limited.

Based on the above problems, embodiments of the present application provide a system on a chip and a corresponding method thereof, which add a first deskew buffer and an alignment control unit on a sending side, so that data is aligned at the sending side at first once, thereby ensuring data alignment efficiency. In addition, the embodiment of the application can realize dynamic reading of data by adding the elastic buffer, the second deskew buffer and the corresponding control unit at the receiving side, further realize alignment of the data and dynamic deskew correction, and greatly improve the flexibility and correction effect of deskew correction.

The system on chip and the corresponding data processing method thereof provided by the embodiment of the application can be applied to any computer equipment which needs to transmit and process data. A system-on-a-chip (SoC) refers to a technology of integrating a complete system-on-chip on a single chip to package and group electronic circuits of all or part of the chip, and allows a plurality of independent devices on the chip to communicate via a network-on-chip (NoC). With a system on chip, data can be transmitted, received, and processed. The system on chip can correspond to a plurality of communication links, and the data to be transmitted can be transmitted in parallel through the plurality of communication links. The number of communication links may be, for example, 2, 4, 8, 16, or 32, etc., which is not specifically limited in this application. The plurality of communication links may constitute a link, which may be in any type of form. For example, the link may be a high speed serial expansion bus or the like.

Fig. 1 is a scene schematic diagram corresponding to the system on chip and the data processing method provided in the embodiment of the present application, and as shown in fig. 1, the system on chip and the data processing method may be applied to a scene in which multiple computer devices perform data interaction. Fig. 1 illustrates an example of data exchange between a computer device a and a computer device B. When the number of the related computer devices is larger than two, the scheme of the application can be used for data interaction between every two computer devices. Referring to fig. 1, a system-on-chip a1 is included in computer device a, and a system-on-chip B1 is included in computer device B. Data transfer between system-on-chip A1 and system-on-chip B1 occurs in parallel via multiple communication links. Specifically, assuming that the computer device a is a device for sending data and the computer device B is a device for receiving data, the system on chip a1 first aligns data corresponding to each communication link by using the scheme of the present application, and sends the aligned data to the system on chip B1 through each communication link. The system-on-chip B1 utilizes the scheme of the present application to align and dynamically deskew data received over the various communication links.

Hereinafter, the system on chip and the data processing method according to the present application will be described in detail with reference to a plurality of embodiments.

Fig. 2 is a schematic structural diagram of a system on chip according to an embodiment of the present application, and as shown in fig. 1, the system on chip includes: a transmitting unit 1. Wherein, the transmitting unit 1 includes: a plurality of first storage units 11, and an alignment control unit 12. The first storage units 11 are connected to the alignment control unit 12. The first storage unit 11 includes: the first deskew buffer 111.

Alternatively, the first storage units 11 may correspond one-to-one to the communication links. Specifically, for each communication link, a first storage unit 11 is disposed in the system on chip. Accordingly, a first deskew buffer 111 is included in each first storage unit 11.

Illustratively, the first deskew buffer 111 may be a FIFO, or the first deskew buffer 111 may be another type of buffer.

Each first memory cell 11 is connected to the alignment control unit 12, so that the alignment control unit can know the data in each first deskew buffer 111 in each first memory cell 11 and perform alignment control accordingly.

Optionally, the first deskew buffer 111 is configured to store data to be transmitted, where the data to be transmitted includes: load data and alignment data, wherein the alignment data comprises a start identifier and an end identifier.

The load data may include data to be processed, calculated and used by the receiving side, and the alignment data may include data added to achieve data transmission alignment. The alignment data includes the start identifier and the end identifier. Optionally, the first deskew buffer 111 may specifically include load data and control data. The alignment data may be control data or part of control data. The control data may include only alignment data, or may include alignment data and other data symbols for control.

Illustratively, the sending unit 1 may further include a data generating unit, in which case the data generating unit may process the raw data to generate the load data. Thereafter, the load data may be written into each of the first deskew buffers 111 according to a preset policy. In the writing process, the data generation unit periodically writes load data and control data into each first deskew buffer 111 according to the empty condition of each first deskew buffer 111.

It should be noted that the data generating unit may be coupled with the alignment control unit 12, or may be independent from the alignment control unit 12, which is not limited herein.

The alignment data may be data of different forms in consideration of a protocol standard on which the system on chip is based. In one example, if the system on chip is based on the Peripheral Component Interconnect Extended (PCIE) protocol standard, the alignment data may be a SKP ordered set consisting of negligible (Skip) symbols, in which case the SKP ordered set includes a plurality of SKP symbols. The SKP ordered set transmitted by the transmitting unit 1 may include 4 SKP symbols, 12 SKP symbols, 16 SKP symbols, or the like, according to different protocol versions. In another example, if the system on chip is based on the ethernet protocol standard, the alignment data may be an Idle Frame (Idle Frame) or the like.

Optionally, the alignment control unit 12 is configured to identify a start identifier and an end identifier of the alignment data in each first de-skew buffer 111, and read and send the data to be transmitted from each first de-skew buffer 111 after identifying the start identifier and the end identifier of the alignment data.

Taking the example that the alignment data comprises an SKP ordered set and the SKP ordered set comprises 12 SKP symbols, the first symbol in the SKP ordered set is marked as an SKP header symbol and is used as a 2-bit synchronization header, and meanwhile, the SKP ordered set simultaneously comprises an SKP end symbol and three linear feedback shift register symbols. Correspondingly, the SKP header symbol may be used as a start identifier of the alignment data, and the SKP end symbol may be used as a start identifier of the alignment data. The alignment control unit 12 may identify data in each first deskew buffer 111 in real time or periodically, and if a start identifier and an end identifier of the aligned data are identified in each first deskew buffer 111, it indicates data alignment of each communication link on the sending unit 1, and the alignment control unit 12 may further read and send data to be transmitted from each first deskew buffer 111 at the same time.

Alternatively, the alignment control unit may follow the following two constraints when reading data to be transmitted from each first deskew buffer 111.

First, the read clocks of all the first deskew buffers 111 use the same common clock.

Second, if a first deskew buffer 111 is empty, it is not possible to continue reading data from the first deskew buffer 111.

In this embodiment, a plurality of first deskew caches and an alignment control unit are provided in the sending unit, the first deskew caches can cache load data and alignment data dedicated to data alignment, the alignment control unit can determine whether the sending unit side has achieved data alignment by identifying a start identifier and an end identifier of the alignment data in each first deskew cache, and if so, the alignment control unit reads and sends data to be transmitted from each first deskew cache. Through the processing, the data is firstly aligned once on the sending unit side, so that the efficiency of data alignment can be ensured.

As an alternative implementation, the alignment control unit 12 may specifically be configured to:

and identifying a start identifier and an end identifier of the aligned data in each first deskew cache 111, and reading and sending data to be transmitted from each first deskew cache 111 if the depth information of each first deskew cache 111 is greater than a second preset threshold after the start identifier and the end identifier of the aligned data are identified.

Optionally, the depth information of the first deskew buffer 111 may be used to identify the amount of data buffered in the first deskew buffer 111. In the case where the data stored in the first deskew buffer 111 is not empty, the depth information of the first deskew buffer 111 may be greater than a second preset threshold. Accordingly, the data to be transmitted can be read and transmitted from each first deskew buffer 111, thereby ensuring both alignment when the data is transmitted and safe reading of the data.

Fig. 3 is a schematic structural diagram of a transmitting unit of a system on chip according to an embodiment of the present application, and as shown in fig. 3, the transmitting unit 1 further includes: a first user logic unit 13. The first custom logic unit 13 is connected to each of the first deskew buffers 111.

Optionally, the first user logic unit 13 is configured to control attribute information of each first deskew cache 111 according to preset configuration information, where the attribute information includes at least one of the following items: cache size, data processing bit width.

Alternatively, the preset configuration information may be input in advance by a user through an input interface provided by the computer device and stored in the first user logic unit 13. Accordingly, the first user logic unit 13 may control the buffer size, the data processing bit width, and other attribute information of each first deskew buffer 111 according to the configuration information. For example, when the user sets a new buffer size, and the sending unit 1 stores the new configuration information into the first user logic unit 13, the first user logic unit 13 correspondingly adjusts the buffer size of each first deskew buffer 111 to the buffer size set by the user.

By setting the first user logic unit, flexible configuration of each first deskew buffer 111 can be realized.

With continued reference to fig. 3, the transmitting unit 1 may further comprise a serializing unit 14, which serializing unit 14 is connected with the alignment control unit 12. The serializing unit 14 is configured to convert the parallel data sent by the alignment control unit 12 into a single-bit serial data and send out.

Specifically, as described above, the alignment control unit 12 reads and transmits the data to be transmitted from each first deskew buffer 111 after identifying the start identifier and the end identifier of the alignment data of each first deskew buffer 111, where the transmitted data is multiple paths of data transmitted in parallel according to the communication link. For example, the sending unit 1 provides 4 communication links corresponding to 4 first deskew buffers 111, and the alignment control unit reads data from the 4 first deskew buffers 111 and sends the data of the 4 first deskew buffers 111 to the serializing unit 14 in parallel through the 4 communication links in 4 ways. The serializer 14 receives 4 paths of parallel data, converts the parallel data into single-bit data, and outputs the single-bit data.

On the basis of any of the above embodiments, the system on chip of the embodiments of the present application may further include a receiving unit. The following embodiments explain the structure and principle of the receiving unit in detail.

Fig. 4 is another schematic structural diagram of a system on chip according to an embodiment of the present application, and as shown in fig. 4, the system on chip further includes: a receiving unit 2. The receiving unit 2 includes: a plurality of second storage units 21 and a plurality of elastic buffer control units 22 connected to the respective second storage units 21, each of the second storage units including: the elastic buffer 211.

Alternatively, each elastic buffer control unit 22 and each elastic buffer 211 may correspond to each other one by one. Each elastic buffer control unit 22 and the corresponding elastic buffer 211 may be integrated in the same physical unit module.

Alternatively, the number of the second storage unit 21, the elastic buffer 211, and the elastic buffer control unit 22 may be consistent with the number of communication links. For example, if the system on chip supports N communication links, the numbers of the second storage unit 21, the elastic buffer 211, and the elastic buffer control unit 22 are all N, and each elastic buffer 211 and the corresponding elastic buffer control unit 22 are respectively used for processing data on one communication link. Wherein N may be an integer greater than 1.

Optionally, the elastic buffer 211 is used to store the received data. The elastic buffer control unit 22 is configured to adjust the alignment data in the received data of the elastic buffer 211 according to the data read/write speed of the receiving unit 2. Wherein receiving the data comprises: load data and alignment data, wherein the alignment data comprises a start identifier and an end identifier.

The meaning of the above load data and alignment data can be referred to the description in the foregoing sending unit 1, and is not described herein again.

After the computer device where the system on chip is located receives data from multiple communication links as a device for receiving data, that is, after receiving the received data, the elastic buffer control unit 22 corresponding to each communication link writes the received data on each communication link into the corresponding elastic buffer 211, and adjusts alignment data in the received data of the elastic buffer 211 according to the data read-write speed of the receiving unit 2. Wherein the adjusting of the alignment data may comprise: write new corresponding alignment data or delete existing alignment data in the elastic buffer 211, etc. For example, if the data reading speed of the receiving unit 2 is fast, the elastic buffer control unit 22 additionally writes one alignment data into the elastic buffer 211 after writing a preset amount of data into the elastic buffer 211. Illustratively, the alignment data may be, for example, one or more idle frames.

Referring to fig. 4, the receiving unit 2 may further include a plurality of deserializing units 27 connected to the elastic buffer control units 22 in a one-to-one correspondence, and after the receiving unit 2 receives the received data through the communication links, the received data is first input to the deserializing units 27 corresponding to the communication links, the deserializing units 27 convert the single-bit serial data into multi-bit parallel data, and the corresponding elastic buffer control units 22 collect the multi-bit parallel data into data in units of blocks and write the data into the elastic buffer 211. In which collecting multi-bit parallel data as data in units of blocks can improve transmission efficiency of data.

In this embodiment, the received data is stored in the elastic buffer, and the alignment data in the received data in the elastic buffer is adjusted according to the data read-write speed of the receiving unit, so that different communication links can achieve data alignment.

Fig. 5 is a schematic diagram of another structure of a system on chip according to an embodiment of the present application, and as shown in fig. 5, each second storage unit 21 further includes: a second de-skew buffer 212, the second de-skew buffer 212 being connected to the elastic buffer 211. Meanwhile, the receiving unit 2 further includes: the second deskew buffers 212 in the second memory units 21 are connected to the deskew control unit 23, respectively, in the deskew control unit 23.

Optionally, the second de-skew buffers 212 and the elastic buffers 211 may have a one-to-one correspondence, and each communication link has a corresponding second de-skew buffer 212 for reading and storing data from the elastic buffers 211.

Optionally, the second de-skew buffer 212 is used to read and store received data from the elastic buffer 211. The deskew control unit 23 is configured to recognize the start flag and the end flag of the alignment data in each second deskew buffer 212, and read the received data from each second deskew buffer 212 after recognizing the start flag and the end flag of the alignment data.

Alternatively, the second de-skew buffer 212 may read and store the received data from the elastic buffer 211 according to a particular policy. Specific strategies are illustrated in the following examples.

Alternatively, the deskew control unit 23 may control all the second deskew buffers 212 in the second storage unit 21 at the same time. Specifically, for each second deskew buffer 212, the deskew control unit 23 identifies a start flag and an end flag of the alignment data in the second deskew buffer 212, and if the start flag and the end flag of the alignment data are identified, indicating that the data in each second deskew buffer 212 is aligned, the deskew control unit 23 correspondingly reads the received data from each second deskew buffer 212. The deskew control unit 23 may then send the read received data to other module units in the receiving unit 2 for further analysis processing.

In this embodiment, a plurality of second deskew buffers and deskew control units are added in the receiving unit, the second deskew buffers read and store the received data from the elastic buffer, and the deskew control unit identifies the start identifier and the end identifier of the aligned data in each second deskew buffer, so that the read control of the second deskew buffers by the deskew control unit is realized, and further, the dynamic deskew correction inside the receiving side is realized.

As an alternative embodiment, read control of the second deskew cache may be facilitated by adding a read enable flag.

Optionally, the deskew control unit 23 is specifically configured to: when the alignment data in each second deskew cache 212 is identified to have the start identifier and the end identifier, the value of the read enable flag is adjusted, and when the value of the read enable flag is the second preset value, the received data is read from the second deskew cache 212.

The read enable flag may be set in the deskew control unit 23 or in the second deskew buffer 212, which is not specifically limited in this application.

When the deskew control unit 23 recognizes that the alignment data in each of the second deskew buffers 212 has the start flag and the end flag, the value of the read enable flag is adjusted. The skew control unit 23 reads the received data from the second deskew buffer 212 only if the value of the read enable flag is the second preset threshold.

For example, the read enable flag may be, for example, one bit of data, the value of the read enable flag may be 0 or 1, and the second preset threshold may be 1. When the value of the read enable flag is 0, indicating that it is currently low, then no read of the received data from the second deskew buffer 212 is allowed. When the value of the read enable flag is 1, indicating that it is currently a high value, then the received data is allowed to be read from the second deskew buffer 212.

In addition, when performing read control, read control may also be performed in conjunction with the depth information of the second deskew buffer 212. Specifically, when it is recognized that the alignment data in each second deskew cache 212 has a start identifier and an end identifier, and the depth information of each second deskew cache 212 is greater than a third preset threshold, the value of the read enable flag is adjusted, and when the value of the read enable flag is a second preset value, the received data is read from the second deskew cache 212.

In this embodiment, by adjusting the read enable flag, the deskew control unit can quickly determine whether to read data from the second deskew cache according to the value of the read enable flag, so that the control efficiency is high, and no additional resource is occupied while dynamic skew correction is realized.

As previously described, the second deskew buffer 212 may read and store received data from the elastic buffer 211 according to a particular policy. As an alternative embodiment, a plurality of load control units may be added to the receiving unit 2 to control the second de-skew buffer 212 to read and store the received data from the elastic buffer 211, that is, to perform write control of the second de-skew buffer 212. The following description will be specifically made.

Fig. 6 is a schematic diagram of another structure of a system on chip according to an embodiment of the present application, and as shown in fig. 6, on the basis of fig. 5, the receiving unit 2 further includes: a plurality of load control units 24. Each load control unit 24 is connected to an elastic buffer 211 and a second de-skew buffer 212.

Optionally, the load control units 24 may correspond to the second de-skew buffers 212 and the elastic buffers 211 one by one, each communication link has a corresponding load control unit 24, and the load control unit 24 is connected to the second de-skew buffers 212 and the elastic buffers 211 on the communication link, and is configured to perform write control on the second de-skew buffers 212.

Optionally, the load control unit 24 is configured to control the second de-skew buffer 212 to read and store the received data from the elastic buffer 211 when it is detected that the aligned data in the elastic buffer 211 has a start identifier and an end identifier, and the depth information of the second de-skew buffer 212 is smaller than a first preset threshold.

Wherein the depth information of the second deskew buffer 212 may be used to indicate the amount of data buffered in the second deskew buffer 212. In the case where the data stored in the second deskew buffer 212 is not empty, the depth information of the second deskew buffer 212 may be greater than a first preset threshold. The larger the depth is, the larger the data storage amount of the second deskew buffer 212 is, and the smaller the depth is, the smaller the data storage amount of the second deskew buffer 212 is.

The load control unit 24 may monitor data in the corresponding elastic buffer 211 in real time, if the aligned data in the elastic buffer 211 has a start identifier and an end identifier, which indicate that the data in the elastic buffer 211 is aligned, and the load control unit 24 determines whether the depth information of the second deskew buffer 212 is smaller than a first preset threshold, and if so, indicates that the free storage space of the second deskew buffer 212 is sufficient, the load control unit may control the corresponding second deskew buffer 212 to read and store the received data from the corresponding elastic buffer 211, thereby implementing dynamic write-in of the received data to the second deskew buffer 212, ensuring security of data write-in, and further ensuring dynamic read of subsequent data of the second deskew buffer 212 to implement dynamic deskew correction inside the receiving side.

As an alternative embodiment, the load control unit 24 may assist in write control of the second deskew buffer by adding a write enable flag.

Optionally, the load control unit 24 is specifically configured to: when detecting that the alignment data in the elastic buffer 211 has the start identifier and the end identifier, and the depth information of the second de-skew buffer 212 is smaller than the first preset threshold, adjusting the value of the write enable flag, and controlling the second de-skew buffer 212 to read and store the received data from the elastic buffer 211. Accordingly, the second deskew buffer 212 is specifically configured to: when the value of the write enable flag is a first preset value, the received data is read from the elastic buffer 211 and stored.

The write enable flag may be set in the unload control unit 24, or may be set in the second deskew buffer 212 or the elastic buffer 211, which is not specifically limited in this application.

When the load control unit 24 recognizes that the alignment data has the start flag and the end flag in the elastic buffer 211, the value of the write enable flag is adjusted. The second deskew buffer 212 is allowed to read and store received data from the elastic buffer 211 only if the write enable flag has a value of a second predetermined threshold.

For example, the write enable flag may be, for example, one bit of data, the value of the write enable flag may be 0 or 1, and the second preset threshold may be 1. When the value of the write enable flag is 0, indicating that it is currently a low value, the second deskew buffer 212 is not allowed to read and store received data from the elastic buffer 211. When the write enable flag has a value of 1, indicating that it is currently high, the second deskew buffer 212 is allowed to read and store received data from the elastic buffer 211.

In this embodiment, by adjusting the write enable flag, the load control unit may quickly determine whether to allow the second deskew buffer to read and store the received data from the elastic buffer according to the value of the write enable flag, so that the control efficiency is high, and no additional resource is occupied while the dynamic skew correction is implemented.

As an alternative embodiment, the load control unit 24 may be further configured to adjust the alignment symbol in the second deskew buffer 212, in addition to implementing the above-described write control on the second deskew buffer 212, so as to further improve the data alignment effect. Whether to enable the function of the load control unit 24 to adjust the alignment symbols in the second deskew buffer 212 may be achieved by adding an ordered set control unit to the receiving units. The following description will be specifically made.

Fig. 7 is a schematic structural diagram of a system on chip according to an embodiment of the present application, and as shown in fig. 7, on the basis of fig. 6, the receiving unit 2 further includes: a plurality of ordered set control units 25. Each of the order-set control units 25 is connected to the deskew control unit 23 and the load control unit 24, respectively.

Optionally, the ordered set control units 25 and the load control units 24 may be in one-to-one correspondence, each communication link has a corresponding ordered set control unit 25, the ordered set control unit 25 is connected to the load control unit 24 and the deskew control unit 23 on the communication link, and the alignment symbol adjustment function of the load control unit 24 is controlled by interaction with the load control unit 24 and the deskew control unit 23.

The ordered-set control unit 25 is configured to receive the ordered-set control instruction of the deskew control unit 23, and accordingly send an ordered-set control signal to the load control unit 24, where the ordered-set control signal is used to indicate whether the load control unit 24 is allowed to write the alignment symbol to the second deskew buffer 212.

Correspondingly, the load control unit 24 is further configured to write an alignment symbol to the second deskew buffer 212 when the ordered-set control signal indicates that the load control unit 24 is allowed to write the alignment symbol to the second deskew buffer 212, where the alignment symbol includes: the ordered set symbols and/or idle frames may be ignored.

It should be understood that the above-mentioned negligible ordered set refers to the aforementioned SKP ordered set, and correspondingly, the above-mentioned negligible ordered set corresponds to the aforementioned SKP symbol. As previously described, the SKP ordered set may contain 4 SKP symbols, 12 SKPs, or 16 SKP symbols. In this embodiment, the SKP symbol as the alignment symbol may be one or more symbols in the SKP ordered set. For example, assuming that the SKP ordered set in the alignment data of the received data includes 12 SKP symbols, the number of written SKP symbols in this embodiment may be 1, 2, and so on.

In addition, the alignment symbol may also be the idle frame.

Optionally, the deskew control unit 23 may generate an ordered set control instruction according to configuration information of a user or preset settings, and send the ordered set control instruction to the ordered set control unit 25. The ordered set control unit 25 parses the ordered set control instruction, and if the ordered set control instruction indicates permission of the load control unit 24 to write the alignment symbol to the second deskew buffer 212, the ordered set control unit 25 sends an ordered set control signal to the load control unit 24 indicating permission of the load control unit 24 to write the alignment symbol to the second deskew buffer 212. If the ordered-set control instruction indicates that the load control unit 24 is not allowed to write the alignment symbol to the second deskew buffer 212, the ordered-set control unit 25 sends an ordered-set control signal to the load control unit 24 indicating that the load control unit 24 is not allowed to write the alignment symbol to the second deskew buffer 212, or the ordered-set control unit 25 may not send a signal to the load control unit 24, and when the ordered-set control unit 25 may not send a signal to the load control unit 24, it indicates by default that the load control unit 24 is not allowed to write the alignment symbol to the second deskew buffer 212.

After the load control unit 24 receives the ordered set control signal that allows it to write the alignment symbols into the second de-skew buffer 212, the alignment symbols may be dynamically written into the second de-skew buffer 212 according to the speed at which the second de-skew buffer 212 reads the received data from the elastic buffer 211, the amount of the alignment data in the second de-skew buffer 212, and so on. For example, if the data reading speed of the second deskew cache 212 is fast and there are fewer SKP symbols in the SKP ordered set in the second deskew cache 212, the load control unit 24 may insert SKP symbols into the second deskew cache 212 to further ensure the effect of data alignment.

In this embodiment, the sequential set control unit may flexibly control the on/off of the alignment symbol writing function of the load control unit, and when the alignment symbol writing function of the load control unit is on, the load control unit may write the alignment symbol into the second deskew cache, so as to further ensure the data alignment effect.

With continuing reference to fig. 7, as an alternative implementation, the receiving unit 2 further includes: a second user logic unit 26. The second user logic unit 26 is connected to the deskew control unit 23.

The deskew control unit 23 is further configured to control attribute information of each second deskew buffer 212 according to the configuration information sent by the second user logic unit 26, where the attribute information includes at least one of the following: cache size, data processing bit width.

In addition, the second user logic unit 26 may also receive configuration information input by a user, the configuration information being used to indicate whether the load control unit 24 is allowed to write the alignment symbol to the second deskew buffer 212, the second user logic unit sending the configuration information to the deskew control unit 23, and the deskew control unit 23 controlling the load control unit to turn on or off the above-mentioned functions accordingly using the method of the foregoing embodiment.

Alternatively, the second user logic unit 26 may obtain preset configuration information and send the configuration information to the deskew control unit to control the attribute information of the second deskew cache 212. The configuration information may be input in advance by a user through an input interface provided by the computer device and stored in the second user logic unit 26, and the second user logic unit 26 correspondingly sends the configuration information to the deskew control unit 23.

By setting the second user logic unit, flexible configuration of each second deskew cache can be realized.

As an alternative embodiment, the deskew control unit 23 may also implement recovery of the communication link and the like through determination of data in the second deskew buffer 212.

Optionally, the deskew control unit 23 is further configured to: and determining whether the data transmission link is abnormal or not by using the start identifier and the end identifier of the alignment data in each second deskew cache 212 as a judgment basis, and performing retraining processing, reinitialization processing or link recovery processing on the data transmission link when the data transmission link is abnormal.

It should be understood that the data transmission links described above have the same meaning as the communication links described in the previous embodiments.

In one example, all data communication links may be reinitialized if no start flag is present in the alignment data in the second deskew buffer 212 on all data transmission links.

In another example, if no start flag is present in the aligned data in the second deskew buffer 212 on a data transmission link, the data transmission link may be retrained or link restored.

In this embodiment, the fast recovery of the communication link may be implemented by using the deskew control unit to determine the aligned data in the second deskew buffer.

Based on the same inventive concept, the embodiment of the present application further provides a data processing method corresponding to the foregoing system on chip, and since the principle of solving the problem of the data processing method in the embodiment of the present application is similar to that of the foregoing system on chip in the embodiment of the present application, the implementation of the data processing method may refer to the implementation of the foregoing device side, and repeated details are not described again.

To facilitate understanding of the methods described herein, the first control unit in the sending unit to which the following method embodiments relate includes the alignment control unit, the first user logic unit, the serialization unit, etc. in the preceding device embodiments. Correspondingly, each first storage unit is connected with the first control unit. It is to be understood that this first control unit comprises all the unit modules on the transmitting unit for implementing the control function. In addition, for the first control unit, the alignment control unit, the first user logic unit, the serialization unit, and the like included therein may be coupled to or independently disposed in a physical structure, which is not specifically limited in this application.

In addition, in order to facilitate understanding of the method described in the present application, the second control unit in the receiving unit according to the following method embodiment includes an elastic buffer control unit, a de-skew control unit, a load control unit, an ordered set control unit, a second user logic unit, and the like in the foregoing device embodiment. Correspondingly, each second storage unit is connected with the second control unit. It is to be understood that this second control unit comprises all the unit modules on the receiving unit for implementing the control functions. In addition, for the second control unit, the elastic buffer control unit, the de-skew control unit, the load control unit, the ordered set control unit, the second user logic unit, and the like included therein may be coupled in physical structure, or may be independently disposed, which is not specifically limited in this application.

Fig. 8 is a schematic flowchart of a data processing method according to an embodiment of the present application, where the method is applied to the foregoing system on chip, and the system on chip includes: a transmitting unit, the transmitting unit comprising: the device comprises a plurality of first storage units and a first control unit, wherein each first storage unit is connected with the first control unit. The first storage unit includes: a first de-skew buffer to store data to be transmitted, the data to be transmitted comprising: load data and alignment data, wherein the alignment data comprises a start identifier and an end identifier. As shown in fig. 8, the method includes:

s801, the first control unit identifies a start identifier and an end identifier of the alignment data in each first deskew buffer.

S802, after recognizing the start mark and the end mark of the alignment data, the first control unit reads and sends the data to be transmitted from each first deskew buffer.

As an optional implementation, the system on chip further includes: a receiving unit; the receiving unit includes: a plurality of second storage units and a second control unit, the second storage unit including: elastic caching; the elastic buffer is used for storing the received data; the method further comprises the following steps:

the second control unit adjusts alignment data in the received data of the elastic cache according to the data read-write speed of the receiving unit, wherein the received data comprises: the device comprises load data and alignment data, wherein the alignment data comprises a starting mark and an ending mark.

As an optional implementation, each of the second storage units further includes: a second de-skew buffer connected to the elastic buffer, the second de-skew buffer configured to read and store received data from the elastic buffer; the method further comprises the following steps:

As an optional implementation, the method further comprises:

As an optional implementation manner, when it is detected that the alignment data in the elastic buffer has a start identifier and an end identifier, and the depth information of the second de-skew buffer is smaller than a first preset threshold, the second control unit controls the second de-skew buffer to read and store the received data from the elastic buffer, including:

and when detecting that the alignment data in the elastic cache has a start identifier and an end identifier and the depth information of the second de-skew cache is smaller than the first preset threshold, the second control unit adjusts the value of a write enable flag and controls the second de-skew cache to read and store the received data from the elastic cache, so that when the value of the write enable flag in the second de-skew cache is a second preset value, the second control unit reads and stores the received data from the elastic cache.

As an optional implementation manner, the second control unit identifies a start identifier and an end identifier of the alignment data in each second deskew buffer, and reads the received data from each second deskew buffer after identifying the start identifier and the end identifier of the alignment data, including:

As an optional implementation, the method further comprises:

Specifically, the ordered set control unit in the second control unit receives the ordered set control instruction of the deskew control unit, and correspondingly sends an ordered set control signal to the load control unit, where the ordered set control signal is used to indicate whether the load control unit is allowed to write an alignment symbol into the second deskew cache. After receiving the ordered set control signal, the load control unit writes an alignment symbol into the second deskew cache if the ordered set control signal indicates that the load control unit is allowed to write the alignment symbol into the second deskew cache.

As an optional implementation, the method further comprises:

As an optional implementation manner, the first control unit identifies a start identifier and an end identifier of the alignment data in each first deskew buffer, and reads and sends the data to be transmitted from each first deskew buffer after identifying the start identifier and the end identifier of the alignment data, including:

As an optional implementation, the method further comprises:

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.

Claims

1. A system on a chip, comprising: a transmitting unit; the transmission unit includes: the device comprises a plurality of first storage units and an alignment control unit, wherein each first storage unit is respectively connected with the alignment control unit; the first storage unit includes: a first de-skew cache; wherein the content of the first and second substances,

the first de-skew buffer is configured to store data to be transmitted, where the data to be transmitted includes: load data and alignment data, wherein the alignment data comprises a starting identifier and an ending identifier;

2. The system-on-chip as recited in claim 1, further comprising: a receiving unit;

3. The system on a chip of claim 2, wherein each of the second storage units further comprises: a second de-skew cache coupled to the elastic cache;

4. The system on a chip of claim 3, wherein the receiving unit further comprises: a plurality of load control units; each load control unit is respectively connected with the elastic buffer and the second de-deflection buffer;

5. The system on chip of claim 4, wherein the load control unit is specifically configured to: when detecting that the alignment data in the elastic cache has a start identifier and an end identifier and the depth information of the second de-skew cache is smaller than the first preset threshold, adjusting the value of a write enable flag, and controlling the second de-skew cache to read and store the received data from the elastic cache;

6. The system-on-chip as recited in claim 3, wherein the deskew control unit is specifically configured to: and when the alignment data in each second de-skew cache is identified to have a start identifier and an end identifier, adjusting the value of a read enable flag, and when the value of the read enable flag is a second preset value, reading the received data from each second de-skew cache.

7. The system-on-chip as recited in claim 6, wherein the deskew control unit is further configured to: and determining whether the data transmission link is abnormal or not by taking the initial mark and the end mark of the aligned data in each second deskew cache as a judgment basis, and performing retraining processing, reinitialization processing or link recovery processing on the data transmission link when the data transmission link is abnormal.

8. The system on a chip as claimed in claim 4, wherein the receiving unit further comprises: a plurality of ordered set control units; each ordered set control unit is respectively connected with the de-deflection control unit and the load control unit;

the load control unit is further to write an alignment symbol to the second deskew buffer when the ordered set control signal indicates that the load control unit is allowed to write alignment symbols to the second deskew buffer, the alignment symbol comprising: the ordered set symbols and/or idle frames may be ignored.

9. The system on a chip of any of claims 3-8, wherein the receiving unit further comprises: a second user logic unit; the second user logic unit is connected with the de-skew control unit;

10. The system-on-chip as recited in claim 1, wherein the alignment control unit is specifically configured to: and after the initial identification and the end identification of the aligned data in each first de-skew cache are identified, if the depth information of each first de-skew cache is greater than a second preset threshold, reading and sending the data to be transmitted from each first de-skew cache.

11. The system on a chip of claim 1, wherein the sending unit further comprises: a first user logic unit; the first user logic unit is connected with each first de-skew cache;

12. A data processing method, applied to a system on chip, the system on chip comprising: a transmitting unit, the transmitting unit comprising: the device comprises a plurality of first storage units and a first control unit, wherein each first storage unit is connected with the first control unit; the first storage unit includes: a first de-skew buffer to store data to be transmitted, the data to be transmitted comprising: load data and alignment data, wherein the alignment data comprises a starting identifier and an ending identifier; the method comprises the following steps:

the first control unit identifies the start mark and the end mark of the alignment data in each first de-skew buffer, and reads and sends the data to be transmitted from each first de-skew buffer after identifying the start mark and the end mark of the alignment data.

13. A computer device comprising the system-on-chip of any one of claims 1-11.