KR100678521B1 - Apparatus and method for coding of irregular low density parity check code - Google Patents

Abstract

The present invention relates to an apparatus and method for encoding a non-uniform low density parity check code. Specifically, in order to reduce encoding processing delay time, an element of each matrix has a non-binary value defined as a cyclic matrix, and includes a lower triangular matrix. An apparatus and method for encoding a non-uniform low density parity check code using a parity check matrix composed of six partial matrices.

According to the method of encoding a non-uniform low density parity check code according to the present invention, a parity check matrix is composed of a plurality of partial matrices having non-binary values in which elements of each matrix are defined as cyclic matrices, and the information bits are parallelized in vector units. Create an input vector. Then, a first parity vector is generated from a plurality of intermediate vectors generated based on the plurality of partial matrices, and a second parity vector is generated based on the generated first parity vector and the generated plurality of intermediate vectors. do. At this time, one of the intermediate vectors for obtaining the first parity vector or the second parity vector is generated according to the input value by the time division sharing structure.

Error Correction Code, LDPC, Non-Uniform, Non-Binary, Vector, Recursive Matrix, Parity Check Matrix

Description

Non-uniform low density parity check code encoding apparatus and method {APPARATUS AND METHOD FOR CODING OF IRREGULAR LOW DENSITY PARITY CHECK CODE}

1 is a diagram showing an approximate lower triangular matrix of a parity check matrix to which the present invention is applied.

FIG. 2 is a diagram illustrating a non-binary low density parity check matrix H formed of a 4x4 unit partial matrix.

3 is a diagram illustrating a configuration of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

4 is a diagram illustrating a parity check matrix memory configuration of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

5 is a diagram illustrating an operation timing of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

The present invention relates to an apparatus and method for encoding low density parity check codes (hereinafter referred to as 'LDPC'). In particular, each row and column has a non-uniform number in which the number of elements other than '0' is not constant. LDPC encoding apparatus and method.

Recently, as the demand for broadband multimedia services is increased in a wireless communication system, research and development on high-efficiency high-speed data transmission technology have been actively conducted.

The LDPC coding method is a technique for improving data transmission efficiency by effectively correcting transmission data error caused by signal distortion generated when high-speed broadband data is transmitted through a wireless channel. The fourth generation mobile communication system and satellite communication system, It is being researched and developed in high speed wireless LAN.

The LDPC coding scheme is a block coding scheme that encodes using a matrix for encoding before transmitting information bits. The LDPC coding scheme is a linear block code in which most elements of a parity check matrix are zero. The element of "1" is very small, that is, most of the elements use a coding matrix having a value of "0".

Since the parity check matrix of LDPC codes is very small, it is possible to iterative decoding using sum-product algorithm even in very large block sizes. If the block size is very large, it is close to Shannon's channel capacity limit like turbo code. To show performance. In particular, the non-uniform LDPC code shows the closest performance to Shannon limit. There is a non-uniform LDPC code presently approaching the Shannon limit within 0.0045 dB of length 107. The LDPC code has better performance in a larger block than the turbo code, no error floor, low decoding complexity, and high speed decoding by parallel processing.

In this way, the LDPC coding scheme uses a parity check matrix, H, which is composed of rows and columns with a very small amount of “1” and a very sparse matrix. do.

The basic concept of such LDPC is D.J. MacKay, “Good error-correction codes based on very sparse matrices,” IEEE Trans. On Information Theory, vol. 45, no 2, pp. 399-431, 1999 and a description of the encoding method is described in T. Richardson, R. Urbanke, “Efficient encoding of low density parity check codes,” IEEE Trans. On Information theory, vol 47, no. 2, pp. 638-656, 2001.

Meanwhile, in the case of an error correction code used in a wireless communication system, various coding rates are supported to support various data rates according to a wireless channel environment. In the case of the low density parity check code, there are a method of using puncturing as a method of supporting various code rates and a method of using different parity check matrices for each code rate.

If you use different parity check matrices with optimized performance for each code rate, especially for non-uniform low density parity check codes where the number of non-zero elements in each row and column is not uniform, the encoding processing delay time is high. The production of the encoder also has a difficult problem.

It is an object of the present invention to provide an apparatus and method for encoding a non-uniform low density parity code that supports various types of coding rates while improving hardware efficiency and reducing encoding processing delay time.

In order to solve this problem, the present invention is provided to an apparatus and method for encoding a non-uniform low density parity check code.

Non-uniform low density parity check code encoding apparatus according to an aspect of the present invention,

Non-uniform low-density parity check that encodes information bits using a parity check matrix, where the parity check matrix consists of a plurality of submatrices with a small number of 1s in the element and a non-uniform number of entries into the rows and columns. A code encoding device,

An input bit parallelizer for generating an input vector by parallelizing the input information bits;

A p ₁ vector operator for generating a first parity vector from the plurality of intermediate vectors generated based on the plurality of partial matrices; A t vector operator that generates a second parity vector based on the generated first parity vector and a plurality of intermediate vectors, and generates a first intermediate vector or the second parity vector among the plurality of intermediate vectors by a time division shared structure. ; And a first selector for encoding the input vectors based on the generated first and second parity vectors.

In this case, the plurality of submatrices are A and T matrices in which the row or column size is not 1, where the T matrix is a lower triangular matrix, and the B, C, D and E matrices having a row or column size of 1 are obtained. Element of each matrix from non-binary values defined by the circulant matrix,

The plurality of intermediate vectors include a, t, b, c, d, and e vectors, each generated based on the A, T, B, C, D, and E matrices, and the first intermediate vector is a t vector. .

The t vector operator has a time division sharing structure that generates the t vector when the a vector is input and generates the second parity vector when the sum of the a vector and the b vector is input.

Non-uniform low density parity check code encoding method according to another aspect of the present invention,

A method of encoding a non-uniform low density parity check code using a parity check matrix, wherein the parity check matrix is a matrix having a small number of 1's in an element and a non-uniform number of things entering a row and a column.

a) constructing the parity check matrix into a plurality of partial matrices in which elements of each matrix have non-binary values defined as cyclic matrices; b) parallelizing the information bits in vector units to generate an input vector; c) generating a first parity vector from a plurality of intermediate vectors generated based on the plurality of partial matrices; d) generating a second parity vector based on the generated first parity vector and the generated plurality of intermediate vectors; And e) outputting codeword bits to the generated first and second parity vectors.

Wherein the plurality of partial matrices comprise A and T matrices in which the row or column size is not one, where the T matrix is a lower triangular matrix, wherein the B, C, D, and E matrices have a row or column size of one. ,

The plurality of intermediate vectors include a, t, b, c, d and e vectors, respectively generated based on the A, T, B, C, D and E matrices.

And c) comprises: generating a vector from the A matrix and the input vector; Generating a t vector from the generated a vector and the T matrix; Generating an e vector from the generated t vector and the E matrix; Generating a c vector from the input vector and the C matrix; And generating a first parity vector from a product of the sum of the e vector and the c vector and the inverse of the circulant matrix, the t vector or the second parity vector according to a vector value input by a time division shared structure. Is generated. The a and t vectors are also processed simultaneously with a predetermined start delay.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

An apparatus and method for encoding a non-uniform low density parity code according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, the parity check matrix applied in the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a diagram illustrating an approximate lower triangular matrix of a low density parity check matrix.

As shown in Fig. 1, for the low-density parity check matrix H, a lower triangular matrix having an upper triangular region of '0' can be obtained by using row and column substitution and Gaussian elimination. Parity check matrices are represented by partial matrices (A, B, C, D, E, T), and the parity codewords are converted into parity codewords according to the operations of Equations 1 to 9 described below in a more efficient manner. Get from

FIG. 2 is a diagram illustrating a non-binary low density parity check matrix H formed of a 4x4 unit partial matrix.

을 원소로 갖는 비 이진의 경우, 순환 행렬을 단위 부분 행렬로 정의하여 패리티 검사 행렬을 표현할 때 각 원소의 값은 단위 부분 행렬의 순환 값이다.As shown in Fig. 2, each element of the parity check matrix H is, for example, a 4x4 circular matrix.

In the case of non-binary having as element, when the parity check matrix is defined by defining the circulant matrix as the unit submatrix, the value of each element is the cyclic value of the unit submatrix.

When the low density parity check matrix H is expressed using the circulant matrix as the unit matrix, the matrix-vector operation may be implemented in the form of a simple shift register, and the encoding process may be processed in units of the size of the unit matrix. It is more advantageous for real time processing.

Also, even in the decoding apparatus, when the message transfer decoding method is used, parallelization of each bit and check node message to a unit matrix size is simplified, which is advantageous for high-speed processing.

In the present invention, each partial matrix is formed according to the parity code arithmetic process of Equations 1 to 9 described below, and the size of the unit partial circulant matrix is defined as 32 × 32 matrix.

Next, a non-uniform low density parity code encoding apparatus according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a diagram illustrating a configuration of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

As shown in Fig. 3, a non-uniform low density parity code encoding device includes an input bit parallelizer 301, an input vector buffer 302, a vector operator 303, a vector buffer 304, and a matrix memory 305. ), t vector operator 306, t / p ₂ vector buffer 307, T matrix memory 308, e vector operator 309, c vector operator 310, p ₁ vector operator 311 and b vector The operator 312 is included.

The input bit parallelizer 301 generates an input vector by parallelizing an information bit string input to an encoding device in units of 1 × 32 part vectors. Hereinafter all matrices, or vectors, are processed in 32-bit units.

The a vector operator 302 generates an a vector by accumulating the input vectors corresponding to positions of elements other than '0' of each row in units of rows of the matrix A by element values. At this time, the length of the a vector is the row length of the A matrix. That is, the a vector calculation process is shown in Equation 1.

t vector operator 306 generates a t vector in a manner similar to the a vector, where the length of the vector is the row length of the T matrix. In this case, the difference from the vector operator 302 is that a backward substitution method is used after the first t vector t ₀ value is obtained from the inverse of a ₀ according to the form of the lower matrix T matrix. This is obtained by accumulating a value obtained by inverting a vector by the diagonal element value of the T matrix and by cyclically moving the previous t vector by the element value of the T matrix below the diagonal element. That is, the t vector calculation process is shown in Equation 2.

The e vector operator 309 cyclically accumulates the t vector obtained from the t vector operator 306 by the element value of the E matrix according to Equation 3 to generate the e vector. That is, the e-vector calculation process is shown in Equation 3.

The c vector operator 310 cyclically accumulates the input vectors by the element values of the C matrix to generate the c vector. That is, the c vector operation process is shown in Equation 4.

의 곱으로 첫 번째 패리티 부분 벡터 p₁을 생성한다. 즉, p₁ 벡터 연산 과정은 수학식 5를 통해 수학식 6과 같이 나타난다.p ₁ vector operator 311 is the sum of two 1 × 32 vectors (e and c vectors) and an inverse of size 32 × 32

Create the first parity partial vector p ₁ with the product of. That is, the p ₁ vector operation process is represented by Equation 6 through Equation 5.

Here, d represents the d vector, and the d vector is generated as the sum of the e vector and the c vector.

The b vector operator 312 generates a b vector by circularly shifting p ₁ by an element value from the first parity partial vector p ₁ at a position other than '0' of the B matrix. That is, the operation of the b vector is as shown in Equation (7).

Meanwhile, the sum of the b vector and the a vector is used as an input for obtaining the second parity vector p ₂ , and the second parity vector p ₂ is obtained through the t vector operator 306. This is represented by Equations 8 and 9.

At this time, when the obtained t vectors using the equations (2) and the similarity of the equation (9) using a vector and, if obtained p ₂ vector by making the sum of a vector and the b vector type t vector computing unit 306, The portion (indicated by dashed lines) including the t vector buffer 307, the T vector memory 308, and the selector 314 has a time division shared structure.

In addition, an apparatus for encoding a non-uniform low density parity check code according to an embodiment of the present invention may include three types of internal memories, namely, an input vector buffer 302, a vector buffer 304, and a t / p ₂ vector buffer 307. It is included.

The input vector buffer 302 stores the parallelized input vector from the input bit parallelizer in 32 bit partial vector units. At this time, the input vector buffer 302 stores the input bit sequence in parallel by 32 bits because positions of elements other than '0' may exist in any order in each row of the A matrix used when calculating a vector. do.

a vector buffer 304 stores a vector. In this case, the a vector buffer 304 is a value input when the t vector and the p ₂ vector are obtained, and are required because the a vector must be stored because these two vectors are calculated and obtained at a time interval.

The t / P ₂ vector buffer 307 stores the t vector and the parity vector p ₂ . At this time, the t / p ₂ vector buffer 307 inputs a t (or p ₂ ) vector element equal to or less than n−1 to obtain an n th t (or P ₂ ) vector element according to the T matrix structure in the form of a triangle below. This is necessary because the output of the operator 307 of the t vector must be stored.

In addition, the apparatus for encoding a non-uniform low density parity check code according to an embodiment of the present invention further includes adders 313 and 315 and selectors 314 and 316.

The adder 313 inputs the sum of the a vector and the b vector to the t vector operator 306, and outputs the sum of the a vector and the b vector to obtain a p ₂ vector.

The selector 314 selects whether to input the a vector to the t vector operator 306 or the sum of the a vector and the b vector, depending on whether to obtain the t vector or the p ₂ vector, and then to the t vector operator 306. Output

The adder 315 sums the e vector and the c vector and outputs the sum to the p ₁ vector operator 311.

The selector 316 selects a corresponding vector from a p ₁ vector output from the p ₁ vector operator 311, a p ₂ vector output from the t vector operator 306, and an input vector output from the input bit parallelizer 301. Output the codeword.

In addition, the encoding apparatus of the non-uniform low density parity check code according to the embodiment of the present invention further includes an A matrix memory 305 and a T matrix memory 308.

The A matrix memory 305 stores an A matrix.

T matrix memory 308 stores a T matrix.

The A matrix memory 305 and the T matrix memory 308 will be described in detail with reference to FIG. 4.

4 is a diagram illustrating a parity check matrix memory configuration of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

As shown in Fig. 4, first, when storing the parity check matrix by dividing it into six partial matrices, element values of the parity check matrix can be stored or a calculation (cyclic and cumulative accumulation at a predetermined position) can be used.

In the embodiment of the present invention, as described above, the A matrix and the T matrix are respectively stored in the A matrix memory 305 and the T matrix memory 308, and the B, C, D, and E matrices except the A matrix and the T matrix are Since the size of a row or column is 1, a method of configuring an operator according to each coding rate is used by using a method of defining an operation without using a memory method.

On the other hand, in the case of the uniform low density parity code, since the weight of each row is constant, the elements of the vector are obtained by reading the column position and the cyclic value of the row unit by a certain number of weights, but the nonuniform low density parity as in the embodiment of the present invention. In the case of the sign, the weight of the row unit is not constant. Therefore, in the case of the A matrix and the T matrix, since both the a vector operator 303 or the t vector operator 306 operate in a row unit, the A matrix memory 305 and the T matrix memory 308 are each '0' in a row unit. It consists of a memory that stores the number of non-elements (row weights) and a memory that stores the position and cyclic values of non-zero elements of a row.

Therefore, to obtain the elements of the a and t or p ₂ vectors for each row, the desired row weight is read from the memory that stores the non-zero number of elements, and the weight is stored in the memory that stores the column positions and cycles. Read the position and the cyclic value of the column by the number of times to get the element of the desired vector.

In order to support various code rates, the structure of A and T matrices is continuously stored for each code rate, and the start address of each code rate is stored and stored in a separate ROM table, and the B, C, The D and E matrices select and use the output of the operator defined for each coding rate.

5 is a diagram illustrating an operation timing of an encoding apparatus of a non-uniform low density parity code according to an embodiment of the present invention.

As shown in FIG. 5, the rest of the vector operators have a minimum operation delay except for obtaining a t vector and a p ₂ vector which are not parallelized in order to minimize encoding processing delay time while increasing hardware efficiency of the encoding apparatus.

The t vector and the p ₂ vector have a time-sharing shared structure to reduce hardware size by using similarity using the triangular matrix T below.

For the a vector operator 303 and the t vector operator 306, the t vector is obtained through the a vector, but since the T matrix is the lower triangular matrix, the input needed to obtain the n th element t _n is a _n and t _m ( m <n). Accordingly, as shown in FIG. 5, the t vector operation 306 may be operated after a predetermined delay time from the operation time of the a vector operator 303.

If the T matrix does not have the triangular matrix characteristic below, the positions of the elements other than '0' of each row of the T matrix may be randomly defined, and thus the t vector may be calculated after the a vector operation is completed.

The difference between the start point of operation of the a vector operator 303 and the t vector operator 306 is related to the operation speed of the two operators 303 and 306.

t vector computing unit 306 n it requires a _n inputs to obtain a second element t _n, but is in a particular time t vector computing unit 306 may ahead of the operating speed of a vector arithmetic unit (303), A matrix and the T Depending on the number and distribution of non-zero elements in the matrix, if two operators 303, 306 start at the same time, or if the t vector operator 306 starts without sufficient delay, it needs to obtain the _nth element t _n . It happens that a _n input does not arrive. Therefore, in the case of the non-uniform low density parity code, since the start delay time between the a vector operator 303 and the t vector operator 306 required for each coding rate is different, it is necessary to control accordingly.

As described above, according to an embodiment of the present invention, the non-binary low density parity check matrix is composed of six partial matrices including lower triangular matrices in order to reduce encoding processing delay time, and the elements of each matrix are defined as cyclic matrices. It has a non-binary value and supports hardware parity check matrix according to various code rates.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, encoding time of a nonuniform low density parity check code can be minimized by operating a vector and t vector almost simultaneously while improving hardware efficiency through a time division structure of a t vector and a p ₂ vector. Can be. In addition, by defining and using several types of parity check matrices, multiple coding rates can be supported.

Claims (22)

Non-uniform low-density parity check that encodes information bits using a parity check matrix, where the parity check matrix consists of a plurality of submatrices with a small number of 1s in the element and a non-uniform number of entries into the rows and columns. In the encoding device of a code, An input bit parallelizer for generating an input vector by parallelizing the input information bits; A p ₁ vector operator for generating a first parity vector from the plurality of intermediate vectors generated based on the plurality of partial matrices; A t vector operator that generates a second parity vector based on the generated first parity vector and a plurality of intermediate vectors, and generates a first intermediate vector or the second parity vector among the plurality of intermediate vectors by a time division shared structure. ; And A first selector for encoding the input vectors based on the generated first and second parity vectors Non-uniform low density parity check code encoding apparatus comprising a. The method of claim 1, The plurality of submatrices, A and T matrices where the size of the row or column is not 1, where the T matrix is a lower triangular matrix, a non-binary that includes the B, C, D, and E matrices where the size of the row or column is 1; An encoding device of a non-uniform low density parity check code in which elements of each matrix are formed from values. The method of claim 2, Wherein the plurality of intermediate vectors comprises a, t, b, c, d and e vectors, respectively generated based on the A, T, B, C, D and E matrices, And encoding the non-uniform low density parity check code as the first intermediate vector. The method of claim 3, And the t vector operator generates the t vector when the a vector is input and generates the second parity vector when the sum of the a vector and the b vector is input. The method of claim 4, wherein An a vector operator configured to cyclically accumulate the input vectors corresponding to positions of non-zero elements of each row in units of rows of the matrix A by an element value; T vector is generated by accumulating a value of the reverse vector of the a vector by the diagonal element value of the T matrix and a value circulating the previous t vector by the element value of the T matrix under the diagonal element, and generating the vector vector A t vector operator for generating a second parity vector based on the b vector; An e vector operator for cyclically accumulating the t vector by an element value of the E matrix to generate an e vector; A c vector operator configured to cyclically accumulate the input vectors by an element value of the C matrix to generate a c vector; And A b vector operator that generates a b vector by circularly shifting the first parity vector by an element value at a nonzero element of the B matrix. Non-uniform low density parity check code encoding apparatus comprising a. The method of claim 5, And a non-uniform low density parity check code for operating the t vector operator after a predetermined delay time from an operation time point of the a vector operator. The method of claim 5, An A matrix memory storing the A matrix; And T matrix memory storing the T matrix that is the lower triangular matrix Non-uniform low density parity check code encoding apparatus further comprising. The method of claim 7, wherein Each of the A matrix memory and the T matrix memory, A first memory for storing a weight of a row from each of the A and T matrices, wherein the weight of the row is the number of nonzero elements in a row unit; And A second memory for storing the position and the cyclic value of the non-zero column of the row unit from each of the A matrix and the T matrix Non-uniform low density parity check code encoding apparatus comprising a. The method of claim 7, wherein An input vector buffer unit for storing the input vector in units of 32-bit partial vectors; A vector buffer unit for storing the a vector; And T / p ₂ vector buffer unit for storing the t vector and the second parity vector Non-uniform low density parity check code encoding apparatus further comprising. The method of claim 9, A second selector for selecting the vector a or the sum of the vector a and the vector b as the input of the vector t Non-uniform low density parity check code encoding apparatus further comprising. The method according to any one of claims 2 to 10, And the cyclic matrix is a 32 × 32 matrix. In the method of encoding a non-uniform low density parity check code using a parity check matrix, wherein the parity check matrix is a matrix having a small number of 1's in an element and a non-uniform number of things entering a row and a column. , a) constructing the parity check matrix into a plurality of partial matrices in which elements of each matrix have non-binary values defined as cyclic matrices; b) parallelizing the information bits in vector units to generate an input vector; c) generating a first parity vector from a plurality of intermediate vectors generated based on the plurality of partial matrices; d) generating a second parity vector based on the generated first parity vector and the generated plurality of intermediate vectors; And e) encoding the input bits based on the generated first and second parity vectors Non-uniform low density parity check code encoding method comprising a. The method of claim 12, Wherein the plurality of partial matrices comprise A and T matrices in which the size of the row or column is not 1, where the T matrix is a lower triangular matrix, wherein the B, C, D, and E matrices are 1 or 2 in size; And a plurality of intermediate vectors comprising a, t, b, c, d and e vectors respectively generated based on A, T, B, C, D and E matrices. The method of claim 13, Step c) is Generating a vector from the A matrix and the input vector; Generating a t vector from the generated a vector and the T matrix; Generating an e vector from the generated t vector and the E matrix; Generating a c vector from the input vector and the C matrix; And Generating a first parity vector from a product of the sum of the e and c vectors and the inverse of the circulant matrix Non-uniform low density parity check code encoding method comprising a. The method of claim 14, In step d), a non-uniform low density parity check code encoding method generates a second parity vector from a sum of the generated first parity vector, the b vector generated from the B matrix, and the a vector. The method of claim 15, And a t vector or a second parity vector is generated according to a vector value input by a time division shared structure. The method of claim 14, And a vector and a vector are processed at the same time with a predetermined start delay. The method of claim 14, Storing the parallelized input vector in 32-bit vector units; And Storing the generated a and t vectors Non-uniform low density parity check code encoding method further comprising. The method of claim 14, Storing a weight of a row based on the A vector and the T vector, wherein the weight of the row is the number of nonzero enemies in a row unit; And Storing the position and cyclic value of the column of non-zero elements in the row unit Non-uniform low density parity check code encoding method further comprising. The method of claim 19, And reading the weight value of the stored row and reading the position and the cyclic value of the column as many times as the weight value to generate the a vector, the t vector, and the second parity vector. The method of claim 14, The a vector is generated by cyclically accumulating the input vectors corresponding to positions of nonzero elements of each row in units of rows of the matrix A by element values, The t vector is generated by accumulating a value obtained by inverting the a vector by the diagonal element value of the T matrix and by cyclically moving the previous t vector by the element value of the T matrix below the diagonal element. The e vector is generated by cyclically accumulating the t vector by an element value of the E matrix, The c vector is a non-uniform low density parity check code encoding method generated by cyclically accumulating the input vectors by an element value of the C matrix. The method of claim 15, And the b vector is a non-uniform low density parity check code generated by circularly shifting the first parity vector by an element value at positions of nonzero elements of the B matrix.

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