JP4832447B2 - Decoding apparatus and method using channel code - Google Patents

Description

  The present invention relates to an encoding and decoding method. More specifically, the low density parity check (Low Density Parity) can improve the performance without occupying a large memory capacity, and can improve the encoding and decoding performance by reducing the complexity of hardware at the time of implementation. The present invention relates to an encoding / decoding method and apparatus using a code (hereinafter referred to as LDPC) code.

  Recently, an encoding method using an LDPC code has been highlighted. The LDPC code was proposed by Gallager in 1962 as a low density linear block code because most elements of the parity check matrix H are zero. The LDPC code is very complex and could not be implemented with the technology at the time of the proposal, but has been actively researched until recently since it was discovered again in 1995 and proved to have excellent performance. . (Reference: [1] Non-Patent Document 1 (Robert G. Gallager, “Low-Density Parity-Check Codes”, The MIT Press, September 15, 1963); [2] Non-Patent Document 2 (DJC) Mackay, Good error-correcting codes based on very sparse matrix, IEEE Trans. Inform. Theory, IT-45, pp. 399-431 (1999)).

  Since the parity check matrix of the LDPC code has a very small number of ones, even a very large block size can be decoded through iterative decoding. When the block size becomes very large, the channel capacity of Shannon like a turbo code is increased. Shows performance close to the limit. In the parity check matrix, the number of 1 included in a row or column is referred to as a weight.

The LDPC code is described by an (n−k) × n parity check matrix H. A generator matrix G corresponding to the parity check matrix H is obtained by the following mathematical formula 1.
[Mathematical Formula 1]
H ・ G = 0
In the encoding and decoding method using the LDPC code, on the transmission side, input data can be encoded by the mathematical formula 2 using the generation matrix G having the relationship of the parity check matrix H and the mathematical formula 1. .
[Mathematical formula 2]
c = G · x (where c is a code word and x is an information bit)
Hereinafter, a decoding method using the H matrix according to the related art will be described.

The decoder on the reception side should obtain the information bit x from the code word c that is the encoding result on the transmission side, but determines the information bit using the condition of Hc = 0. That is, when the received code word is c ′, the value of Hc ′ is calculated. When the calculation result of Hc ′ is 0, the k bits before c ′ are decoded information. Decide with a bit. If the value of Hc ′ is not 0, x is recovered by searching for c ′ that satisfies Hc ′ = 0 using a sum-product algorithm, a belief propagation algorithm or the like through a graph. Since the check equation Hc ′ = 0 can be changed to c′H ^T = 0 depending on the relationship between the information bits and the G matrix, the check equation varies depending on the relationship between the information bits and the G matrix.

FIG. 1 is a diagram illustrating a parity check matrix H through a bipartite graph. In FIG. 1, CNU (Check Node unit) indicates a check node unit, and VNU (variable node unit) indicates a bit node unit. The process of decoding by applying an algorithm to a bipartite graph can be roughly divided into three processes.
1. 1. Update probability value from check node to bit node 2. Update probability value from bit node to check node Decoding Value Determination Through Bit Node Probability First, in order to perform the first process, the check node is updated through an initialization step in which a probability value received from a channel is input. When the probability value from the bit node to the check node is updated after finishing the first process, the second process is performed. After the first and second processes are finished, a decoding value is determined using the probability value received from the channel and the probability value updated through the first and second processes.

  In the decoding process, after the first and second processes, if the decoded value c ′ determined in the third process satisfies the check expression Hc ′ = 0, the value c ′ is correctly received. Otherwise, the first and second processes are repeated a predetermined number of times until the inspection formula is satisfied. In the update process of probability values performed in the first and second processes, each update process is repeated by the number of non-zero components belonging to each row or column of the parity check matrix, that is, by one. That is, at the position corresponding to the weight of the parity check matrix H, the update of the first process and the update of the second process are performed. As the first and second processes are repeated, the reliability of the probability value between the check node and the bit node increases, and as a result, the reliability of the codeword to be obtained becomes closer.

Recently, in LDPC encoding, a method of encoding input data using the parity check matrix H regardless of the generation matrix G is generally used. Therefore, as described above, the parity check matrix H is the most important element in the encoding method using the LDPC code. Since the parity check matrix H has a size of about 1000 × 2000 or more, many operations are required in the encoding and decoding processes, the implementation is very complicated, and a lot of storage space is required. There is a problem.
Robert G. Gallager, “Low-Density Parity-Check Codes”, The MIT Press, September 15, 1963. D. J. et al. C. McCay, Good error-correcting codes based on very sparse metrics, IEEE Trans. Inform. Theory, IT-45, pp. 399-431 (1999)

  An object of the present invention is to solve the above problems, and an object of the present invention is to provide an encoding and decoding method using an LPDC code capable of improving performance when data is encoded or decoded on a transmission or reception side. Is to provide.

  A decoding method according to an embodiment of the present invention includes a step of receiving a signal encoded using a parity check matrix from a transmission side, and a step of decoding the received signal using the parity check matrix. The parity check matrix includes a plurality of layers, and non-zero components do not overlap each other in the column direction between the layers, and one layer includes at least one or more rows. It is characterized by that.

  Another example of a decoding method according to an embodiment of the present invention includes a step of receiving a signal encoded using a parity check matrix, and a plurality of layers, and a non-zero configuration in a column direction between the layers Decoding the received signal in units of a specific number of layers that do not overlap each other using a parity check matrix configured such that elements do not overlap each other, and each layer includes at least one or more rows It is characterized by including.

  A decoding apparatus according to an embodiment of the present invention includes a reception module that receives a signal encoded using a parity check matrix and a plurality of layers, and non-zero components are arranged in a column direction between the layers. Decoding a received signal in units of a specific number of layers that do not overlap each other using a memory that stores information of a parity check matrix configured not to be superposed and information of the parity check matrix obtained from the memory A module, wherein one layer includes at least one or more rows.

  The present invention is applied to a communication system that requires encoding and decoding, as well as various devices that require encoding and decoding.

  According to the encoding and decoding method using the LPDC code according to the present invention, there is an effect that the performance can be improved when data is encoded or decoded on the transmission or reception side.

  Hereinafter, preferred embodiments of an encoding method using an LDPC code according to the present invention will be described with reference to the accompanying drawings. FIG. 2A is a diagram for explaining a preferred embodiment of the present invention, and is an example in which the technical features of the present invention are applied to a wireless communication system. The embodiments described below are merely examples for explaining the features of the present invention, and those skilled in the art can apply the technical features of the present invention to all fields that require encoding. Will understand.

  As shown in FIG. 2A, the transmitter 10 and the receiver 30 communicate via the radio channel 20. In the transmitter 10, the k-bit source data u output from the data source 11 is LDPC-encoded by the LDPC encoding module 13 into an n-bit code word c. The codeword c is wirelessly modulated by the modulation module 15, transmitted through the antenna 17, and received by the antenna 31 of the receiver 30 through the wireless channel 20. The receiver 30 goes through the reverse process of the process that occurred in the transmitter 10. That is, the received data is demodulated by the demodulation module 33 and decoded by the LDPC decoding module 35, whereby the source data u is finally obtained. The above-described data transmission / reception process has been described within the minimum range necessary for explaining the features of the present invention, and a person skilled in the art can perform many other processes necessary for data transmission. You will understand that there is.

The parity check matrix H used to encode input source data in the LDPC encoding module has (n−k) × n dimensions. The k means the length (bit unit) of the source data input to the LDPC encoding module 13, and the n means the length (bit unit) of the encoded code word c. As shown in FIG. 3, the parity check matrix H includes a plurality of z × z permutation matrices or zero matrices. That is, in FIG. 3, P _{i, j} means a z × z-dimensional permutation matrix or a zero matrix.

  The plurality of permutation matrices are formed by transforming at least one basic permutation matrix according to a predetermined rule. The basic permutation matrix is preferably a unit matrix. The plurality of permutation matrices including the one or more basic permutation matrices preferably have a row and column weight of 1. That is, it is preferable that only one element is 1 and the remaining elements are 0 among all the rows and all the columns of the permutation matrix.

In the present invention, the method of deforming at least one or more basic permutation matrices according to a predetermined rule to form a plurality of permutation matrices may include all rows (or columns) of the basic permutation matrix. Including a method of shifting by a predetermined interval. 4A and 4B are diagrams for explaining an example thereof. That is, all the rows of the basic permutation matrix of FIG. 4A are shifted downward by 5 rows (n _s = 5) (or all the columns are shifted to the right by 3 columns) to form the permutation matrix of FIG. 4B. did. According to this method, (z−1) permutation matrices can be formed by the row (or column) spacing shifted with respect to the basic permutation matrix of z × z dimensions. Accordingly, z permutation matrices including the basic permutation matrix are formed. When the basic permutation matrix is given, the z permutation matrices including the basic permutation matrix are each expressed by one integer. For example, a basic permutation matrix is represented by 0, a permutation matrix obtained by shifting all the rows of the basic permutation matrix by one row is represented by 1, and all rows of the basic permutation matrix are represented. All permutation matrices are expressed by one integer by a method of expressing 2 by shifting the permutation matrix by 2 lines.

  As described above, a plurality of permutation matrix types formed from the basic permutation matrix are simply expressed by one integer according to the number of shifted rows (or columns). The method of expressing the multiple permutation matrix types with one integer is merely an example, and the multiple permutation matrix types may be expressed by other methods.

In the present invention, when encoding or decoding is performed using a parity check matrix H, each row (or column) of the at least one basic permutation matrix and the at least one basic permutation matrix. Each time when encoding or decoding is required on the transmitting side or the receiving side in a state where a large number of permutation matrix types formed by shifting by a predetermined interval are stored in the basic matrix _Hb , the at least A basic feature is that a parity check matrix H is generated using at least one basic permutation matrix and the basic matrix _Hb , and encoding or decoding is performed using the generated parity check matrix. To do. As shown in FIG. 2B, a preferred embodiment of an encoding apparatus using an LDPC code according to the present invention includes a memory module 131, a parity check matrix generation module 132, and an encoding module 134. The memory module 131 stores the basic permutation matrix and the basic matrix. The basic matrix generation module 132 generates the parity check matrix using the basic permutation matrix and the basic matrix stored in the memory module 131. The encoding module 134 encodes input source data using the parity check matrix generated by the parity check matrix generation module 132. It is obvious to those skilled in the art that the parity check matrix generation module 132 and the encoding module 134 are implemented by software or hardware according to each function.

The base matrix H _{b |} Considering divided into two parts of H _d and H _p having the structure [H d _{H p],} the said H _p portion, generally block double diagonal matrix Although it is preferable to use, it is not limited to this. A block double diagonal matrix means that the main diagonal and the diagonals directly below or above the main diagonal are all unit matrices, and the rest are all zero matrices. When the H _p portion is in the form of a block double diagonal matrix, a column having a column weight of 1 is generated in the H _p portion. To avoid this, one or two zero matrices are generated. Is preferably replaced with a unit matrix.

The H _d portion of the basic matrix H _b is composed of a combination of the basic permutation matrix, a number of permutation matrices formed by shifting each row of the basic permutation matrix by a predetermined interval, and a zero matrix. However, when the basic matrix _Hb is configured by combining the three types of matrices, the following matters are preferable in terms of encoding or decoding performance.

First, the difference in the number occupied by any two of the multiple permutation matrix types with respect to the entire basic matrix _Hb is not less than or equal to an already set first critical value. Don't be. That is, it is preferable that the number of each permutation matrix is the same or similar to the entire basic matrix _Hb . The first critical value is preferably as small as possible, but is allowed in the range of 3 to 7.

Second, it is preferable not to generate 4-cycles or 6-cycles in the entire parity check matrix H or to minimize the number of 4-cycles or 6-cycles. In particular, the parity check matrix preferably has no 4-cycle. In addition, the parity check matrix H preferably has 6 cycles less than or equal to the second critical value C _maX that has already been set. 4-cycle means a case where any two rows of the parity check matrix H have 1 at two points simultaneously. The 6-cycle means a case where all two combinable rows selected from any three rows of the parity check matrix H have 1 at the same point.

  Third, for the entire parity check matrix H, column weights and / or row weights should have regularity. When a z × z unit matrix is used as the basic permutation matrix, column weights and / or row weights have regularity for the entire parity check matrix H.

Fourth, the basic matrix _Hb should be configured by combining the three kinds of matrices so as to have good encoding or decoding performance for all code rates and all codeword sizes. is there. Recently, in the mobile communication system, since the variable code rate and codeword size is applied, the base matrix H _b and the base permutation matrix, each row of the base permutation matrix by a predetermined distance shift When configured by a combination of a large number of permutation matrices and zero matrices formed, it should be optimized to have good performance for all code rates and all codeword sizes.

FIGS. 5A to 5F are diagrams showing a preferred embodiment of the basic matrix _Hb having the above characteristics. The example shown in FIGS. 5A to 5F is a basic matrix when the code rate is 3/4, where “0” means a z × z-dimensional unit matrix, and “−1” indicates a z × z-dimensional unit matrix. Zero matrix means an integer of 1 or more means a permutation matrix formed by shifting each row of the z × z-dimensional unit matrix by the integer.

As shown in FIG. 6, the basic matrix _Hb when the code rate is 1/2 can be formed by reducing the size of the basic matrix when the code rate is 3/4.

FIG. 7 is a diagram showing another example of the basic matrix _Hb having the above characteristics. The example shown in FIG. 7 is a basic matrix when the code rate is 2/3. The meanings of '0', '-1' and other integers of 1 or more are the examples shown in FIGS. 5A to 5F. Is the same.

The basic permutation matrix should have different dimensions (i.e., z values) depending on the codeword length variation. However, the basic permutation matrix is provided for the basic permutation matrix of all dimensions, It is not preferable in terms of memory saving to save and use for encoding. Therefore, only the first basic matrix for the first basic permutation matrix having the largest dimension z _maX is stored, and the basic matrix for the second basic permutation matrix having the other dimension z is used for encoding or decoding. It is preferable to generate using the first basic matrix whenever necessary.

  In this case, the first basic matrix has two or more permutation matrix types as its elements. That is, the entire range of the dimension z of the basic permutation matrix to be changed is divided into two or more ranges, and the type of permutation matrix optimized for each range is set. For example, when the entire range of z to be varied is 10 to 96, the entire range is divided into a range of 10 to 53 and a range of 54 to 96, and the first basic matrix optimized for each range is obtained. Constitute. With this configuration, the first basic matrix becomes two, but by storing two values as each element of one first basic matrix without storing each separately, encoding or decoding is performed. Memory can be saved while improving performance.

  FIG. 8 shows another embodiment of the basic matrix when the code rate is 3/4. The basic matrix shown in FIG. 8 minimizes the number of 4 cycles and 6 cycles, makes the weight of each column regular, and each element of the basic matrix has the same code rate and code word size. The basic permutation matrix is shifted so as to have good performance. When the example shown in FIG. 8 is compared with the example shown in FIGS. 5A to 5F, the simulation result shows that the size is the same as that of the example shown in FIGS. Demonstrated performance.

Hereinafter, a method for decoding an LDPC code using the basic matrix _Hb as described above will be described. Conventional decoding of an LDPC code is mainly performed by repeating a process of increasing reliability by updating a probability value between a check node and a bit node on a bipartite graph which is another expression of a parity check matrix. Since the decoding method using the bipartite graph, which is another representation of the parity check matrix, determines the codeword through the updated probability value, the update process of the probability value that determines the codeword affects the performance of the decoder. Direct impact.

  The reliability update process is divided into a probability value update process from the check node to the bit node and a probability value update process from the bit node to the check node. When performing a probability value update process from the check node to the bit node or a probability value update process from the bit node to the check node, the probability value of the same column or the same row excluding its own probability value to be updated Update its own probability value with the value. As the probability value used at this time is updated more, a more reliable result (a more positive influence) is given to the decoder.

  Hereinafter, an LDPC decoding method that has a more positive influence on the decoding method will be described. According to an embodiment of the present invention, when an LDPC-encoded received signal is decoded using the parity check matrix, a method of decoding the received signal in units of layers that are groups of rows of the parity check matrix (hereinafter, Layered decoding is used. In the layered decoding, when updating a probability value from a bit node to a check node, if there is an updated value in the same column of the parity check matrix, the probability value is updated using the updated value. There are features.

  The layered decoding is a method of iterative decoding by dividing a row of a parity check matrix used for encoding and decoding of an LDPC code into a plurality of layers. The layer indicates a group of rows when the rows of the parity check matrix are grouped and divided. That is, when the rows of the parity check matrix are divided into several groups, one group becomes a layer. The layer is also a row.

  FIG. 9 is a diagram illustrating a basic matrix partitioned in units of layers. The basic matrix shown in FIG. 9 is an example for explaining the layered decoding method, and the numbers shown here indicate the types of multiple permutation matrices formed from the basic permutation matrix. This is indicated by the number of shifts.

  In the layered decoding, in the reliability update in the same row of the parity check matrix H, the reliability is updated using probability values that have undergone all the same level update processes. That is, similar to the conventional LDPC decoding method, the probability value is updated between the check node and the bit node on the bipartite graph. However, in the probability value update process from the bit node to the check node (that is, the probability value update process of the column of the parity check matrix H), the probability value is updated in units of layers, and the probability value included in a specific layer Is updated, the probability value included in the already updated layer is used. In the layered decoding, decoding is performed in units of layers, and once the probability values are updated for all layers included in the parity check matrix, one iteration for LDPC decoding is performed. The layered decoding has already been performed for the update of the probability value for one layer, and when the operation for the update of the probability value is performed for the next layer, the result of the calculation for the one layer, That is, by using the message result with the updated reliability in the calculation of the next layer, a message with higher reliability is used in the decoding process (that is, the probability value updating process). As a result, when the update of the probability value as described above is repeated, since a message with higher reliability is used for the update of the probability value, the reliability of the probability value between the check node and the bit node is increased, and the decoder The performance of becomes better. The matrix shown in FIG. 9 is a general basic matrix. The matrix shown in FIG. 9 can be sequentially decoded by a layered decoding method. For example, decoding is performed in the order of Layer 1 → Layer 2 → Layer 3 → Layer 4 → Layer 5 → Layer 6 → Layer 7 → Layer 8.

  The basic concept of parallel processing used in the present invention and preconditions for performing layered decoding by the parallel processing method will be described below.

  FIG. 10A is a diagram schematically illustrating the concept of parallel processing. Parallel processing means that when a single operation is performed, a plurality of arithmetic devices divide and process the work processed by one arithmetic device. As a result of the parallel processing, a positive effect that the time required to perform one work decreases in proportion to the number of operation blocks used for the parallel processing occurs. However, when parallel processing is performed, problems such as memory collision and dependency between data to be processed in parallel occur. In order to perform layered decoding in parallel according to the present invention, the above problems must be solved. I must.

  Hereinafter, a problem caused by the parallel processing of the layered decoding described above and a method for solving the problem according to the present invention will be described.

  FIG. 10B is a diagram illustrating the concept of memory collision by parallel processing. In the case of the serial processing method, since one arithmetic unit uses a memory block, there is no problem in reading a value to be calculated or storing a calculation result. However, in a parallel processing method in which a large number of arithmetic units operate simultaneously, a memory collision occurs when two or more arithmetic units simultaneously approach a memory block at the same position. If the probability value update units for LDPC decoding simultaneously approach the memory at the same position, the memory collision may occur.

  In order to apply the parallel processing method to the LDPC decoding, problems such as not only simultaneous access to the memory block but also dependency between data to be processed simultaneously should be eliminated. That is, if the output value of any one of a plurality of calculation blocks should be the input value of another calculation block at the same time, it must be sequentially calculated according to its dependence without processing at the same time. Don't be.

  In one embodiment of the LDPC decoding method according to the present invention, the parity check matrix is divided in units of layers and each layer is processed in a specific order, and the above-described memory collision and parallel processing are performed for a specific layer. There is a feature that the specific layer is decoded by a parallel processing method by solving a problem such as dependency between data. An embodiment of the present invention provides a parity check matrix having no overlapping portion between specific layers in order to perform data processing on the specific layers in a parallel processing manner. In the parity check matrix according to an embodiment of the present invention, the non-zero elements in a specific layer of the parity check matrix exist at different positions in the column direction. That is, for a specific layer, the positions where the parity check matrix weights are different from each other in the column direction.

  As described above, in a general LDPC code decoding method, probability values are updated in all rows of the H matrix, and subsequently, probability values are updated for all columns. On the other hand, in the layered decoding, when updating the probability value of each row, the probability value is updated in a group unit (that is, a layer unit) divided in advance. In this decoding method, when the probability values corresponding to the second and subsequent groups are updated, the decoding performance is improved by calculating using the probability values with higher reliability already updated in the previous group. The layered decoding has the advantages as described above. However, when the conventional parity check matrix is partitioned in a specific layer unit and data is processed in parallel processing for the specific layer, the layered decoding is performed. In order to avoid the above-described problems such as memory collision and dependency between data to be processed in parallel in the parallel processing process, only one layer should be processed at the same time, which causes a delay in decoding. However, as proposed in the present embodiment, when the parity check matrix is designed so that the positions where column weights do not overlap between specific layers, parallel processing for a large number of layers can be performed simultaneously.

  Hereinafter, a method of parallel processing layered decoding using a parity check matrix that is not superimposed on a specific layer according to an embodiment of the present invention will be described.

  FIG. 11 shows another embodiment of the basic matrix when the code rate is ½. In the embodiment, the rows of the parity check matrix generated by the basic matrix of FIG. 11 are grouped into one layer according to the size of the basic permutation matrix with respect to the basic matrix. That is, in the embodiment, the layer of the parity check matrix generated using the basic matrix and the basic permutation shown in FIG. 11 is composed of the number of rows of the basic permutation matrix. It is an example. As a result, the number of rows included in one layer in FIG. 11 is the same as the number of rows of the basic permutation matrix based on the basic matrix shown in FIG. The basic matrix shown in FIG. 11 has been proposed for effective parallel processing. In the layered decoding, when the order of the rows of the basic matrix shown in FIG. 11 is determined as 1 → 7 → 2 → 8 → 3 → 9 → 4 → 10 → 5 → 11 → 6 → 12 For the two rows (for example, the first row and the seventh row), the non-zero components do not overlap each other in an arbitrary column direction. In the basic matrix, components having a shift number of 0 or more are not superimposed in the column direction for any two rows (for example, the first row and the seventh row). For example, when the eighth row is compared with the second or third row, it can be seen that components having a shift number of 0 or more in any column direction do not overlap each other. In addition, a description will be given with reference to a parity check matrix generated by the basic matrix shown in FIG. 11. One row of the basic matrix indicates one layer of the generated parity check matrix. The position where the weight between each layer of the parity check matrix exists is not superimposed in the column direction.

  FIG. 12 shows another embodiment of the basic matrix when the code rate is ½. The basic matrix shown in FIG. 12 is proposed for more effective parallel processing. The basic matrix shown in FIG. 12 has the following two row pairs (1, 7), (2, 8), (3, 9), (4, 10), (5, 11), (6 , 12), a component having a shift number of 0 or more is designed not to be superimposed in an arbitrary column direction. 11 and 12 has a feature that efficient parallel processing is possible in an implementation process for layered decoding.

  Hereinafter, according to another embodiment of the present invention, the order of layers of a base matrix having no overlapping portion between specific layers is adjusted, and layered decoding is performed using a parity check matrix generated by the adjusted base matrix. A method of parallel processing will be described.

  FIG. 13A is a diagram illustrating an example of a basic matrix for layered decoding according to an embodiment of the present invention. In the basic matrix, “−1” indicates a zero matrix, and “#” indicates an arbitrary permutation matrix formed by shifting the basic permutation matrix by an arbitrary integer of 0 or more in the row or column direction. Indicates. In the embodiment, the rows of the parity check matrix generated by the basic matrix shown in FIG. 13A are grouped into one layer according to the size of the basic permutation matrix with respect to the basic matrix. That is, the number of rows included in each layer is the same as the number of rows of the basic permutation matrix by the basic matrix shown in FIG. 13A. Accordingly, one layer of the parity check matrix generated by the basic matrix corresponds to one row of the basic matrix. Hereinafter, a method for designing a new parity check matrix by adjusting the row order of the basic matrix so that positions where weights between adjacent layers of the parity check matrix do not overlap will be described. Since the base matrix has a double diagonal portion, it is possible to change the order of the rows without affecting the LDPC decoding performance and to design the parity check matrix according to an embodiment of the present invention. FIG. 13B is a basic diagram in which the order of the rows is adjusted so that components having a shift number of 0 or more do not overlap each other between the specific rows in FIG. 13A, that is, the column weight is 1 or less for a specific row. It is an example of a matrix. In the case of FIG. 13B, in Layer 0 and Layer 3, the position where the column weight exists is not superimposed on any column. FIG. 13C is a diagram showing the basic matrix shown in FIG. 13B in units of layers that can be processed in parallel. In FIG. 13B, when LDPC decoding is performed using the parity check matrix generated by the basic matrix shown in FIG. 13C, the calculation can be performed simultaneously on two layers (for example, Layer 0 and Layer 3). That is, as shown in FIG. 13D, Layers 0, 6, 4, and 2 and Layers 3, 1, 7, and 5 can be processed in parallel to process each layer simultaneously. As a result, when performing LDPC decoding using a parity check matrix according to an embodiment of the present invention, the same effect as when decoding two LDPC codes at once through two arithmetic units can be obtained, and decoding time can be increased. Can be reduced to a maximum of 50%.

  FIG. 14 is a diagram showing another embodiment of the basic matrix when the code rate is 2/3. In the basic matrix, “−1” indicates a zero matrix, and an arbitrary integer is an arbitrary permutation matrix formed by shifting the basic permutation matrix by an arbitrary integer of 0 or more in the row or column direction. Indicates. In the basic matrix shown in FIG. 14, “X” is a value that represents an arbitrary integer from 0 to 95, and is preferably any one of 86, 89, and 95. Most preferably, X = 95. The basic matrix shown in FIG. 14 has been proposed to have parallel processing characteristics and high performance. The parallel processing feature means that a decoding method for parallel processing layered decoding is applied according to the present invention. In the embodiment, the rows of the parity check matrix generated by the basic matrix shown in FIG. 14 are grouped into one layer according to the size of the basic permutation matrix for the basic matrix. That is, in FIG. 14, the number of rows included in each layer is the same as the number of rows of the basic permutation matrix based on the basic matrix shown in FIG. When the rows of the basic matrix are divided by the indices 1, 2, 3, 4, 5, 6, 7, and 8, the basic matrix generated by exchanging the rows with each other is zero or more between adjacent rows. Components having shift numbers do not overlap each other. For example, when the first row is compared with the fourth row, it can be seen that components having a shift number of 0 or more in any column direction do not overlap each other. Also, referring to the parity check matrix generated by the basic matrix shown in FIG. 14, one row of the basic matrix indicates one layer of the generated parity check matrix, but the generated The position where the weight between each layer of the parity check matrix exists does not overlap in the column direction.

  FIG. 15 is one of various examples of the basic matrix provided by exchanging rows satisfying the above-described conditions in the basic matrix shown in FIG. The basic matrix shown in FIG. 15 is an example in which the indexes of the basic matrix shown in FIG. 14 are exchanged in the order of 1-4-7-2-5-8-3-6. FIG. 15 adds the first row (i.e., to easily compare the first row with the last row of the basic matrix consisting of the index order 1-4-4-2-5-8-3-6). 1-4-7-2-5-8-3-6- (1)).

  All the basic matrices generated by exchanging the rows of the basic matrix shown in FIG. 15 define the same LDPC code as the LDPC code defined by the basic matrix shown in FIG. Therefore, even when a basic matrix whose rows are exchanged in decoding and encoding is used, decoding and encoding that exhibit the same performance as the basic matrix shown in FIG. 8 can be performed.

  In the above description, exhibiting high performance means that, for example, a frame error rate (FER) is good. In addition, decoding that exhibits the same performance means a decoding method that exhibits the same decoding performance, and encoding that exhibits the same performance means that the same codeword is generated.

  Hereinafter, an LDPC decoder that performs LDPC decoding using various basic matrices proposed in the present invention will be described. FIG. 16 is a block diagram showing an embodiment of the LDPC decoder according to the present invention. The LDPC decoder 1000 includes a CNU (Check Node Update Unit) block 1100, a control block 1200, a VNU (Variable Node Update Unit) block 1300, and a memory block 1400. The CNU block 1100 updates the probability value of the check node and includes at least one CNU 1110. The CNU 1110 is an arithmetic unit that updates the probability value of the check node. The control block 1200 includes a control unit 1210 that controls the operation of each unit of the decoder 1000, a CNU routing network 1220 that controls the CNU block 1100 and the memory block 1400 according to a parity check matrix structure, and the VNU block. 1300, a VNU routing network 1230 that controls the memory block 1400, a parity check matrix index storage unit 1240 that stores information on the structure of the parity check matrix, and the like, and a decoded value is determined using the updated probability value. A hard decision unit 1250 that inspects the decoded value. The VNU block 1100 updates probability values of bit nodes and includes at least one VNU 1310. The VNU 1310 is an arithmetic unit that updates the probability value of the check node. The CNU 1110 and VNU 1310 controlled by the control block 1200 calculate and update the probability value for the non-zero component of the H matrix, and the calculated probability value is stored in the memory unit 1400. The memory unit 1400 stores an R-memory 1410 that stores a probability value calculated for updating a probability value from a check node to a bit node, and a probability calculated for updating a probability value from the bit node to the check node. A receive LLR memory 1420 that stores values (eg, Log Likelihood Ratio values received from a radio channel), and a Q-memory 1430 that stores probability values calculated for updating probability values from bit nodes to check nodes. ,including.

Hereinafter, each unit will be described. The reception LLR memory 1420 is a memory for storing a probability value for a received signal to be decoded, for example, an LLR value for a codeword of the received signal. The R-memory 1410 stores a result R _mj of a probability value update at a specific check node, and the Q-memory 1430 stores a result L (q _mj ) of a probability value update at a specific bit node. save. The control unit 1210 controls the operation order of each unit and the operation timing of each unit, and the parity check matrix index storage unit 1240 stores information on the positions of weights of the parity check matrix. In addition, the CNU routing network 1220 acquires information on the parity check matrix from the parity check matrix index storage unit 1240, and appropriately connects the CNU 1110 and the memory of the memory unit 1400. In addition, the VNU routing network 1230 acquires information on the parity check matrix from the parity check matrix index storage unit 1240, and appropriately connects the VNU 1310 and the memory of the memory unit 1400. The hard decision unit 1250 is a unit that determines a decoded value using the Q-memory 1430 and inspects the determined decoded value c ′, and the decoded value c ′ satisfies a check expression of Hc ′ = 0. In this case, the decoded value c ′ is output as a true value, and when the check expression is not satisfied, decoding is repeated within a predetermined maximum number of iterative decoding.

  16 may decode the received signal using a parity check matrix stored in a separate memory (not shown) or the parity check matrix index storage unit 1240, or may generate a base matrix and a base par. The received signal can be decoded using a parity check matrix generated through a mutation matrix. When generating a parity check matrix through the basic matrix and the basic permutation matrix, the decoder 1000 includes a storage unit (not shown) that stores the basic matrix and the basic permutation matrix, and the basic matrix and the basic matrix. It is preferable to include a parity check matrix generation unit (not shown) that generates the parity check matrix using a permutation matrix. In addition, the decoder 1000 illustrated in FIG. 16 can adjust the row order (for example, layer order) of the parity check matrix and generate a new parity check matrix. In this case, the decoder 1000 preferably includes a parity check matrix adjustment unit (not shown) that adjusts the order of the rows of the parity check matrix.

Hereinafter, the operation of the LDPC decoder 1000 will be described. The LDPC decoder 1000 can perform decoding using a Log BP (Log Belief Propagation) algorithm which is one of LDPC decoding algorithms. The decoder 1000 operates in an initialization stage, a check node update stage, a bit node update stage, and a hard decision stage. In the initialization step, the probability value for the received signal transmitted from the transmission side is stored in the reception LLR memory 1420, and the probability value stored in the reception LLR memory 1420 is stored in the parity check matrix index storage unit 1240. And storing information at a specific position of the Q-memory 1430 using information on the weight of the parity check matrix. In the check node update step, check node update using the probability value stored in the Q-memory 1430, that is, update from check node to bit node, and storing the result in the R-memory 1410 is performed. including. The bit node updating step updates the bit node using the probability value stored in the R-memory 1410, that is, updates the bit node to the check node, and stores the result in the Q-memory 1430. including. The hard decision step temporarily determines a decoded value c ′ using a probability value stored in the Q-memory 1430, checks the determined decoded value c ′, and determines the decoded value c ′ according to a check result. If 'is a true value, the true value is output, and if the decoded value c ′ is not a true value, the check node update step and the bit node update step are repeated within a specific number of iterations.
[Formula 3]

前記復号器１０００で用いるパリティ検査行列Ｈが前記数学式３と同一であるとき、前記Ｒ−メモリ１４１０と前記Ｑ−メモリ１４３０は、前記パリティ検査行列の非ゼロ成分、すなわち、１が存在する成分の位置の値を保存する役割をする。したがって、前記Ｒ−メモリ１４１０と前記Ｑ−メモリ１４３０は、次のような位置の値を保存する役割をする。

When the parity check matrix H used in the decoder 1000 is the same as the mathematical formula 3, the R-memory 1410 and the Q-memory 1430 have a non-zero component of the parity check matrix, that is, a component in which 1 exists. It serves to store the position value of. Accordingly, the R-memory 1410 and the Q-memory 1430 serve to store the following position values.

ただし、前記Ｒ−メモリ１４１０及び前記Ｑ−メモリ１４３０は、前記非ゼロ成分の位置に該当する値のみを保存すればよいので、図１７のような構造で前記確率値更新のための演算結果を保存することができる。したがって、ＬＤＰＣ復号化のために必要なメモリは、Ｈ行列の重みに比例する。図１７に示したパリティ検査行列の重みに関する位置情報は、前記パリティ検査行列インデックス保存部１２４０に保存される。上述したように、前記復号器１０００は、基本行列及び基本パーミュテーション行列を用いてパリティ検査行列を生成して復号化作業を行うか、特定のメモリに保存されたパリティ検査行列を用いて復号化作業を行うか、任意の方法によって生成されたパリティ検査行列を用いて復号化作業を行う。以下で説明されるパリティ検査行列は、基本行列でない実際のパリティ検査行列を意味する。前記パリティ検査行列は、基本行列及び基本パーミュテーション行列を用いて生成されるか、特定のメモリや外部装置に保存されたパリティ検査行列を獲得して生成されるが、これらに限定されることはない。

However, since the R-memory 1410 and the Q-memory 1430 need only store the value corresponding to the position of the non-zero component, the calculation result for updating the probability value in the structure as shown in FIG. Can be saved. Therefore, the memory required for LDPC decoding is proportional to the weight of the H matrix. The location information on the parity check matrix weight shown in FIG. 17 is stored in the parity check matrix index storage 1240. As described above, the decoder 1000 generates a parity check matrix using a basic matrix and a basic permutation matrix, and performs a decoding operation or decodes using a parity check matrix stored in a specific memory. Or a decoding operation is performed using a parity check matrix generated by an arbitrary method. The parity check matrix described below means an actual parity check matrix that is not a basic matrix. The parity check matrix may be generated using a basic matrix and a basic permutation matrix, or may be generated by acquiring a parity check matrix stored in a specific memory or an external device, but is not limited thereto. There is no.

  FIG. 18 is a diagram illustrating an example of a connection form of a CNU, a VNU, and a memory of a decoder that performs decoding using the H matrix of the mathematical formula 3. The decoder shown in FIG. 18 is an example in the case of including 4 CNUs and 8 VNUs. 19A to 19H are diagrams illustrating a process from an initialization process in which a probability value for a received signal is input to a process of performing one iteration decoding when decoding is performed using the decoder illustrated in FIG. is there. The coordinates displayed in the R-memory 1410 and the Q-memory 1430 in FIGS. 19A to 19H indicate memory addresses when the memory is configured as shown in FIG.

  FIG. 19A is a diagram illustrating an initialization stage in LDPC decoding. The component shown in FIG. 19A indicates a non-zero component of the H matrix, and the probability value received from the transmission side is input to the memory address corresponding to the non-zero component.

  19A to 19E are diagrams illustrating probability value update from a check node to a bit node. The update of the probability value at the specific position is an operation of updating the own component using the remaining components excluding the own component in a specific row. 19F to 19H are diagrams illustrating probability value update from a bit node to a check node. The update of the probability value at the specific position is an operation of updating the own component using the remaining components excluding the own component in the specific column.

  After performing the process up to FIG. 19H, the code word is temporarily determined with reference to the Q-memory 1430, and whether or not the temporarily determined code word c ′ satisfies the check expression Hc ′ = 0. Confirm. If the inspection formula is not satisfied, the processes of FIGS. 19B to 19H are repeated. If there has been a set number of iterations or a codeword satisfying the check equation is obtained, the process is terminated.

  Hereinafter, the operation of the LDPC decoder 1000 that performs parallel processing on layered decoding to which parallel processing is applied will be described.

According to an embodiment of the present invention, the CNU 1110 and VNU 1310 of the LDPC decoder 1000 update the probability value through an operation such as Equation 4 below. The following mathematical formula 4 is a mathematical formula used when performing iterative decoding once.
[Formula 4]

上記の数学式で用いられる変数は、次の通りである。

The variables used in the above mathematical formula are as follows.

Ｌ（ｑ_ｍｊ）：ｍ番目のビットノードからｊ番目の検査ノードに連結されたＬＬＲ（Ｌｏｇ Ｌｉｋｅｌｉｈｏｏｄ Ｒａｔｉｏ）値
Ｌ（ｑ_ｊ）：ｊ番目のビットノードの事後ＬＬＲ値（ａ ｐｏｓｔｅｒｉｏｒ ＬＬＲ ｖａｌｕｅ）
Ｒ_ｍｊ：ｊ番目の検査ノードからｍ番目のビットノードに連結されたＬＬＲ値
Ａ_ｍｊ：ｊ番目の検査ノードからｍ番目のビットノードに連結されたＬＬＲ値を計算するための中間変数（ｄｕｍｍｙ ｖａｒｉａｂｌｅ）
Ｓ_ｍｊ：ｊ番目の検査ノードからｍ番目のビットノードに連結されたＬＬＲ値の符号を計算するための中間変数。

L (q _mj ): LLR (Log Likelihood Ratio) value concatenated from the mth bit node to the jth check node L (q _j ): a posteriori LLR value of the jth bit node (a positive LLR value)
R _mj : LLR value concatenated from the jth check node to the mth bit node A _mj : Intermediate variable for calculating the LLR value concatenated from the jth check node to the mth bit node (dummy variable) )
S _mj : An intermediate variable for calculating the sign of the LLR value connected from the jth check node to the mth bit node.

m: Check node index of parity check matrix j: Bit node index of parity check matrix Equation 5 below is an example of an LLR of a received signal, and Equation 6 below is a decoder according to an embodiment of the present invention. 1000 is an example of a parity check matrix used by 1000.
[Mathematical formula 5]

［数学式６］

[Formula 6]

上記の数学式６の行列は、本発明の一実施例による復号器１０００で用いるパリティ検査行列の一例である。前記行列において、前記パリティ検査行列の一つの行は、一つのレイヤーを示す。前記各レイヤーは、互いに隣接するレイヤーと重畳しない。前記復号器１０００のＣＮＵ１１１０及びＶＮＵ１３１０の個数は、前記パリティ検査行列の構造によって決定することが好ましい。また、重畳しないレイヤーは、並列処理されるが、前記ＣＮＵ１１１０の個数は、並列処理されるレイヤーに含まれる行の個数であることが一層好ましく、前記ＶＮＵ１３１０の個数は、前記パリティ検査行列の列の個数であることが一層好ましい。したがって、上記の数学式６を用いる前記復号器１０００のＣＮＵ１１１０は、２個であることが好ましく、ＶＮＵ１３１０は、２４個であることが好ましい。

The matrix of Equation 6 is an example of a parity check matrix used in the decoder 1000 according to an embodiment of the present invention. In the matrix, one row of the parity check matrix indicates one layer. The layers do not overlap with adjacent layers. The number of CNU 1110 and VNU 1310 in the decoder 1000 is preferably determined according to the structure of the parity check matrix. The non-overlapping layers are processed in parallel, but the number of CNUs 1110 is more preferably the number of rows included in the parallel processed layers, and the number of VNUs 1310 is the number of columns of the parity check matrix. More preferably, it is the number. Therefore, the number of CNUs 1110 of the decoder 1000 using the mathematical formula 6 is preferably two and the number of VNUs 1310 is preferably 24.

20A to 20I are diagrams illustrating a process of performing iterative decoding once when decoding is performed by the LDPC decoding method of the present invention. 20A to 20I, Q and R in FIG. 20 indicate the state of the memory that stores the q _mj and R _mj values of Equation 4, and “##” is an arbitrary value that has not yet been set to a specific value. Indicates the value of. The Q-memory 1430 and the R-memory 1410 in FIGS. 20A to 20I can store only the operation value corresponding to the position of the non-zero component, as shown in FIG.

  FIG. 20A is a diagram illustrating an initialization stage in LDPC decoding according to an embodiment of the present invention. A probability value (eg, LLR value) received from a channel is stored in the reception LLR memory 1420, and the received probability value is related to a weight of a parity check matrix stored in the parity check matrix index storage unit 1240. The position information is input to the Q-memory 1430. FIG. 20A shows a probability value input to the Q-memory through the initialization step.

  FIG. 20B shows a probability value update process from a check node to a bit node for Layer 0 and Layer 3 of the H matrix. The CNU 1110 performs an operation of updating the probability value from the check node to the bit node for Layer 0 and Layer 3 of the H matrix. As described above, two CNUs 1110 operate with two CNUs 1110, and the two CNUs 1110 perform a check node update process for Layers 0 and 3. The calculation result is stored in the R-memory 1410.

  FIG. 20C shows a probability value update process from the bit node to the check node for Layer 0 and Layer 3 of the H matrix. Unlike the conventional LDPC decoding process, the process of updating the probability value from the bit node to the check node updates the probability value of the current layer using the probability value of the layer already updated in the same iteration stage. Since Layer 0 and Layer 3 do not overlap each other, problems such as memory collision due to parallel processing and dependency between parallel processed data do not occur. Therefore, the process of updating the probability value from the bit node to the check node for Layer 0 and the process of updating the probability value from the bit node to the check node for Layer 3 are performed in parallel. As described above, the decoder performs calculations on Layer 0 and Layer 3 using 24 VNUs 1310. In FIG. 20C, the result of the probability value update from the bit node to the check node for Layer 0 and Layer 3 and the probability value for the update of the probability value from the check node to the bit node for Layer 6 and Layer 1 are input. The result of the setting stage is shown.

  FIG. 20D illustrates a probability value updating process from the check node to the bit node for Layer 6 and Layer 1 of the H matrix, and FIG. 20E illustrates a probability value updating process from the bit node to the check node for Layer 6 and Layer 1 of the H matrix. 20F shows a probability value update process from check nodes to bit nodes for Layer 4 and Layer 7 of the H matrix, and FIG. 20G shows a probability value update process from bit nodes to check nodes for Layer 4 and Layer 7 of the H matrix. FIG. 20H shows a probability value update process from the check node to the bit node for Layer2 and Layer5 of the H matrix, and FIG. 20I shows the probability from the bit node to the check node for Layer2 and Layer5 of the H matrix. Value update process It is. The value stored in the Q-memory 1430 is an operation value obtained through one iteration. After performing the process up to FIG. 20I, the hard decision unit 1250 temporarily determines the code word c ′ with reference to the Q-memory 1430, and the code word c ′ satisfies the check expression Hc ′ = 0. Check if you are satisfied. If the check equation is not satisfied, the decoder repeats the processes of FIGS. 20B to 20I. If there is a repetition of the maximum number of repetitions or if a code word satisfying the check equation is obtained, the process is terminated and the code word c 'is output to the outside.

  The decoding method shown in FIG. 20 has the following differences when compared with the decoding method shown in FIG. That is, the decoding method shown in FIG. 19 performs one check node update and bit node update using the maximum number of CNUs and VNUs according to the size of the parity check matrix, but the decoding method shown in FIG. Includes CNUs corresponding to the number of layers having no data dependency, that is, the number of layers not overlapping each other in the parity check matrix, and performing parallel processing of the check node update process according to the number of layers having no data dependency. Can do.

  Further, the decoding method shown in FIG. 19 initializes the entire area of the Q-memory 1430 using the probability value for the received signal, whereas the decoding method shown in FIG. Initialization is performed, and the result values for these layers are used as initial values for the next layer.

  It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit and essential characteristics of the invention. Accordingly, the above detailed description should not be construed as restrictive in all respects but should be considered as exemplary. The scope of the invention should be determined by reasonable analysis of the appended claims, and all changes that come within the equivalent scope of the invention are intended to be embraced within the scope of the invention.

6 is a diagram illustrating a parity check matrix H through a bipartite graph. FIG. 1 is an example in which the technical features of the present invention are applied to a wireless communication system. This is an example in which the technical features of the present invention are applied to an encoding apparatus. It is a figure which shows that a basic matrix is comprised by many permutation matrices or zero matrix of zxz dimension. FIG. 6 is a diagram illustrating a method of shifting all rows (or columns) of a basic permutation matrix by a predetermined interval according to the present invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix based on one Example of this invention. It is a figure which shows the basic matrix in case the code rate is 1/2 formed by reducing the magnitude | size of the basic matrix in case the code rate is 3/4. It is a figure which shows the other basic matrix which concerns on one Example of this invention. It is another Example of the said basic matrix in case a code rate is 3/4. It is a figure which shows the example of the parity check matrix divided | segmented per layer. It is a figure which shows the concept of parallel processing. It is a figure which shows the concept of the memory collision by parallel processing. It is another Example of a basic matrix in case a code rate is 1/2. It is another Example of the said basic matrix in case a code rate is 1/2. It is a figure which shows an example of the parity check matrix which can be processed in parallel by this invention. It is a figure which shows an example of the parity check matrix which can be processed in parallel by this invention. It is a figure which shows an example of the parity check matrix which can be processed in parallel by this invention. It is a figure which shows an example of the parity check matrix which can be processed in parallel by this invention. It is a figure which shows the other Example of the said basic matrix in case a code rate is 2/3. It is a figure which shows the basic matrix obtained by exchanging the row | line | column of the basic matrix proposed by this invention. It is a block diagram which shows one Example of the LDPC decoder based on one Example of this invention. 3 is a diagram illustrating a memory structure of an LDPC decoder according to an embodiment of the present invention. FIG. It is a figure which shows the connection form between the hardware of the LDPC decoder which concerns on one Example of this invention. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding, it is a figure which shows the process of performing iterative decoding once in the initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process. When performing LDPC decoding to which parallel processing is applied, it is a diagram illustrating a process of performing iterative decoding once in an initialization process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Transmitter 11 Data source 13 LDPC encoding module 15 Modulation module 17, 31 Antenna 20 Radio channel 30 Receiver 33 Demodulation module 35 LDPC decoding module

Claims (13)

A decoding method using a channel code,
The method
Receiving a signal encoded using a parity check matrix H;
A basic matrix H corresponding to the parity check matrix H _b Decoding the received signal using a z × z basic permutation matrix and a z × z zero matrix;
Including
z is greater than 1,
The basic matrix H _b Is

“−1” represents the z × z zero matrix, “non-negative integer” represents the number of shifts, and each row or each column of the basic permutation matrix of z × z is the number of shifts. A z × z permutation matrix is generated by shifting, where “X” represents an integer in the range of 0-95,
The basic matrix H _b Layer of

Identified by indices 1, 2, 3, 4, 5, 6, 7 and 8 of
In decoding the received signal, layers 1 and 4 are processed in parallel, layers 7 and 2 are processed in parallel, layers 5 and 8 are processed in parallel, and layers 3 and 6 are processed in parallel. ,Method. The method of claim 1, wherein the z × z basic permutation matrix is a z × z identity matrix. The decoding step includes:
The basic matrix H _b “−1” of the above is replaced with the z × z zero matrix, and the basic matrix H _b By exchanging the “non-negative integer” of ｚ with a z × z permutation matrix represented by the non-negative integer. _b Generating the parity check matrix H from:
Decoding the received signal using the parity check matrix H;
The method according to claim 1, comprising: The decoding step includes:
Inputting data corresponding to the received signal into layer 1 and layer 4, layer 7 and layer 2, layer 5 and layer 8 or layer 3 and layer 6;
Updating the data entered in the corresponding two layers;
The method of claim 3 comprising: Updating the data input to the two corresponding layers is as follows:
Performing a check-variable node data update process on the corresponding two layers;
Performing a variable-check node data update process for the two corresponding layers;
The method of claim 4 comprising: The method of claim 4, wherein the input data is data updated through the data update process. The decoding step includes:

The basic matrix H so that there is at most one permutation matrix in the column direction of two adjacent layers of the adjusted basic matrix _b Adjusting the layer order of
Two adjacent layers 1 and 4 are processed in parallel, two adjacent layers 7 and 2 are processed in parallel, two adjacent layers 5 and 8 are processed in parallel, two adjacent layers 3 and layer Parallel processing 6
The method according to claim 1, comprising: A decoding device using a channel code,
The device is
A receiving module for receiving a signal encoded using a parity check matrix H;
A basic matrix H corresponding to the parity check matrix H _b And a memory for storing a z × z basic permutation matrix and a z × z zero matrix,
The basic matrix H obtained from the memory _b And a decoding module for decoding the received signal using the z × z basic permutation matrix and the z × z zero matrix.
Including
z is greater than 1,
The basic matrix H _b Is

“−1” represents the z × z zero matrix, “non-negative integer” represents the number of shifts, and each row or each column of the basic permutation matrix of z × z is the number of shifts. A z × z permutation matrix is generated by shifting, where “X” represents an integer in the range of 0-95,
The basic matrix H _b Layer of

Identified by indices 1, 2, 3, 4, 5, 6, 7 and 8 of
The decoding module is configured to process layer 1 and layer 4 in parallel, layer 7 and layer 2 in parallel, layer 5 and layer 8 in parallel, and layer 3 and layer 6 in parallel. The equipment. 9. The apparatus of claim 8, wherein the z × z basic permutation matrix is a z × z identity matrix. The decryption module is
The basic matrix H _b “−1” of the above is replaced with the z × z zero matrix, and the basic matrix H _b By exchanging the “non-negative integer” of ｚ with a z × z permutation matrix represented by the non-negative integer. _b Generating the parity check matrix H from:
Decoding the received signal using the parity check matrix H;
10. An apparatus according to claim 8 or 9, wherein the apparatus is configured to perform: The decryption module is
At least one check node update unit for updating data input to two corresponding layers to be processed in parallel and performing a check-variable node update of the data corresponding to the received signal;
At least one variable node update unit for performing a variable-check node update of data corresponding to the received signals input to two corresponding layers to be processed in parallel;
The apparatus of claim 10, comprising: The apparatus according to claim 11, wherein the input data is data already updated via the check node update unit or the variable node update unit. The decryption module is

The basic matrix H so that there is at most one permutation matrix in the column direction of two adjacent layers of the adjusted basic matrix _b Adjusting the layer order,
Two adjacent layers 1 and 4 are processed in parallel, two adjacent layers 7 and 2 are processed in parallel, two adjacent layers 5 and 8 are processed in parallel, two adjacent layers 3 and layer Parallel processing 6
10. An apparatus according to claim 8 or 9, further configured to perform:

Images