KR100559376B1 - Method and circuits for acquiring synchronization - Google Patents

Abstract

The present invention discloses a synchronization acquisition method and a circuit. The method of the present invention obtains the correlation integral value between the received in-phase signal and the quadrature signal and the replicated signal, respectively. The obtained in-phase and quadrature correlation integral value pairs are synthesized to generate one sample value. The sample values are stored for a predetermined sample period. The Fourier transforms the stored sample values to obtain a transform value. For each of the plurality of taps, a tap having a peak value is determined from the obtained conversion values.

Therefore, in the present invention, the processing speed is improved by reducing the amount of memory used in the CDMA communication system and performing one channel FFT.

Description

Method and circuits for acquiring synchronization

1 is a block diagram of a GPS receiver according to the present invention.

2 is a block diagram showing a conventional configuration of the channel circuit of FIG.

3 is a block diagram showing a configuration of a channel circuit according to the present invention;

4 is a circuit diagram of a synthesizer corresponding to a tap other than the center tap of the combining section of FIG.

FIG. 5 is a circuit diagram of a center synthesizer corresponding to the center tap of the combiner of FIG. 3. FIG.

Fig. 6 is a graph showing a change in sample value during one sample period of a tap in which no peak value exists.

7 is a graph showing a change in sample value during one sample period of a tap in which a peak value exists.

FIG. 8 is a graph comparing the change in the composite value and the peak tap trend of a tap having no peak value and a tap having a peak value during one sample period. FIG.

9 is a graph comparing the results of the conventional two-channel FFT and the results of the one-channel FFT according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to spread spectrum (SS) global positioning system (GPS) receivers, and more particularly, to a method and a circuit capable of high-speed search for a correlation maximum value for synchronization acquisition.

The Global Positing System (GPS) installs more than 30 satellites in a given orbit, and up to 12 satellites of the 30 satellites can be viewed simultaneously by a GPS receiver at a given location.

The GPS receiver determines its position by calculating the transit time of signals transmitted simultaneously from several satellites within range of view. The receiver must receive signals of at least four visible satellites in order to calculate its position.

Each satellite in the GPS system transmits a so-called L1 signal at a carrier frequency of 1575.42 MHz. This frequency is also denoted as 154f ₀ , where f ₀ = 10.23 MHz.

In satellites, signals are modulated in a code division multiple access (CDMA) scheme with a similar noise sequence to form a code modulated wideband signal.

One of the similar noise sequences used for each satellite for modulation of the L1 signal is the C / A code (coarse / acquisition code), which is a gold code. Each GPS satellite transmits a signal using a unique C / A code. The codes are formed of a modulo 2 sum of two 1023 bit binary sequences. C / A codes are binary codes and in a GPS system the chipping rate is 1.023 MHz. The C / A code has 1023 chips which means that the code repetition time is 1 ms.

The carrier of the L1 signal is further modulated with navigation information at a bit rate of 50 bits / s. The navigation information includes information about satellite health, orbit and clock data parameters, and the like.

In order to detect satellite signals and to identify satellites, the receiver must perform a synchronization operation, and the receiver retrieves the signals of the respective satellites and attempts to synchronize with the signals so that the data transmitted in the signal can be received and demodulated. do.

The positioning receiver must perform synchronization, for example when the receiver is switched on and also in a situation where the receiver cannot receive signals of any satellite for a long time. Such a situation can easily occur in mobile devices, for example, because the device is moving and the antenna of the device is not always in optimal position with respect to satellites, weakening the strength of the signal reaching the receiver. In urban areas, buildings also affect the received signal, and in addition, the so-called multiplex, in which the transmitted signal reaches the receiver via several other routes, eg, straight from the satellite, and also reflected from the buildings. Can cause path propagation. As a result of this multipath propagation, the same signal is received as several signals with different phases.

The distances to the satellites are called pseudo ranges because the time is not known exactly at the receiver. In that case the determination of position and time is repeated until sufficient accuracy is achieved.

The calculation of the pseudo range can be performed by measuring the average transit times of other satellite signals. After the receiver synchronizes with the received signal, the information transmitted in the signal is demodulated.

Almost all known GPS receivers use correlation methods to calculate similar ranges. Pseudo-random sequences of satellites are stored or generated locally at the positioning receiver.

Down conversion is performed on the received signal and the receiver multiplies the received signal by a stored (or locally generated) similar noise sequence. The signal formed as a result of multiplication is integrated and the result indicates whether the received signal includes the signal transmitted by the satellite. The multiplication performed at the receiver is repeated so that the phase of the pseudonoise sequence stored at the receiver is shifted every time. The exact phase is estimated in such a way that the correct phase is found when the correlation result is the highest. The correlation result also represents the information transmitted in the GPS signal, meaning that it is a demodulation signal.

The above-described synchronization and frequency adjustment process must be repeated for each satellite signal received at the receiver. Thus, this process consumes a lot of time, especially in situations where the received signals are weak.

In some prior art receivers, several correlators are used to speed up this process, so that more correlation peaks can be retrieved simultaneously. In certain applications, since the number of correlators cannot be infinitely increased, simply increasing the number of correlators cannot accelerate the synchronization and frequency adjustment process more.

In general, a receiver has a plurality of channels for high speed synchronization, and each channel is composed of multiple correlation taps. Therefore, since the number of correlation peak values stored in the memory increases in proportion to the number of channels and the number of taps, a large amount of storage space is required. In addition, in order to perform a Fast Fourier Transform (FFT) algorithm in which the processor determines synchronization acquisition with reference to the data stored in the memory, the amount of data access between the processor and the memory increases. In addition, since the two-channel FFT in in-phase and quadrature is performed in the FFT process, the processing speed becomes slow.

Therefore, the hardware design burden between the processor and the memory is increased to store a large amount of data in memory at high speed and read the data again to process the data.

In addition, since a large amount of memory is required to store a lot of data, the area occupied by the memory becomes large, which hinders the miniaturization of the GPS receiver.

Therefore, in order to solve such a problem, GPS receiver developers or manufacturers employ technologies that store only correlation integral values above the threshold value in the memory, compared to the threshold value, before storing the plurality of correlation integral values in the memory. An example is disclosed in US Pat. No. 6,208,291.

However, if the correlation integral values are simply compared with a threshold value, there is a fear that the wrong value is searched for as the correlation maximum value. Therefore, in order to minimize such errors, each manufacturer is researching various technologies using their own algorithms.

 Summary of the Invention An object of the present invention is to synchronize the in-phase and quadrature sample values into one and perform a one-channel FFT with the synthesized sample values before storing the correlated integrated sample values in a memory in order to solve the above-described problems of the prior art. To provide a capturing method and apparatus.

In order to achieve the above object, the method of the present invention obtains in-phase and quadrature correlation integral values between the received in-phase signal and the quadrature signal and the replicated signal, respectively. The obtained in-phase and quadrature correlation integral value pairs are synthesized and generated as one sample value. The sample values are stored for a predetermined sample period. The stored plurality of sample values are transformed by one channel fast Fourier transform to obtain a transform value. For each of the plurality of taps, a tap having a peak value is determined from the obtained conversion values.

In the present invention, the step of generating a sample value is a sign of the current in phase correlation integral value is a negative sign when the current in phase correlation integral value and the previous in phase correlation integral value is different from each other and a positive sign. If the sign of the current orthogonal correlation integral value and the previous orthogonal correlation integral value is different from each other, the sign of the current orthogonal correlation integral value is made a negative sign and the same sign is a positive sign. The signed in-phase correlation integral value and the orthogonal correlation integration value are added together to generate the sum value as the sample value.

The absolute value of each of the signed in-phase and quadrature correlation integral values in the present invention is adjusted to a value that is an appropriate positive number, preferably one half of the absolute value, of the current in-phase and quadrature correlation integration values.

The method further comprises storing in-phase correlation integral values and quadrature correlation integral values from the determined taps as separate sample values, respectively, after determining the taps having the peak values.

In the present invention, the predetermined sample period is determined according to the configuration of the FFT. For example, in the case of a 16-point FFT, 16 samples are obtained.

The circuit of the present invention is composed of a plurality of taps, each tap having a correlation integration unit for obtaining a correlation integral value between a received in-phase signal and a quadrature signal and a duplicated signal, and the obtained in-phase and quadrature correlation integral value pairs. Synthesizer to generate one sample value for each tap, a first storage unit to store the sample values for a predetermined sample period, and to perform Fourier transform on the stored sample values to obtain a converted value, A peak tap determination unit for determining a tap having a peak value from the obtained conversion values, and a code generator for providing a duplicated signal having a different delay characteristic to each tap of the correlation integrator in response to the peak tap determination unit; do.

In the circuit of the present invention, when the current in-phase correlation value and the previous in-phase correlation value are different from each other, the synthesis part has a negative sign and a positive sign in the same case. Orthogonal code processing unit for setting the sign of the current orthogonal correlation integral value as a negative sign when the current orthogonal correlation integral value and the previous orthogonal correlation integral value are different from each other; And an adder that adds the signed in-phase correlation integral value and the orthogonal correlation integration value and generates the sum value as the sample value.

The circuit of the present invention further includes a second storage unit for storing the in-phase correlation integral value and the orthogonal correlation integral value from the determined tap as separate sample values after determining the tap having the peak value.

The present invention is applied to a synchronous acquisition circuit of a CDMA communication receiver using a PN code, and particularly to a synchronous acquisition circuit of a GPS receiver integrated circuit chip.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention.

1 shows a configuration of a general GPS receiver. The GPS receiver 100 receives a radio frequency signal of 1575.42 MHz transmitted from the GPS satellites 10 through the GPS antenna 102. The received radio frequency signal is mixed with the local oscillation signal provided from the local oscillator 106 in the radio frequency converter 104 and down converted to an intermediate frequency signal of 4.3 MHz. The RF converter 104 is separated into and outputs in-phase and quadrature intermediate frequency signals through a low noise amplifier, a filter, a mixer, an intermediate frequency amplifier, and a quadrature mixer.

In-phase and quadrature intermediate frequency signals are respectively converted into digital data signals through an analog-to-digital converter (ADC), and the converted in-phase and quadrature digital data signals are respectively transmitted to the plurality of channel circuits 110. Each channel circuit 110 searches for a correlation maximum value by performing code correlation for synchronization acquisition and tracking of a GPS signal provided from a selected satellite.

The search processor 112 calculates a similar range from each satellite by performing acquisition and tracking with the searched correlation maximum. The controller 114 calculates a position value of the receiver using the plurality of similar ranges provided from the search processor 112 and displays the calculated position value on the display unit 116.

Referring to FIG. 2, the conventional channel circuit 110 performs a two-dimensional search process to capture a carrier / acquisition (C / A) code and a carrier frequency of a satellite signal selected for each channel.

The Doppler frequency is present in the intermediate frequency signals I _IF and Q _IF . The carrier numerically controlled oscillator 202 generates an oscillation signal whose frequency varies in response to the detected Doppler frequency information. A sine signal generator 204 inputs the oscillation signal to generate a sine signal, and a cosine signal generator 206 inputs the oscillation signal to generate a cosine signal.

The in-phase multiplier 208 multiplies the intermediate frequency signal I _IF by a sine signal to generate an in-phase signal I _B of the baseband. The quadrature booster 210 multiplies the intermediate frequency signal Q _IF by the cosine signal to generate a baseband quadrature signal Q _B.

The code numerically controlled oscillator 212 generates an oscillation signal whose phase is changed in response to the search phase, and generates a duplicate code in the PN code generator 214 in response to the generated oscillation signal. The generated duplicate code is generated with m delayed duplicate codes having different delay characteristics through the code shifter 216. Each of the m delayed replication codes generated is provided to corresponding taps TAP1 to m of the correlation integration unit 218.

The correlation integrator 218 includes m correlation integrators. Each correlation integrator multiplies the in-phase signal (I _B ) and the quadrature signal (Q _B ) by the corresponding delayed duplicate signal and the multiplier, respectively, to obtain a correlation value. -detection) Integral during integration time to generate in-phase and quadrature correlation integrals, respectively.

In-phase and quadrature correlation integral values obtained for each tap TAP1 to TAPm, that is, 2m sample values for each sample period are stored in the memory 220 over k times. Thus, 2mk sample values are stored in the memory 220.

Therefore, if the number of taps per channel is n, n sample values are stored in the memory 220 every sample period.

The search processor 112 takes 2k sample values stored in the memory for each tap during the sample period, that is, the post-detection time, and performs fast Fourier transform on each of the in-phase and quadrature signals and thresholds the converted values. Compare the value to find the peak value. When the tap with the peak value is detected, the delayed replication code with the peak value is controlled to be located at the center of the tap, that is, the m / 2 position tap, and then the confirmation procedure, that is, the tracking operation, is performed to perform the synchronous tracking mode. To perform. On the contrary, if a tap having a peak value is not detected, it is determined that the received signal is only noise and changes the search range, that is, phase and frequency. That is, the values of the code numerically controlled oscillator 212 and the carrier numerically controlled oscillator 202 are controlled to be changed.

This Costas loop is repeated, changing the phase and frequency to be searched until synchronization is acquired.

Therefore, in the conventional receiver, since the number of samples stored in the memory is determined by the product of the number of channels, the number of taps, the in-phase and quadrature, and the number of samplings of the post-search time, a large storage location is required.

Since a large amount of samples should be written to the memory and the written data should be read at high speed, hardware design burden for signal interfacing between the search processor and the memory is increased from the hardware developer or designer's point of view.

In addition, the search processing unit 112 performs FFTs on two in-phase and quadrature channels, respectively, and obtains a result value, respectively, and then searches for a tap having a peak value with absolute values of the result values obtained by the peak value determination unit. . Therefore, two-channel FFT and search processing algorithm are complicated and processing time is increased.

Accordingly, the present invention solves the existing problem by reducing the number of samples stored in the memory in half and improving the processing speed with one channel FFT in order to reduce the memory interfacing design burden.

3 shows the configuration of the channel circuit 310 according to the present invention. In the circuit of FIG. 3, parts identical to those of FIG. 2 are denoted by the same reference numerals.

Referring to FIG. 3, the channel circuit 310 of the present invention uses one sample value Ii + Qi through the synthesizer 314 to store in-phase and quadrature correlation integral values before storing the correlation integral values in the memory 316. 0 <i <m + 1). Therefore, the storage capacity of the memory 316 can be reduced to 1/2 compared to the existing one, and the interface between the search processor 312 and the memory 316 can be simplified.

The memory 316 stores m sample values every k cycles for a sample period. Also, the memory 316 receives and stores in-phase and quadrature sample values I _{m / 2} and Q _{m / 2} from the center tap m / 2 at the time of capturing. Therefore, the size of the memory 316 has a size of (m + 2) k (l + 1) bits (l is the number of sample bits) for each channel circuit. For example, for 16-bit samples, 17 bits are required for composite values. Therefore, the memory size is reduced by about 47% compared with the case of storing the conventional I and Q sample values.

The search processor 312 receives k samples for each tap and performs Fourier transform through one channel FFT 312-1. The peak value determining unit 312-2 compares the FFT-converted value with a threshold value to determine a tap having a peak value.

If a tap with a peak value is found, it is determined that synchronization is acquired and the code numerically controlled oscillator 212, code generator 214, code shifter is placed so that the delayed duplicate signal of the corresponding tap is located at the center tap for synchronization tracking. Control 216 to fix the code value and frequency at which the peak value appears. The in-phase sample value I _{m / 2} and the quadrature sample value Q _{m / 2} obtained through the center tap by the fixed code value and the frequency are stored in the memory 316 without passing through the synthesis unit 314. Save it. This value is used for phase offset, bit boundary search, and bit decoding during sync tracking.

If the tap with the peak value is not found, the search range is changed and the phase and frequency of the changed search range are provided to the code numerically controlled oscillator 212 and the carrier numerically controlled oscillator 202, respectively, and the peak is repeated. Navigate through the tabs with values.

Referring to FIG. 3, the synthesis unit 314 of the present invention is composed of m synthesizers COMPO1 to COMPOm, each synthesizer is as shown in FIG. 4, and the center synthesizer COMPO _{m / 2} is illustrated in FIG. 5. As shown.

Referring to FIG. 4, each synthesizer COMPOi includes a three-bit synthesizer including delayers 314-1 and 314-3, exclusive logic circuits 314-2 and 314-4, and an adder 314-5. .

The delay unit 314-1 delays the sine bit of the current in-phase sample value by one sample period in the in-phase channel to generate the sine bit of the previous in-phase sample value.

The exclusive logic circuit 314-2 compares the sine bits of the current in-phase sample value with the sine bits of the previous in-phase sample value, and makes the minus sign of the current in-phase sample value negative in case of mismatch, and adds it in the same case.

Delay 314-3 delays the sine bit of the current orthogonal sample value by one sample period in the orthogonal channel to generate the sine bit of the previous orthogonal sample value.

The exclusive logic circuit 314-4 compares the sine bits of the current orthogonal sample value and the sine bits of the previous orthogonal sample value to make the sign bits of the current orthogonal sample value minus in the case of mismatch, and to positive in the same case. do.

The adder 314-5 uses the output bit of the exclusive logic circuit 314-2 and the two bits of the in-phase sample value as one 3-bit inputs, and the output bit of the exclusive logic circuit 314-4 and the 2-bit orthogonal sample value. The other 3 bits are input and these are summed and the result is output as a 4 bit data signal.

Therefore, the synthesizer of the present invention adds a sign when the sign of the present value and the previous value is the same, minus the sign of the difference, and sets an absolute value to 1/2 of the present value. 1/2 is for scaling absolute values, which is theoretically positive.

Referring to FIG. 5, the center synthesizer COMPO _{m / 2} corresponding to the center tap has the same structure as the synthesizer described above. However, it also has paths PS1 and PS2 for providing in-phase sample values I _{m / 2} and quadrature sample values Q _{m / 2} to the memory during synchronization capture.

<Computer simulation example>

Comparing the sample values of the tap with no peak value and the tap with a peak value in the strong signal (1dB) is shown in Tables 1 and 2 below.

Sample value of tap without peak I _i value (phase sample value) Q _i value (Orthogonal sample value) I _i / 2 Q _i / 2 Composite One 174 -6 87 3 90 2 -214 280 -107 -140 -247 3 360 -88 -180 -44 -224 4 -297 154 -148.5 -77 -225.5 5 353 43 -176.5 21.5 -155 6 -84 289 -42 144.5 102.5 7 -95 -255 47.5 -112.5 -65 8 -4 -172 2 86 88 9 153 158 -76.5 -79 -155.5 10 -11 -267 -5.5 -133.5 -139 11 -267 -19 133.5 9.5 143 12 -44 -152 22 76 98 13 324 182 -162 -91 -253 14 -346 21 -173 10.5 -162.5 15 -167 -24 83.5 -12 71.5 16 20 -276 -10 138 128

Sample value of tap with peak I _{m / 2} value (phase sample value) Q _{m / 2} value (orthogonal sample value) I _{m / 2/2} Q _{m /} 2/2 Composite One 12200 1020 6100 510 6610 2 12100 -132 6050 -66 5984 3 11900 -2650 5950 1325 7275 4 11300 -4340 5650 2170 7820 5 10700 -6010 5350 3005 8355 6 9940 -6990 4970 3495 8465 7 9250 -7910 4625 3955 8580 8 7780 -9350 3890 4675 8565 9 6510 -10400 3255 5200 8455 10 5400 -10800 2700 5400 8100 11 4080 -11400 3040 5700 7740 12 2200 -11800 1100 5900 7000 13 774 -12100 387 6050 6457 14 -408 -11900 -204 5950 5746 15 -2020 -11700 1010 5850 6860 16 -3670 -11500 1835 5750 7585

FIG. 6 is a graph showing changes in, I and Q values in Table 1, and FIG. 7 is a graph showing changes in I and Q sample values in Table 2. 6 and 7, if there is no peak value, the sign change of the I and Q sample values is very severe and the absolute value is small, but if there is a peak value, there is almost no change in the sign of the I and Q sample values and the absolute value. You can see this is relatively large.

8 is a graph showing changes in the composite values of Tables 1 and 2 and peak tap trend lines. Referring to FIG. 8, the number of sign changes of the composite value is less than the number of sign changes of the I and Q sample values, and the absolute value is also reduced. If there is no peak value, the number of sign changes is reduced but the sign change is still severe. However, if there is a peak value, there is no sign change.

FIG. 9 is a graph showing two channel FFTs of I and Q sample values of Tables 1 and 2, respectively, and an absolute value of the result and one channel FFT of the composite value of Table 1. FIG. In the figure, the curves indicated by square points (non-peak taps in the figure) represent the two-channel FFTs of the I and Q sample values in Table 1, respectively, and the absolute values of the results. Tap) is a two-channel FFT of the I and Q sample values in Table 2, respectively, and represents the absolute value of the result, and a curve (indicated by Interr.FFT in the figure) represents the combined value of Table 1 in one channel. The result of the FFT is shown. As shown in FIG. 9, it can be seen that the result of the one-channel FFT of the synthesized value is similar to the result of the two-channel FFT of the tap with the peak value. Therefore, even if I and Q sample values are first synthesized and the synthesized value is 1 channel FFT, the peak value can be searched.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

As described above, in the present invention, instead of separately storing the I and Q sample values in each tap and storing them in a memory, the memory spaces are obtained by obtaining their synthesized values in hardware and storing the obtained synthesized values as one sample value in the memory. It can be reduced by about 47.5%.                     

In addition, the FFT configuration can be simplified by configuring a one-channel FFT instead of a two-channel FFT, and the processing speed can be improved since the calculation of the absolute value is omitted after the FFT.

Therefore, the configuration of the Costas loop circuit in the CDMA receiver integrated circuit can be simplified, and the processing performance can be improved.

Claims (8)

Obtaining in-phase and quadrature correlation integral values between the received in-phase signal and the quadrature signal and the replicated signal, respectively; Synthesizing the obtained in-phase and quadrature correlation integral value pairs and generating them as one sample value; Storing the sample values for a predetermined sample period; Obtaining a transform value by transforming the plurality of stored sample values by 1 channel fast Fourier transform; And And determining a tap having a peak value from the obtained conversion values for the plurality of taps, respectively. The method of claim 1, wherein generating the sample value If the sign of the current in-phase correlation integral value and the previous in-phase correlation integral value is different from each other, making the sign of the current in-phase correlation integral value a negative sign and in the same case, a positive sign; If the sign of the current orthogonal correlation integral value and the previous orthogonal correlation integral value is different from each other, making the sign of the current orthogonal correlation integral value a negative sign and a positive sign if it is the same; And adding the coded in-phase correlation integral value and the orthogonal correlation integration value and generating the sum value as the sample value. 3. The method of claim 2, wherein an absolute value of each of the coded in-phase and quadrature correlation integral values is one half of an absolute value of each of the current in-phase and quadrature correlation integral values. The method of claim 1, wherein after the tap having the peak value is determined, the synchronization capturing method further includes storing in-phase correlation values and orthogonal correlation values from the determined taps as separate sample values, respectively. Synchronous acquisition method. A correlation integrating unit comprising a plurality of taps, each tap obtaining a correlation integration value between the received in-phase signal and the quadrature signal and the duplicated signal; A synthesizer for synthesizing the obtained in-phase and quadrature correlation integral pairs and generating one sample value for each tap; A first storage unit for storing the sample values for a predetermined sample period; A peak tap determination unit which obtains a transform value by fast Fourier transforming the stored sample values and determines a tap having a peak value from the obtained transform values; And And a code generator for providing a duplicated signal having a different delay characteristic to each tap of the correlation integrator in response to the peak tap determination unit. The method of claim 5, wherein the synthesis unit An in-phase sign processing unit that makes the sign of the current in-phase correlation integral value negative when the sign of the current in phase correlation integral value and the previous in-phase correlation integral value differs from each other; An orthogonal code processing unit that sets a sign of a current orthogonal correlation integral value as a negative sign and a same sign as a positive sign when the current orthogonal correlation integral value and the previous orthogonal correlation integral value are different from each other; And an adder which adds the coded in-phase correlation integral value and the orthogonal correlation integration value and generates the sum value as the sample value. 7. The acquisition circuit according to claim 6, wherein an absolute value of each of the coded in-phase and quadrature correlation integral values is one half of an absolute value of each of the current in-phase and quadrature correlation integral values. The method of claim 5, wherein the acquisition circuit further comprises a second storage unit for storing the in-phase correlation integral and the orthogonal correlation integral from the determined tap as separate sample values after determining the tap having the peak value. A synchronous acquisition circuit, characterized in that.

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