KR101276727B1 - Method and apparatus for detecting phase and frequency - Google Patents

Abstract

The present invention relates to a phase frequency detection method and apparatus, comprising: a sampling signal generation step of generating a sampling signal by sampling input data at an active transition of a reference clock signal; Generating a first simulation delay signal in which the input data is delayed by a delay time in the sampling signal generation step; A sampling delay signal generating step of generating a sampling delay signal having a preset phase difference from the sampling signal by using the sampling signal; Generating a second simulation delay signal in which the sampling signal is delayed by a delay time in the sampling delay signal generating step; Generating a pulse train by using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal; And adjusting a frequency of the reference clock signal by using the pulse train.

Description

Phase frequency detection method and apparatus {METHOD AND APPARATUS FOR DETECTING PHASE AND FREQUENCY}

The present invention relates to a method and apparatus for detecting phase frequency, and more particularly, to a method and apparatus for detecting phase frequency of input data by comparing input data with sampled data.

Existing high speed data transceiver has a form of transmitting a reference clock signal synchronized with the transmitter to transmit data from the transmitter to the receiver. However, according to this method, when data is transmitted over a long distance of up to several meters, a skew problem may occur between the data and the reference clock, which may cause a problem in data recovery at the receiver. In addition, the conventional transceiver has a cumbersome problem such as changing the reference clock signal of the receiver, or change the digital code to change the transmission speed.

To solve this problem, the “A 650 Mb / s-to-8 Gb / s referenceless CDR circuit with automatic acquisition of data rate” detects the detection window to compare the phase of arbitrary serial data with the clock signal of the voltage-controlled oscillator (VCO). We propose a method that detects the phase of serial data and clock only when there is a data transition within a given window, but according to this method, the phase update time is reduced because the phase difference cannot be detected at every transition of the serial data. In addition, there is a problem that the jitter characteristic is lowered and the synchronization time is increased, and the problem of large power consumption and area increase due to the use of the delay locked loop also occurs.

On the other hand, "A 0.5-to-2.5 Gb / s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance" divides the input data over a long period to generate a low frequency clock signal. To solve the above problems. However, this method has a problem of requiring a long synchronization time because the data must be divided for a long period instead of having a simple structure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and an object thereof is to provide a method and apparatus for detecting phase frequency having a wide frequency operating range without using an external clock or a specific data pattern.

In addition, the present invention detects the phase frequency of the input data by comparing the input data with the sampled data, thereby eliminating skew problems between the reference clock and the data, improving the actual data rate, and improving phase update time and frequency synchronization. It is another object of the present invention to provide a method and apparatus for detecting phase frequency that can shorten time.

It is another object of the present invention to provide a satellite frequency detection method and apparatus which can minimize the number of transmission channels and reduce hardware costs by eliminating the use of additional clock sources.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned can be understood by the following description and more clearly understood by the embodiments of the present invention. It will also be readily apparent that the objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

According to an aspect of the present invention, there is provided a phase frequency detection method comprising: a sampling signal generation step of generating a sampling signal by sampling input data at an active transition of a reference clock signal; Generating a first simulation delay signal in which the input data is delayed by a delay time in the sampling signal generation step; A sampling delay signal generating step of generating a sampling delay signal having a preset phase difference from the sampling signal by using the sampling signal; Generating a second simulation delay signal in which the sampling signal is delayed by a delay time in the sampling delay signal generating step; Generating a pulse train by using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal; And adjusting a frequency of the reference clock signal by using the pulse train.

In addition, the present invention provides a phase frequency detection device comprising: a sampling unit for sampling a input data at an active transition of a reference clock signal to generate a sampling signal; A first simulation delay unit generating a first simulation delay signal in which the input data is delayed by a delay time in the sampling unit; A sampling delay unit configured to generate a sampling delay signal having a predetermined phase difference from the sampling signal by using the sampling signal; A second simulation delay unit which generates a second simulation delay signal in which the sampling signal is delayed by a delay time in the sampling delay unit; A phase detector generating a pulse train using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal; And a frequency adjusting unit adjusting the frequency of the reference clock signal using the pulse train.

According to the present invention as described above, it can have a wide frequency operating range without using an external clock or a specific data pattern.

Further, according to the present invention, by detecting the phase frequency of the input data by comparing the input data with the sampled data, the skew problem between the reference clock and the data is eliminated, the actual data rate is improved, and the phase update time and Frequency synchronizing time is shortened.

In addition, according to the present invention, by eliminating the use of additional clock sources, the number of transmission channels can be minimized and hardware costs can be reduced.

1 is a block diagram of a phase frequency detection apparatus according to an embodiment of the present invention;
2 is a block diagram of a frequency adjusting unit according to an embodiment of the present invention;
3 is a block diagram of a phase frequency detection apparatus according to an embodiment of the present invention using a multi-phase clock as a reference clock signal;
4 is a timing diagram illustrating an operation of a phase frequency detection device according to an embodiment of the present invention;
5 is a block diagram of an acceleration signal generator according to an embodiment of the present invention;
6 is a circuit diagram of an acceleration signal generator according to an embodiment of the present invention;
7 is a timing diagram illustrating an operation of an acceleration signal generator according to an embodiment of the present invention;
8 is a flow chart for explaining the overall flow of the phase frequency detection method according to an embodiment of the present invention;
9 is a flowchart illustrating a pulse train generation process in detail in a phase frequency detection method according to an embodiment of the present invention;
10 is a flowchart illustrating a frequency adjustment process of a reference clock signal in a phase frequency detection method according to an embodiment of the present invention;
11 is a flowchart illustrating a phase frequency detection method including an acceleration signal generation process according to an embodiment of the present invention;
12 is a flowchart illustrating a method of generating an acceleration signal in detail in a phase frequency detection method according to an embodiment of the present invention.

The above objects, features, and advantages will be described in detail with reference to the accompanying drawings, whereby those skilled in the art to which the present invention pertains may easily implement the technical idea of the present invention. In describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements.

In addition, in this specification, the active transition of the signal means the rising edge or the falling edge of the signal, and the active transition of the inverted signal means the falling edge or the rising edge.

Hereinafter, a configuration of a phase frequency detection device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of an apparatus for detecting phase frequency according to an embodiment of the present invention, and FIG. 2 is a block diagram of a frequency adjusting unit according to an embodiment of the present invention.

Referring to FIG. 1, a phase frequency detection device according to an exemplary embodiment of the present invention includes a sampling unit 110, a first simulation delay unit 130, a sampling delay unit 150, and a second simulation delay unit 170. , The phase detector 180 and the frequency controller 190 may further include the acceleration signal generator 140.

The sampling unit 110 generates a sampling signal by sampling input data at an active transition of the reference clock signal. The reference clock signal is a signal output from a voltage controlled oscillator included in the frequency adjuster 190, more specifically, the frequency adjuster 190 of the present invention.

In an ideal system, the sampling signal is generated by sampling the input data at the active transition of the reference clock signal, so that it is in phase with the reference clock signal. Therefore, if the frequency of the reference clock signal is within a range capable of sufficiently sampling the input data, the sampling signal may be a signal having the same shape as the input data and whose phase is synchronized with the reference clock signal. Using this principle, the present invention attempts to detect phases easily by comparing two signals having the same shape and different phases, without generating a window or applying a separate design technique. In this case, since phase detection is possible for every transition of data, phase update time can be minimized and synchronization time can be minimized.

, 샘플링부(110)에 의해 지연되는 위상을

라고 하면, 샘플링 신호의 위상

은

이 된다. 따라서 본 발명은 실제 시스템에서 발생하는 지연을 고려하여, 샘플링 신호와의 위상 차 검출 시에, 입력 데이터 대신 샘플링부(110)의 지연 시간에 따른 위상 변화가 반영된 제1 모사지연신호를 사용한다.However, in practice, the phase change according to the delay time of the sampling unit 110 is reflected in the phase synchronized with the reference clock signal. For example, the phase of the reference clock signal

The phase delayed by the sampling unit 110

If so, the phase of the sampling signal

silver

. Accordingly, the present invention uses the first simulation delay signal reflecting the phase change according to the delay time of the sampling unit 110 when detecting the phase difference with the sampling signal in consideration of the delay occurring in the actual system.

라고 하면, 제1 모사지연부(130)에서 생성되는 제1 모사지연신호의 위상(

)은

로 나타낼 수 있다.The first simulation delay unit 130 generates a first simulation delay signal in which the input data is delayed by the delay time of the sampling unit 110. The first copy delay unit 130 may delay the input data by the delay time of the sampling unit 110 using a replica delay circuit. Therefore, the phase of the input data

In this case, the phase of the first simulation delay signal generated by the first simulation delay unit 130 (

)silver

.

The acceleration signal generator 140 improves the frequency synchronization speed of the reference clock signal by using the sampling signal output from the sampling unit 110 and the first simulation delay signal output from the first simulation delay unit 130. Generate an acceleration signal. The acceleration signal is input to the frequency adjusting unit 190 and used to adjust the frequency of the reference clock signal. The present invention further includes an acceleration signal generation unit 140, thereby shortening the time for synchronizing the phase and the frequency of the reference clock signal with the phase and the frequency of the input data. A detailed operation of the acceleration signal generator 140 will be described in detail with reference to FIG. 4.

라 하면, 샘플링 지연신호는

로 나타낼 수 있다.(

는 샘플링 지연부(150)에서의 지연시간에 따른 위상 차.)The sampling delay unit 150 generates a sampling delay signal having a preset phase difference from the sampling signal by using the sampling signal output from the sampling unit 110. More specifically, the sampling delay unit 150 may sample the sampling signal such that the sampling signal and the sampling delay signal have a phase difference of 0.5 UI (Unit Interval). Here, the phase difference of 0.5 UI means a phase difference except for the phase difference according to the delay time in the sampling delay unit 150. Therefore, the phase of the sampling delay signal

In other words, the sampling delay signal is

Can be represented as:

Is the phase difference according to the delay time in the sampling delay unit 150.)

)에는 샘플링 신호의 위상에 샘플링지연부(150)에서의 지연 시간에 따른 위상 변화가 더해지므로,

로 표현할 수 있다.The second simulation delay unit 170 generates a second simulation delay signal in which the sampling signal is delayed by the delay time of the sampling delay unit 150. Like the first simulation delay unit 130, the second simulation delay unit 170 may delay the sampling signal by the delay time of the sampling delay unit 150 using a replica delay circuit. . Therefore, the phase of the second simulated delay signal (

) Is added to the phase of the sampling signal according to the delay time of the sampling delay unit 150 according to the delay time,

.

The phase detector 180 generates a pulse train using a sampling signal, a first simulation delay signal, a sampling delay signal, and a second simulation delay signal. More specifically, the phase detector 180 generates a positive pulse PD_UP proportional to the phase difference between the sampling signal and the first simulation delay signal, and generates a negative signal proportional to the phase difference between the sampling delay signal and the second simulation delay signal. Generates a pulse of PD_DN. Therefore, referring to the phase of the signal output from each module described above is as follows.

First, the phase difference between the sampling signal and the first simulation delay signal may be expressed by Equation 1 below.

 The phase difference between the sampling delay signal and the second simulation delay signal may be expressed by Equation 2 below.

delete

Generating a pulse corresponding to the phase difference means generating a pulse having a pulse width proportional to the phase difference. Thus, referring to Equation 2, the phase of the sampling delay signal and the second simulation delay signal are described. The negative pulse PD_DN corresponding to the difference has a pulse width corresponding to 0.5 UI for every data transition.

The frequency controller 190 adjusts the frequency of the reference clock signal by using the pulse train generated by the phase detector 180. Referring to FIG. 2, the frequency controller 190 may include a charge pump 193, a loop filter 195, and a voltage controlled oscillator 197.

The charge pump 193 pumps a charge proportional to the pulse width of the pulse train. Therefore, the amount of charge corresponding to the pulse width of the positive pulse PD_UP corresponding to the phase difference between the sampling signal and the first simulation delay signal is pushed out by the loop filter 195, and the phase difference between the sampling delay signal and the second simulation delay signal is reduced. The amount of charge corresponding to the pulse width of the negative pulse PD_DN corresponding to may be attracted.

The loop filter 195 generates a control voltage corresponding to the change in the amount of pumped charge. The loop filter 195 generally has a structure of a low pass filter and includes capacitors arranged in parallel to accumulate or discharge charges pumped by the charge pump 193. Since the voltage applied to the capacitor is proportional to the accumulated charge amount, the control voltage applied to the output terminal of the loop filter 195 is determined by the change of the charge amount pumped by the charge pump 193. The loop filter 195 may also serve to remove harmonics at the front end of the voltage controlled oscillator 197.

The voltage controlled oscillator 197 adjusts the frequency of the reference clock signal in response to the change of the control voltage. Therefore, looking at the overall operation of the frequency adjuster 190, it can be seen that the frequency is finally adjusted by the pulse train output from the phase detector 180.

에 비례하므로, 전체 루프는 입력 데이터와 기준 클럭 신호가 0.5UI의 위상 차이를 가질 때까지 동기화 동작을 계속 수행하게 된다. 그 결과, 기준 클럭 신호의 위상 및 주파수가 입력 데이터의 위상 및 주파수에 동기되면, 전체 루프는 위상 및 주파수 동기화 동작을 마치게 된다. 위상 및 주파수가 동기되는 원리는 후술하는 도 4 및 도 7의 타이밍도를 통해 보다 자세히 설명하기로 한다.The negative pulse output from the phase detector 180 always has a fixed pulse width of 0.5 UI, and the pulse width of the positive pulse is

In proportion to, the entire loop continues to perform the synchronization operation until the input data and the reference clock signal have a phase difference of 0.5 UI. As a result, if the phase and frequency of the reference clock signal are synchronized with the phase and frequency of the input data, the entire loop completes the phase and frequency synchronization operation. The principle of synchronizing phase and frequency will be described in more detail through the timing diagrams of FIGS. 4 and 7 described later.

When the above-described modules are actually implemented, the delay time of the sampling unit 110 and the sampling delay unit 150 and the first and second simulation delay units 130 and 170 may be changed by process, voltage, and temperature variation (PVT variation). There may be a difference in the delay time. However, according to the present invention, this delay time difference does not affect the frequency adjustment.

라고 하면, 제1 모사지연부(130)에서 생성되는 제1 모사지연신호의 위상(

)은

가 되고, 제2 모사지연신호의 위상(

)은

가 된다. 이 경우, 샘플링 신호와 제1 모사지연신호의 위상 차는 하기의 [수학식 3]과 같이 나타낼 수 있다.This is shown in the following formula. The phase difference according to the difference between the delay time of the sampling unit 110 and the sampling delay unit 130 and the delay time of the first and second simulation delay units 130 and 170 is calculated.

In this case, the phase of the first simulation delay signal generated by the first simulation delay unit 130 (

)silver

Phase of the second simulated delay signal

)silver

. In this case, the phase difference between the sampling signal and the first simulation delay signal may be expressed by Equation 3 below.

The phase difference between the sampling delay signal and the second simulation delay signal may be expressed by Equation 4 below.

delete

가 포함되어 있으므로, 결과적으로 해당 위상 차에 의한 효과는 상쇄되어 주파수를 조절하는 제어 전압에 영향을 미치지 않을 수 있다.
That is, for each of the negative and positive pulses

As a result, the effect of the phase difference is canceled as a result and may not affect the control voltage for adjusting the frequency.

Hereinafter, an operation in the case of using a multi-phase clock as a reference clock signal will be described with reference to FIGS. 3 and 4.

)를 도시하지 않았다.3 is a block diagram of a phase frequency detection apparatus according to an embodiment of the present invention using a multi-phase clock as a reference clock signal, and FIG. 4 illustrates an operation of the phase frequency detection apparatus according to an embodiment of the present invention. Is a timing diagram. For reference, in the timing diagram of FIG. 4, for convenience of explanation, the phase change according to the delay time of each module (

Not shown).

Referring to FIG. 3, a phase frequency detection device using a multi-phase clock as a reference clock signal includes a sampling unit including a first parallel unit 313 and a first serializer 315. A sampling delay unit 350 including a 310, a second parallel unit 353, and a second series unit 355, a first simulation delay unit 330, a second simulation delay unit 370, and a phase detector ( 380, and a frequency adjusting unit 390, and may further include an acceleration signal generator 340.

As shown in Fig. 4, when using a multi-phase clock, the input data is sampled at each active transition (falling edge of the clock shown in Fig. 4) of the multi-phase clock, so the sampling rate is used when using a single clock. It can be several times faster.

When using a multi-phase clock, the first parallelizer 313 samples the input data at each active transition of the multi-phase clock to generate a first parallel signal. The first serializer 315 restores the first parallel signal to a sampling signal in series. As described above, the phase change of the sampling signal is added to the phase of the reference clock signal according to the delay time of the first parallelizer 313 and the first serializer 315. Therefore, in order to compare a sampling signal having the same shape as the input data and having the same phase and frequency as the reference clock signal with the input data, the first parallelizer 313 and the first serializer 315 are reflected in the actual sampling signal. The phase change should also be reflected in the input data. To this end, the first simulation delay unit 330 generates a first simulation delay signal in which the input data is delayed by a delay time between the first parallelizer 313 and the first serializer 315.

The sampling signal is once again parallelized by the second parallelizer 353 and then serialized by the second serializer 355. This is to generate a signal having a preset phase difference from the sampling signal. The second parallelizer 353 may generate a second parallel signal by sampling the sampling signal at each active transition having a predetermined phase difference from each active transition of the multi-phase clock. The second serializer 355 restores the second parallel signal to a sampling delay signal in series. For example, when using a multi-phase clock with odd stages, a sampling signal can be sampled at each active transition (rising edge of the clock shown in FIG. 4) of the inverted multi-phase clock. Through this process, the sampling delay signal may have a preset phase difference from the sampling signal. As an example, referring to FIG. 4, the sampling delay signal has the same shape as the sampling signal and has a phase difference of 0.5 UI.

 The second simulation delay unit 370 receives the sampling signal and delays the sampling signal by the delay time of the second parallel unit 353 and the second serializer 355.

The acceleration signal generator 340 improves the frequency synchronization speed of the reference clock signal by using the sampling signal output from the sampling unit 310 and the first simulation delay signal output from the first simulation delay unit 330. Generate an acceleration signal. The acceleration signal is input to the frequency controller 390 and used to adjust the frequency of the reference clock signal. The present invention further includes an acceleration signal generation unit 340, thereby further shortening the time required for the phase and frequency of the reference clock signal to be synchronized with the phase and frequency of the input data. A detailed operation of the acceleration signal generator 340 will be described later with reference to FIG. 5.

The phase detector 380 generates a pulse train by using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal. More specifically, the phase detector 380 generates a positive pulse PD_UP that is proportional to the phase difference between the sampling signal and the first simulation delay signal, and is negative in proportion to the phase difference between the sampling delay signal and the second simulation delay signal. Generates a pulse of PD_DN. Referring to the exemplary embodiment illustrated in FIG. 4, the positive pulse has a pulse width equal to the phase difference between the sampling signal and the first simulation delay signal. In addition, since the delay time between the sampling delay unit 350 and the second simulation delay unit 350 is the same, except for the delay time, a negative pulse corresponding to the phase difference between the sampling delay signal and the second simulation delay signal is It will always have a pulse width of 0.5 UI.

Positive and negative pulses are input to the frequency controller 390 to adjust the frequency as described above. Since the operation in the frequency adjusting unit 390 is the same as described above, a description thereof will be omitted.

The phase and frequency synchronization operation described above assumes that the frequency of the reference clock signal is sufficiently high that the types of input data are normally sampled by the sampling units 110 and 310 and the sampling delay units 150 and 350.

However, in the initial reset state, since the frequency adjusting units 190 and 390 are set to the lowest frequency at which they can operate, the sampling signal cannot normally sample the type of input data as shown in the timing diagram of FIG. The transition of the input data is lost. In this case, according to the phase frequency detection method of the present invention, the positive pulse generated by the sampling signal and the first simulation delay signal is continued until the rising edge of the next sampling signal occurs. That is, when the frequency of the reference clock signal is lower than the data transmission rate, the present invention generates a pulse train with a polarity that raises the frequency of the reference clock signal. Synchronous operation is possible.

The present invention may further include acceleration signal generators 140 and 340 for further improving the frequency synchronization speed by using the above-described features. Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 5 to 7. The operation of the acceleration signal generator according to the present invention will be described.

5 is a block diagram of an acceleration signal generator according to an embodiment of the present invention, FIG. 6 is a circuit diagram of an acceleration signal generator according to an embodiment of the present invention, and FIG. 7 is an acceleration signal generator according to an embodiment of the present invention. A timing diagram for explaining the operation.

Referring to FIG. 5, the acceleration signal generator 340 according to an embodiment of the present invention includes a first counter 341, a second counter 345, and a signal generator 347.

The first counter 341 counts the number of active transitions of the sampling signal, and the second counter 345 counts the number of active transitions of the first simulation delay signal. N-bit counters may be used as the first counter and the second counter, and the counter of the present invention is not limited to have a specific number of bits.

When the number of active transitions of the sampling signal reaches a preset number, the signal generator 347 shifts the value of the acceleration signal to 1, and when the number of active transitions of the first simulation delay signal reaches a preset number of times, The value of the acceleration signal is shifted to zero.

FIG. 6 illustrates an example in which the 3-bit counters 610 and 650 are used as the first and second counters of the acceleration signal generator, and the AND gates 630 and 670 and the D-flip flop 690 are used as the signal generator. 7 is a timing diagram according to the embodiment of FIG. 6.

First, each 3-bit counter receives the first simulation delay signal and the sampling signal, and counts up the counter on the rising edge of each signal. When the output value of the first counter 610, which receives the first simulation delay signal, reaches 7, the maximum value of the 3-bit counter, the D-flip flop 690 of the last stage is triggered to output the acceleration signal 1. When the output value of the second counter 650 receiving the sampling signal becomes 6, which is one smaller than the maximum value, the D-flip-flop 690 is reset to output the acceleration signal 0 and reset the first and second counters. . The reason why the operation value of the second counter 650 is set to be one less than the maximum value of the first counter 610 is 7 because the phase of the first simulation delay signal is always faster than the phase of the sampling signal. This is because the number of active transitions of the sampling signal is equal to or less than n-1 while n is active.

The acceleration signal is transmitted to the charge pump 193 to increase the control voltage in proportion to the current corresponding to the pulse width, thereby raising the frequency of the reference clock signal. Therefore, the acceleration signal generators 140 and 340 may perform the reference clock signal until the frequency of the reference clock signal sufficiently covers the data transmission rate, that is, until the sampling units 110 and 310 normally restore the input data. By increasing the frequency of the reference clock signal, it is possible to reach the range within which the phase detection operation is possible.

Hereinafter, a phase frequency detection method according to an embodiment of the present invention will be described with reference to FIGS. 8 to 10.

8 is a flow chart for explaining the overall flow of the phase frequency detection method according to an embodiment of the present invention, Figure 9 is a flow chart for explaining in detail the pulse train generation process of the phase frequency detection method according to an embodiment of the present invention 10 is a flowchart illustrating a frequency adjustment process of a reference clock signal in a phase frequency detection method according to an embodiment of the present invention.

Referring to FIG. 8, first, the input data is sampled at an active transition of the reference clock signal to generate a sampling signal, and the first simulation delay signal is generated by delaying the input data by a delay time in the sampling signal generation step. (830). Next, using the sampling signal, a sampling delay signal having a predetermined phase difference from the sampling signal is generated (850), and a second simulated delay signal in which the sampling signal is delayed by a delay time in the sampling delay signal generation step is generated. (870). In operation 880, a pulse train is generated using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal. The frequency of the reference clock signal is adjusted 890 using the generated pulse train.

An embodiment of the pulse train generation process 880 will be described with reference to FIG. 9 to generate 888 a positive pulse having a pulse width proportional to a phase difference between a sampling signal and a first simulation delay signal, and sampling delay signal. And a negative pulse having a pulse width proportional to the phase difference of the second simulation delay signal.

In addition, referring to FIG. 10, an embodiment of adjusting a frequency of a reference clock signal using a pulse train 890 will be described with reference to FIG. 10. A control voltage corresponding to the change may be generated 895, and the frequency of the reference clock signal 897 may be adjusted in response to the change of the control voltage.

In addition, although not shown in the drawing, when the reference clock signal is a multi-phase clock, in another embodiment of the sampling signal generation process 810, the first parallel signal is generated by sampling input data at each active transition of the multi-phase clock. The sampling signal may be generated by reconstructing the first parallel signal into a sampling signal in series. In addition, when the reference clock signal is a multi-phase clock, in another embodiment of the sampling delay signal generation process 850, a second parallel signal may be obtained by sampling a sampling signal at an active transition having a predetermined phase difference from each active transition of the multi-phase clock. The signal may be generated, and the sampling delay signal may be generated by restoring the second parallel signal to the sampling delay signal in series.

11 is a flowchart illustrating a phase frequency detection method including an acceleration signal generation process according to an embodiment of the present invention, and FIG. 12 illustrates an acceleration signal generation process among the phase frequency detection methods according to an embodiment of the present invention. This is a flowchart for explaining in detail.

Referring to FIG. 11, a sampling signal is generated 1110 by sampling input data in an active transition of a reference clock signal, and a first simulation delay signal is generated in which the input data is delayed by a delay time in the sampling signal generating step ( 1130). Next, a sampling delay signal having a predetermined phase difference from the sampling signal is generated 1150 by using the sampling signal. More specifically, the sampling delay signal may be generated 1150 by sampling the sampling signal such that the sampling signal and the sampling delay signal have a phase difference of 0.5 UI (Unit Interval). In operation 1160, a second simulation delay signal in which the sampling signal is delayed by the delay time in the sampling delay signal generation step is generated.

Next, a pulse train is generated 1170 using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal, and the frequency of the reference clock signal is obtained using the sampling signal and the first simulation delay signal. An acceleration signal for improving the synchronization speed is generated 1180. The frequency of the reference clock signal is adjusted 1190 using the generated pulse train and the acceleration signal.

In one embodiment of the acceleration signal generation process 1180, the number of active transitions of the sampling signal is counted 1181 and the number of active transitions of the first simulation delay signal is counted 1183. Next, when the number of active transitions of the sampling signal reaches the preset number of times, the value of the acceleration signal is shifted to 1185. When the number of active transitions of the first simulation delay signal reaches the preset number of times, The value transitions to 0 (1187). Although not shown in the figure, the frequency of the reference clock signal is input by translating the acceleration signal value to 0 (1187) and simultaneously counting again the number of active transitions of the sampling signal and the first simulation delay signal from zero. The acceleration signal can be generated repeatedly until it is synchronized to the data transmission speed.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, But the present invention is not limited thereto.

Claims (14)

A sampling signal generation step of sampling input data at an active transition of the reference clock signal to generate a sampling signal;
Generating a first simulation delay signal in which the input data is delayed by a delay time in the sampling signal generation step;
A sampling delay signal generating step of generating a sampling delay signal having a preset phase difference from the sampling signal by using the sampling signal;
Generating a second simulation delay signal in which the sampling signal is delayed by a delay time in the sampling delay signal generating step;
Generating a pulse train by using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal; And
A frequency adjusting step of adjusting a frequency of the reference clock signal using the pulse train
Phase frequency detection method comprising a.
The method of claim 1,
The pulse train generation step,
Generating a positive pulse having a pulse width proportional to a phase difference between the sampling signal and the first simulation delay signal; And
Generating a negative pulse having a pulse width proportional to a phase difference between the sampling delay signal and the second simulation delay signal;
Phase frequency detection method comprising a.
The method of claim 1,
The sampling delay signal generation step,
And sampling the sampling signal such that the sampling signal and the sampling delay signal have a phase difference of 0.5 UI (Unit Interval).
The method of claim 1,
If the reference clock signal is a multi-phase clock,
The sampling signal generating step,
Sampling the input data at each active transition of the multi-phase clock to generate a first parallel signal; And
Restoring the first parallel signal to a sampling signal in series;
The sampling delay signal generation step,
Sampling the sampling signal at an active transition having a preset phase difference with each active transition of the multi-phase clock to generate a second parallel signal; And
Restoring the second parallel signal to a sampling delay signal in series;
Phase frequency detection method comprising a.
5. The method according to any one of claims 1 to 4,
And generating an acceleration signal by using the sampling signal and the first simulation delay signal to generate an acceleration signal for improving the frequency synchronization speed of the reference clock signal.
The frequency adjustment step,
And adjusting the frequency of the reference clock signal using the pulse train and the acceleration signal.
The method of claim 5,
The accelerating signal generating step,
Counting the number of active transitions of the sampling signal;
Counting the number of active transitions of the first simulation delay signal;
Shifting the value of the acceleration signal to 1 when the number of active transitions of the sampling signal reaches a preset number; And
Translating the value of the acceleration signal to zero when the number of active transitions of the first simulation delay signal reaches a preset number;
Phase frequency detection method comprising a.
The method of claim 1,
The frequency adjustment step,
Pumping charge proportional to the pulse width of the pulse train;
Generating a control voltage corresponding to the change in the pumped charge amount; And
Adjusting a frequency of the reference clock signal in response to a change in the control voltage
Phase frequency detection method comprising a.
A sampling unit for sampling the input data at an active transition of the reference clock signal to generate a sampling signal;
A first simulation delay unit generating a first simulation delay signal in which the input data is delayed by a delay time in the sampling unit;
A sampling delay unit configured to generate a sampling delay signal having a predetermined phase difference from the sampling signal by using the sampling signal;
A second simulation delay unit which generates a second simulation delay signal in which the sampling signal is delayed by a delay time in the sampling delay unit;
A phase detector generating a pulse train using the sampling signal, the first simulation delay signal, the sampling delay signal, and the second simulation delay signal; And
A frequency adjusting unit adjusting the frequency of the reference clock signal using the pulse train
Phase frequency detection device comprising a.
9. The method of claim 8,
The phase detector,
Phase frequency detection, generating a positive pulse proportional to the phase difference between the sampling signal and the first simulation delay signal, and generating a negative pulse proportional to the phase difference between the sampling delay signal and the second simulation delay signal Device.
9. The method of claim 8,
The sampling delay unit,
And sampling the sampling signal such that the sampling signal and the sampling delay signal have a phase difference of 0.5 UI (Unit Interval).
9. The method of claim 8,
If the reference clock signal is a multi-phase clock,
The sampling unit,
A first parallelizer for sampling the input data at each active transition of the multi-phase clock to produce a first parallel signal; And
A first serializer for restoring the first parallel signal into a sampling signal in series;
The sampling delay unit,
A second parallelizer for generating a second parallel signal by sampling the sampling signal at an active transition having a preset phase difference with each active transition of the multi-phase clock; And
A second serial device for restoring the second parallel signal to a sampling delay signal in series;
Phase frequency detection device comprising a.
The method according to any one of claims 8 to 11,
And an acceleration signal generator configured to generate an acceleration signal for improving a frequency synchronization speed of the reference clock signal by using the sampling signal and the first simulation delay signal.
The frequency control unit,
And adjusting the frequency of the reference clock signal using the pulse train and the acceleration signal.
The method of claim 12,
The acceleration signal generator,
A first counter that counts the number of active transitions of the sampling signal;
A second counter that counts the number of active transitions of the first simulation delay signal; And
When the number of active transitions of the sampling signal reaches a preset number, the value of the acceleration signal is shifted to 1, and when the number of active transitions of the first simulation delay signal reaches a preset number, the value of the acceleration signal is changed. Signal generator to transition to zero
Phase frequency detection device comprising a.
9. The method of claim 8,
The frequency control unit,
A charge pump for pumping charges proportional to the pulse width of the pulse train;
A loop filter for generating a control voltage corresponding to the change in the pumped charge amount; And
A voltage controlled oscillator for adjusting the frequency of the reference clock signal in response to the change of the control voltage
Phase frequency detection device comprising a.

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