KR100514748B1 - Direct Memory Access method and apparatus using SOF signal of USB - Google Patents

Abstract

Disclosed are a direct memory access (DMA) method and apparatus using a frame start signal of a general purpose serial bus. This method of receiving data from a device receiving data from a host via a universal serial bus and storing the data in a memory includes determining whether DMA is required while DMA is capable, and determining that DMA is not required. If the counting result is determined to be a predetermined time, and if the counted result is determined not to be a predetermined time, determining whether the DMA is required And counting results are reset when DMA is performed. Therefore, since the DMA can check the time for which the DMA is not required by using the periodically generated frame start signal, the central processing unit eliminates the need to poll the memory access device directly, thereby reducing the burden on the central processing unit as well as inside the device. In order to improve the performance of the overall system, such as not consuming hardware resources, and to eliminate the need for an internal timer, there is an effect of reducing the manufacturing cost and the volume of the product.

Description

Direct memory access method and apparatus using frame start signal of general purpose serial bus {Direct Memory Access method and apparatus using SOF signal of USB}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to direct memory access (DMA), which is one of data access methods. In particular, the present invention relates to a direct memory using a start of frame (SOF) signal of a universal serial bus (USB). It relates to an access method and apparatus.

Hereinafter, a conventional direct memory access method will be described as follows.

If the number of operations of direct memory access is known to the direct access device that performs the direct memory access method, it can be directly accessed from the outside through the input / output (I / O) port while direct memory access can be performed. When the memory access is required, the conventional direct memory access method terminates the direct memory access after performing the direct memory access for a predetermined number of operations.

However, if the number of operations is not known to the direct memory access device, if there is no request for direct memory access from the outside through the input / output port for a predetermined time, the conventional direct memory access method terminates the direct memory access.

At this time, in the conventional direct memory access method, a direct memory access control apparatus (not shown) which allows a central processing unit (not shown) to control direct memory access in order to know whether a time for which there is no request for direct memory access has elapsed. ) To continue polling. Therefore, not only does it increase the burden of the central processing unit that controls the overall device (not shown) for providing data that is directly targeted for memory access, but also consumes internal hardware and occupies an internal bus such as the overall system performance. There is a problem of lowering.

In order to prevent this, the conventional direct memory access method may provide an internal timer (not shown) instead of using a central processing unit to check the passage of a predetermined time. However, when providing the internal timer, there is a problem that the manufacturing cost increases and the volume of the product increases.

An object of the present invention is to start the frame of a general-purpose serial bus that can measure the time when the direct memory access operation is not performed using the frame start signal of the general-purpose serial bus without knowing the number of operations of the direct memory access To provide a direct memory access method using a signal.

Another object of the present invention is to provide a frame of a general-purpose serial bus that can measure the time when a direct memory access operation is not performed by using a frame start signal of a general-purpose serial bus without knowing the number of direct memory access operations. It is to provide a direct memory access device using the start signal.

In order to achieve the above object, a direct memory access method according to the present invention for inputting data from a device that receives data through a universal serial bus from a host and storing the data in a memory includes a method of DMA in a state where direct memory access (DMA) can be performed. (A) determining whether the execution is required; if it is determined that the DMA is not required, performing counting using a periodically generated frame start signal; and (b) performing the counting and the counted result is a predetermined time. If it is determined that the counting result is not the predetermined time, the process proceeds to step (a) (c), and the counting result is preferably reset when the DMA is performed. .

In order to achieve the above object, a direct memory access device according to the present invention for inputting data from a device receiving data through a universal serial bus from a host and storing the data in a memory includes a DMA in a state where direct memory access (DMA) can be performed. And a DMA request checker that generates the checked result as a first control signal, and performs or counts in response to a periodically generated frame start signal in response to the first control signal. A counting unit for resetting a result, outputting a counted result, and a first comparison unit comparing the counted result input from the counting unit with a predetermined time and outputting the compared result as a DMA end signal; The request checker checks whether the DMA is required to be performed in response to the DMA end signal. It is preferable.

Hereinafter, a direct memory access (DMA) method using a frame start signal of a general purpose serial bus according to the present invention will be described with reference to the accompanying drawings.

1 is a flowchart illustrating a direct memory access method using a frame start signal of a general-purpose serial bus according to the present invention, and determining whether DMA is required to be performed in a state where a DAM can be performed (10th and 12th). Steps), checking whether a predetermined time has elapsed by using a frame start (SOF) signal (steps 14 and 16), performing a DAM, and determining whether DMA has been performed a predetermined number of times, and counting the result. And a reset step (18th to 24th steps). The frame start signal is preferably a USB frame signal.

FIG. 2 is an exemplary schematic block diagram of a periphery, including a DMA device for explaining the DMA method shown in FIG. 1, including a host 40, a device 42, and a universal serial bus (USB) 44. , DMA device 46 and memory 48.

At this time, at least one of the DMA device 42 and the memory 48 may be provided inside the device 42, as shown in FIG.

The device 42 shown in FIG. 1 receives data from the host 40 via a universal serial bus (USB) 44, and the DMA device 46 transmits data from the host 40 to the device 42. Is input from the device 42 and stored in the memory 48. Here, the host 40 refers to a personal computer (not shown), and the device 42 refers to a peripheral device, such as a printer, that receives and processes data from the personal computer. In other words, the DMA device 46 inputs data input from the host 40 to the device 42 via the universal serial bus 44 via the bus 60, and inputs data input via the bus 60. Output to memory 48 via bus 62. The device 42 described above can be a printer. In this case, the device 42 receives the printing data from the host 40 through the universal serial bus 44 by the universal serial bus protocol, interprets and converts the received printing data, and the DMA device 46 sends the device. The result processed at 42 is stored in the memory 48.

The DMA method according to the present invention determines whether DMA is required to be performed in a state where direct memory access (DMA) can be performed (10th and 12th steps). For example, it is determined whether the DMA is capable of performing (step 10). The DMA-capable state means a state in which the DAM device 46 is ready to perform DMA, such as supplying power to the DMA device 46 that performs DMA. If it is determined that the DMA is not in an executable state, the flow proceeds to step 10. However, if it is determined that the DMA can be performed, it is determined whether the DMA is required (step 12). In this case, a command for requesting to perform DMA may be provided through a signal line 64 from a central processing unit (not shown) that controls the first half of the device 42.

If it is determined that the DMA is not required, counting is periodically performed using a frame start (SOF) signal generated in units of 1 ms (step 14). Here, the SOF signal is generated in the device 42 by combining D + and D-, which are data transmitted from the host 40 to the device 42, and the device 42 uses the SOF signal to generate a multiplicity of audio or video. Synchronize media data. That is, the SOF signal is generated when a plurality of devices 42 connected to the host 40 by the general purpose serial bus 44, that is, a plurality of devices 42 such as a mouse (not shown), a printer (not shown), or the like. When connected to the host 40 through the universal serial bus 44 is a signal required for managing the work schedule of the plurality of devices 42. In general, general purpose serial bus 44 consists of four signal lines, two data signal lines, D + and D-, a power line and a ground line.

After step 14, it is determined whether the counted result is a predetermined time (step 16). If it is determined that the counted result is not a predetermined time, the flow proceeds to step 12. However, if it is determined that the counted result is a predetermined time, the DMA method shown in Fig. 1 ends because no DMA has been performed for a predetermined time. At this time, if DMA is performed during counting, the counted result is reset. That is, when the DMA is not required to perform the counting operation using the SOF signal, when the DMA is performed, the counting operation is performed again from the beginning.

The details are as follows. The DMA method illustrated in FIG. 1 may further prepare 18 th to 24 th steps. If it is determined that the performance of the DMA is required, the DMA is performed (step 18). After the eighteenth step, it is determined whether the DMA has been performed a predetermined number of times (steps 20 and 22). At this time, if it is determined that DMA has been performed a predetermined number of times, the serial memory access (DMA) method shown in FIG. 1 is terminated. However, if it is determined that DMA has not been performed a predetermined number of times, the flow proceeds to step 24.

According to an embodiment of the present invention, as shown in FIG. 1, after the eighteenth step, the predetermined number of times is decreased by one (step 20). After step 20, it is determined whether the reduced result is 0 (step 22). If it is determined that the reduced result is 0, since the DMA has been performed a predetermined number of times, the direct memory access method shown in FIG. 1 ends. However, if it is determined that the reduced result is not 0, the process proceeds to step 24 since DMA has not been performed a predetermined number of times.

According to another embodiment of the present invention, unlike FIG. 1, after the eighteenth step, the predetermined number of times is increased by one. At this time, it is determined whether the increased result is a predetermined number. If it is determined that the increased result is a predetermined number of times, since the DMA is performed a predetermined number of times, the direct memory access method shown in FIG. 1 ends. However, if it is determined that the increased result is not the predetermined number of times, the flow proceeds to step 24.

If it is determined that DMA has not been performed a predetermined number of times, the result counted in step 14 is reset and the process proceeds to step 12 (step 24). As such, the counted result in step 14 is reset every time the DMA is performed, so the counted result in step 14 corresponds to the counted result for the time when the DMA is not performed.

Hereinafter, a configuration and operation of a direct memory access device using a frame start signal of a general purpose serial bus according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an embodiment of a DMA device according to the present invention, in which a DMA request checker 80, a counting unit 82, a first comparing unit 84, a DMA unit 86, and a second comparing unit 88 are provided. It is composed of

The DMA device shown in FIG. 3 may correspond to a block diagram of one preferred embodiment 46A of the present invention of the DMA device 46 shown in FIG. In this case, the DMA device 46A receives data from the device 42 which has received data from the host 40 via the universal serial bus 44 and stores it in the memory 48. In addition, the DMA device 46A shown in FIG. 3 serves to perform the DMA method shown in FIG.

In order to perform the tenth and twelfth steps shown in FIG. 1, the DMA device 46A provides a DMA request check unit 80. Here, the DMA request checker 80 checks whether or not direct memory access (DMA) is executable to perform the tenth step, checks whether the DMA is required to perform the twelfth step, and checks The result is generated as the first control signal C1 and output to the counting unit 82 and the DMA unit 86, respectively. To this end, the DMA request checker 80 may generate the first control signal C1 by checking whether the DMA request signal for requesting DMA is input from the above-described central processing unit (not shown) through the input terminal IN1.

At this time, in order to perform the fourteenth step, the counting unit 82 responds to the first control signal C1 input from the DMA request check unit 80, and the frame input from the device 42 through the input terminal IN2. In response to the start signal, counting is performed or the counted result is reset, and the counted result is output to the first comparator 84. For example, when it is recognized that the DMA is not required while the DMA is able to be performed through the first control signal C1, the counting unit 82 performs a counting operation in response to the frame start signal input through the input terminal IN2. Perform. However, if it is recognized that the DMA is to be performed through the first control signal C1 after starting counting, the counting unit 82 resets the counted result.

In order to perform the sixteenth step, the first comparison unit 84 compares the counted result input from the counting unit 82 with a predetermined time input through the input terminal IN3, and compares the result as a DMA end signal. While outputting to the request checker 80, an output through the output terminal OUT1, such as a separate DAM control core (not shown) that directly controls memory access. At this time, the DMA request checker 80 checks whether DMA performance is required in response to the DMA end signal input from the first comparator 84. For example, if it is recognized that the result counted through the DMA end signal is not a predetermined time, the DMA request checker 80 checks whether the DMA is required to be performed. In addition, the DMA control core (not shown) may terminate the DMA method illustrated in FIG. 1 by inputting a DMA termination signal output through the output terminal OUT1. For example, if it is recognized that the result counted through the DMA end signal is a predetermined time, the DMA control core (not shown) terminates the DMA method shown in FIG.

Meanwhile, in order to perform the eighteenth step shown in FIG. 1, the DMA unit 86 of the direct memory access device 46A receives the DMA in response to the first control signal C1 input from the DMA request check unit 80. Perform. For example, if it is recognized that the DMA is required to be performed in the state where the DMA can be performed through the first control signal C1, the DMA unit 86 receives the input terminal IN4 from the device 42 via the bus 60. Data is input, and the input data is output to the memory 48 through the output terminal OUT2 to perform DMA.

In order to perform the twentieth and twenty-second steps, the second comparison unit 88 compares the number of times the DMA input from the DMA unit 86 is performed with a predetermined number of times, and compares the result with the second control signal C2. As an output to the counting unit 82, the output is output through the output terminal OUT3 to the aforementioned DMA control core. To this end, the DMA unit 86 may count a number of times the DMA is performed, and separately provide a counter (not shown) that outputs the counted result to the second comparator 88 as the number of times the DMA is performed. In this case, the counting unit 82 counts the result in response to the first control signal C1 input from the DMA request check unit 80 and the second control signal C2 input from the second comparing unit 88. Reset For example, when it is recognized that the DMA is performed through the first control signal C1 and the number of times the DMA is performed through the second control signal C2 is recognized as not being a predetermined number, the counting unit 82 counts. Resets the result. In this case, the DMA control core (not shown) may terminate the DMA method illustrated in FIG. 1 in response to the second control signal C2 output through the output terminal OUT3. For example, if it is recognized that the DMA has been performed a predetermined number of times through the second control signal C2, the DMA control core may terminate the DMA method illustrated in FIG. 1.

As described above, since the direct memory access method and apparatus using the frame start signal of the general-purpose serial bus according to the present invention can check the time when the direct memory access is not required by using the frame start signal which is periodically generated. By eliminating the need for the central processing unit to poll the memory access devices directly, the central processing unit not only reduces the burden on the central processing unit, but also improves the overall system performance by not consuming hardware resources inside the device, eliminating the need for internal timers. This can reduce the manufacturing cost and reduce the volume of the product.

1 is a flowchart illustrating a direct memory access method using a frame start signal of a general-purpose serial bus according to the present invention.

FIG. 2 is an exemplary schematic block diagram of its periphery, including a DMA device for explaining the DMA method shown in FIG.

3 is a block diagram of an embodiment of a DMA device according to the present invention.

Claims (5)

In the direct memory access method for inputting the data from the device receiving the data through the universal serial bus from the host and storing in the memory, (a) determining whether DMA is required to be performed in a state where direct memory access (DMA) can be performed; (b) if it is determined that the performance of the DMA is not required, performing counting using a periodically generated frame start signal (USB Frame signal); And (c) determining whether the counted result is a predetermined time, and if it is determined that the counted result is not the predetermined time, proceeding to step (a); And the counted result is reset when the DMA is performed. The method of claim 1, wherein the direct memory access method is (d) if it is determined that performance of the DMA is required, performing the DMA; (e) determining whether the DMA has been performed a predetermined number of times; And and (f) if it is determined that the DMA has not been performed the predetermined number of times, resetting the counted result and proceeding to step (a). Memory access method. The method of claim 1, wherein step (e) After step (d), decreasing the predetermined number of times by one; And If it is determined that the reduced result is 0, and the determined result is determined to be 0, the direct memory access method is terminated, and if it is determined that the reduced result is not 0, the process proceeds to step (f). And a frame start signal of a general-purpose serial bus. In a direct memory access device that receives the data from a device that receives data from the host via a universal serial bus, and stores the data in a memory, A DMA request checker which checks whether DMA is required to be performed in a state where direct memory access (DMA) can be performed, and generates the checked result as a first control signal; A counting unit configured to perform a counting or reset a counted result in response to a periodically generated frame start signal in response to the first control signal, and output a counted result; And A first comparison unit which compares the counted result inputted from the counting unit with a predetermined time and outputs the compared result as a DMA end signal; And the DMA request checker checks whether the DMA is required to be performed in response to the DMA end signal. The apparatus of claim 4, wherein the direct memory access device A DMA unit configured to perform the DMA in response to the first control signal; And And a second comparing unit which compares the number of times the DMA is performed with a predetermined number of times and outputs the compared result as a second control signal. And the counting unit resets the counted result in response to the first and second control signals.