JP2000276437A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a DMA controller which efficiently performs DMA transfer by detecting the use condition of a shared bus and changing the transfer method in accordance with the detection result. SOLUTION: The access condition to a bus 5 of DMA control parts 1 and 2 requiring the real-time processing is detected by a bus monitor part 8. The transfer method of DMA transfer between DMA control parts 1 to 3 and a memory 7 is changed on the basis of this detection result. Thus, DMA transfer between DMA control parts 1 to 3 and the memory 7 is performed very efficiently without exerting adverse influence on the real-time processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to direct memory access control (hereinafter, also referred to as "DMA control"). More specifically, the present invention relates to a DMA control device capable of efficiently performing DMA transfer between a plurality of devices connected to a shared bus and a memory. For example,
It is suitable for use in a device such as a copying machine that shares a bus between devices that require real-time processing (scanners, printers and the like) and devices that do not need real-time processing (hard disks and the like).

[0002]

2. Description of the Related Art A known DMA control device includes a bus arbitration unit for arbitrating a bus access when a plurality of devices request a bus access. FIG. 6 shows an example of the system. FIG.
Basically, the system shown in FIG.
DMA control units 101 to 103 and the access control unit 104 perform data transfer by accessing the memory 107 via the shared bus 105, having A control units 101, 102, 103 and an access control unit 104. It is. A bus arbitration unit 106 for arbitrating access to the bus 105 from each of the DMA control units 101 to 103 and the access control unit 104 is provided. Also, DMA
A printer 111 is connected to the control unit 101,
A scanner unit 112 is connected to the A control unit 102,
A hard disk 113 is connected to the MA control unit 103, and a CPU 114 is connected to the access control unit 104.

[0003] This system operates as follows. This operation will be described with reference to FIG. For example, DMA
When the control unit 101 needs to access the bus 105, the DMA control unit 101 outputs a request signal req1 to the bus arbitration unit 106. This request signal re
In response to q1, the bus arbitration unit 106 returns a bus use permission signal ack1 if possible. While the permission signal ack1 is active, the printer device 111 can access the bus 105 via the DMA control unit 101. The same applies to other control units (devices).

Here, when there are requests from a plurality of control units at the same time, the bus arbitration unit 106 returns a bus use permission signal according to a predetermined priority. FIG. 8 shows an example of the priority order. In the case of this priority, the request signals req1, r
When eq2, req3, and req4 are output simultaneously, the bus arbitration unit 106 sets the bus use permission signal ack1 having the highest priority.
Only reply. Accordingly, the DMA control unit 101 accesses the bus 105 with priority over the other control units 102 to 104. Similarly, when the request signals req2, req3, and req4 are simultaneously output, the bus arbitration unit 106 returns only the bus use permission signal ack2 having the highest priority among them. For this reason, the DMA control unit 102
The bus 105 is accessed with higher priority than 3, 104.

When each of the DMA controllers 101 to 103 accesses the bus 105, various data are transferred to the CPU 114.
Without going through each of the DMA control units 101 to 103 and the memory 1
07, data transfer, that is, DMA transfer is performed. In this DMA transfer, a printer device or a scanner device needs to perform real-time processing, and in the case of large-capacity data transfer, one process requires a long period of time, and there is a possibility that real-time processing cannot be performed in time. It is performed by repeating the process in small capacity units.

As a method for performing data transfer in a large capacity unit, as described in Japanese Patent No. 2536415, when a high-priority process (real-time process) is requested during DMA transfer, In some cases, the DMA transfer is temporarily stopped, the progress of the DMA transfer is held, and the DMA transfer is continued after the high-priority processing is performed. However, realizing such a transfer method is complicated and not a practical method. For this reason, a transfer method of repeatedly transferring data in small capacity units is generally adopted.

[0007]

However, in the above-described conventional DMA control device 100, since transfer is always performed in small capacity units, there is a problem that transfer efficiency is poor. By the way, in order to improve the transfer efficiency, it is only necessary to transfer data collectively in a large capacity unit of several kilobytes, but if a large amount of data is transferred at one time, the processing takes a long time. For this reason, when transferring in large capacity units,
There is a possibility that the DMA transfer that requires real-time processing cannot be made in time or the processing in the CPU 114 cannot be made in time.

Accordingly, the present invention has been made to solve the above-mentioned problem, and by performing transfer by a transfer method according to the use state of the shared bus, DMA can be efficiently performed.
It is an object to provide a DMA control device capable of performing transfer.

[0009]

According to a DMA control apparatus of the present invention, a memory, a shared bus connected to the memory, and the memory connected to the shared bus are provided. A plurality of devices accessing the shared bus, bus monitoring means for detecting a use status of the shared bus by the devices, and DMA transfer between at least one of the devices and the memory based on a detection result of the bus monitoring means. Transfer method changing means for changing the transfer method.

In this DMA control device, the use status of the shared bus is detected by the bus monitor means. Then, the transfer method changing means changes the transfer method of the DMA transfer between each device and the memory based on the detection result of the bus monitor means. As a result, data transfer is performed between each device and the memory by an optimum transfer method according to the use state of the shared bus. Therefore, DMA transfer is performed efficiently. Further, a situation in which the real-time processing cannot be made in time or the processing in the CPU cannot be made in time can be reliably avoided.

In the DMA control device according to the present invention, the plurality of devices include those requiring real-time processing and those not requiring such real-time processing. It is preferable to detect an operation situation.

Devices in the DMA controller include those that require real-time processing and those that do not. And the bus monitor means
The operating status of the device that requires real-time processing is detected. This is because the bus monitor detects the use status of the shared bus, so that the bus monitor can detect whether or not a device that requires real-time processing is accessing the shared bus (the device is operating). You can. Then, the transfer method of the DMA transfer between each device and the memory is changed by the transfer method changing unit in accordance with the operation state of the device that requires real-time processing. As a result, data is transferred between each device and the memory by an optimal transfer method according to the operation state of the device that requires real-time processing. Therefore, DMA transfer is performed efficiently. Further, a situation in which the real-time processing cannot be made in time or the processing in the CPU cannot be made in time can be reliably avoided.

Further, in the DMA control device according to the present invention, it is more preferable that the transfer method changing means changes a transfer word unit of DMA transfer between at least one of the devices and the memory.

In this DMA control device, the transfer method unit changes the transfer word unit of the DMA transfer between the device and the memory according to the detection result of the bus monitor unit. For example, the transfer word unit of the DMA transfer is changed from a small capacity unit to a large capacity unit, or vice versa. That is, when real-time processing is required, the transfer method is changed so that the DMA transfer is performed by the transfer method in small-capacity units, and when the real-time processing is not necessary, the DMA transfer is performed by the transfer method in large-capacity units. I just need. Thus, extremely efficient DMA transfer is performed within a range that does not affect real-time processing.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a DMA controller according to the present invention; The present embodiment relates to a DMA control device that controls access of each device to a bus in a copying machine. As shown in FIG. 1, the DMA controller 10
DMA control units 1, 2, 3, and 3, an access control unit 4, and a bus monitor unit 8.
And the access control unit 4 accesses the memory 7 via the shared bus 5. Further, a bus arbitration unit 6 for arbitrating access to the bus 5 from each of the DMA control units 1 to 3 and the access control unit 4 and a bus monitoring unit 8 for detecting a use state of the bus 5 are provided. Also, DMA
A printer 11 is connected to the controller 1, a scanner 12 is connected to the DMA controller 2, and a DMA controller 3 is connected to the controller 11.
Is connected to the hard disk 13 and the access control unit 4
Is connected to the CPU 14. The CPU 14 controls the control of the entire copying machine including this system. The printer device 11, the scanner device 12, and the hard disk 13 are respectively DMA controllers 1, 2,
The data transfer can be performed by directly accessing the memory 7 without the intervention of the CPU 14 by the means 3 and 3.

The bus arbitration unit 6, as shown in FIG.
When the request signals req1, req2, req3, and req4 are output from the MA control units 1 to 3 and the access control unit 4, respectively, the bus use permission signals are appropriately sent to the DMA control units 1 to 3 and the access control unit 4. ack1, ack2, ack3, ack4 are returned. Here, the DMA control units 1 to 3 and the access control unit 4 simultaneously transmit the request signals req1 and req.
When 2, req3 and req4 are output, any one of the bus use permission signals ack1 to ack4 is transmitted based on the priority table (see FIG. 8) as in the conventional case.

The bus monitor section 8 detects the operation status of the printer device 11 and the scanner device 12 that require real-time processing. That is, as shown in FIG. 2, the bus use permission signal ack output from the bus arbitration unit 6
It counts the active period of 1, ack2. Then, a transfer method change signal CHT for changing the data transfer method based on the count result is transmitted to the DMA controller 3.
To be output. As shown in FIG. 3, the bus monitor 8 includes counters 21 and 22 and a delay flip-flop (Delay Flip-Flop, hereinafter referred to as “DF”).
F ”), 32, an adder 25, and a comparator 2
6. A bus use permission signal ack1 is input to a terminal EN of the counter 21, and a clock signal C is input to a terminal CLK.
S is input, and a counter clear signal CC is input to the terminal CLR.
S has been entered. On the other hand, from terminal Q, counter 21
Is output, and this is the DFF 31
Is input to the terminal IN. Also, the occupancy rate set signal SSS is input to the terminal CLK of the DFF 31 and the terminal O
The UT outputs the occupancy S1, which is input to the adder 25.

If the bus use permission signal ack1 input to the terminal EN is active at the rising of the clock signal CS input to the terminal CLK, the counter 21 counts up and counts the count value C1 to the terminal EN. The signal is output from Q and input to the terminal IN of the DFF 31. Then, when a counter clear signal CCS transmitted every predetermined period is input to the terminal CLK, the count value C1 is reset. Note that the counter 22 performs the same operation.

When the occupancy rate set signal SSS transmitted every predetermined cycle is input to the terminal CLK, the DFF 31
The count value C1 input from the counter 21 is output from the terminal OUT. That is, the DFF 31
Calculates the generation rate of the bus use permission signal ack1 in the input cycle of the occupancy rate set signal SSS, that is, the bus use rate of the DMA control unit 1. The DFF 32 performs the same operation, and the DFF 32 calculates the bus use ratio of the DMA control unit 2. Further, the clock signal CS, the counter clear signal CCS, and the occupancy rate set signal SSS are all generated inside the bus monitor 8.

The adder 25 calculates the sum of the bus occupancies S1 and S2 calculated by the DFFs 31 and 32. The comparator 26 compares the result calculated by the adder 25 with a comparison value (the comparison value in the present embodiment is “0”), and when the calculation result is equal to the comparison value, the DMA controller 3 is used to activate the transfer mode change signal CHT.

Next, switching of the state of the transfer mode change signal CHT (active / inactive) will be described with reference to FIG. FIG. 4 is a timing chart showing the states of various signals. In the present embodiment,
Both the occupancy rate setting signal SSS and the counter clear signal CCS are transmitted every 100 μs.
Immediately after the transmission of S (after 125 ns), the counter clear signal CC
S is transmitted. The clock signal CS is a signal having a period of 1 μs, and (clock signal CS)
X100 = (occupancy rate set signal SSS).

Before time t ₀ , the count value C
1 and C2 are both “0”. Also, as the bus occupancy rates S1 and S2 of the DMA control units 1 and 2, the value “15” read at the time of transmitting the previous occupancy rate set signal SSS is used.
“8” is input to the adder 25. Therefore, the adder 25 outputs “23” as the calculation result. Then, this output is input to the comparator 26. However, since the comparison value is not equal to “0”, it is determined that a device that requires real-time processing is operating. Therefore, the transfer method change signal CHT is inactive (Lo). Therefore, the data transfer method in the DMA control unit 3 is not changed, and the transfer is performed in small capacity units. Note that the bus occupancy ratio indicates a bus usage ratio at predetermined time intervals.

At time t ₀ , the clock signal C
S rises. However, at this time, the bus use permission signal ac
Since both k1 and ack2 are inactive (Lo), the counters 21 and 22 do not count up. Therefore, each of the count values C1 and C2 remains “0”. Further, the clock signal CS rises again at time t ₁ after 1 μs has elapsed from time t ₀ . However, since the bus use permission signals ack1 and ack2 are both inactive (Lo), the counters 21 and 22 do not count up. Therefore, each count value C
1, C2 remains "0". In addition, time t ₂ even clock signal CS which is 1μs elapsed from the time t ₁ rises again. However, since the bus use permission signals ack1 and ack2 are both inactive (Lo), the counters 21 and 22 are inactive.
2 does not count up. Therefore, each of the count values C1 and C2 remains “0”.

At time t ₃ 375 ns after time t ₂ , the occupancy rate set signal SSS is input to the DFFs 31 and 32, respectively. Then, DFF31 and 32 outputs the count value C1, C2 at time t ₃ when the bus occupation rate S1, S2. That is, “0” is output from the DFF 31 as the bus occupancy S1, and “0” is output from the DFF 32 as the bus occupancy S2. As described above, the count values C1 and C2 can be output as the bus occupancy ratios S1 and S2 in the present embodiment because the occupancy ratio set signal SSS and the counter clear signal CCS are output at a period of 100 μs to the DFFs 31 and 32 and the counters 21 and 22. This is because each is entered.

The bus occupancy rates S1 and S2 calculated in this way are input to the adder 25. Then, the adder 25 outputs “0” as a calculation result, and inputs it to the comparator 26. Since the comparator 26 determines that the comparison value is equal to “0”, the transfer method change signal CHT issued from the bus monitor 8 to the DMA controller 3 becomes active (Hi). While the transfer method change signal CHT is active (Hi), the DMA control unit 3 changes the transfer method of the DMA transfer.

Further, at time t ₄ (elapsed 500 ns from time t ₂ ) 125 ns after time t ₃ , counter clear signal CCS is input to counters 21 and 22. Thereby, the count value C of the counters 21 and 22 is obtained.
1 and C2 are both cleared to “0”.

[0027] rises again clock signal CS from time t ₄ at the time t ₅ has elapsed 500ns. However, the bus use permission signals ack1 and ack2 are inactive (Lo). Therefore, the counters 21 and 22 do not count up. Therefore, the respective count values C1, C2
Remain "0".

[0028] Then, at time t ₆ has elapsed 500ns from the time t _5, bus use permission signal ack1 is to become active (Hi). Then it rises again clock signal CS at the time t ₇ after a lapse 1μs from time t _5. Therefore, the counter 21 counts up. Therefore, the count value C1 is updated to "1". On the other hand, the bus use permission signal ack2 is inactive (Lo). Therefore, the counter 22 does not count up. Therefore, the count value C2 remains “0”.

Thereafter, the counters 21 and 22 count up in the same manner, and the occupancy rate set signal SSS
Are input to the DFFs 31 and 32, respectively, the occupancies S1 and S2 of the DMA control units 1 and 2 are calculated. And
According to the calculation result, the transfer method change signal CHT issued from the bus monitor 8 to the DMA controller 3 is made active (Hi) or inactive (Lo).

Next, a description will be given of the change of the data transfer method accompanying the switching of the transfer method change signal CHT between active (Hi) and inactive (Lo) with reference to FIG. FIG. 5 is a timing chart showing the request signal req3 and the bus use permission signal ack3 of the DMA control unit 3, the signals RAS and CAS for writing data to the DRAM in the memory 7, and the data length.

First, the state where the transfer method change signal CHT is inactive (Lo), that is, the state before time t ₃ will be described. Prior to time t ₃ , at least one of the DMA controllers 1 and 2 that perform the real-time processing is accessing the bus 5. In such a state, the request signal req3 (a) is sent from the DMA control unit 3.
Is issued, and the bus arbitration unit 6 issues a bus use permission signal ack3.
It is assumed that (a) is returned. Then, hard disk 1
DMA transfer between the memory 3 and the memory 7 is performed by transfer in units of 1 byte. Also, a request signal req3 (b) is issued from the DMA control unit 3, and the bus arbitration unit 6
The same is true when the bus use permission signal ack3 (b) is returned. The DMA controllers 1 and 2 and the memory 7
The DMA transfer is performed in the same manner as described above.

That is, while the transfer method change signal CHT is inactive (Lo), each of the DMA control units 1 to 3
The DMA transfer between the memory 7 and the memory 7 is performed in units of 1 byte, and the transfer requires a time of 5 clocks (625 ns). Since the DMA transfer is performed on a byte-by-byte basis, there is no adverse effect on the processing in the DMA controllers 1 and 2 that require real-time processing.

On the other hand, a state where the transfer method change signal CHT is active (Hi), that is, a state after time t ₃ will be described. After time t ₃ , the DMA controllers 1 and 2 that perform real-time processing are not accessing the bus 5. Time t ₃ request signal req3 from the DMA controller 3 (c) is issued toward the front and rear, the time t ₃
Thereafter, the bus arbitration unit 6 uses the bus permission signal ack3 (c).
Is returned. Then, DMA transfer between the hard disk 13 and the memory 7 is performed by transfer in units of 8 bytes. As described above, when the DMA controllers 1 and 2 performing the real-time processing do not access the bus 5, the DMA transfer is performed collectively with a data length eight times as long as that when the bus 5 is accessed. I can do it. The time required for the transfer is 19 clocks (23 clocks).
75 ns). It takes 5 × 8 = 40 clocks (5000 ns) to perform the same transfer (8-byte data transfer) by performing the DMA transfer in 1-byte units, so that the transfer time is reduced by half and the transfer efficiency is reduced. Is very good.

As described in detail above, according to the DMA controller 10 according to the embodiment, the bus monitor 8 detects the access status of the DMA controllers 1 and 2 that need real-time processing to the bus 5. Is done. Then, the transfer method of the DMA transfer between each of the DMA control units 1 to 3 and the memory 7 is changed based on the detection result. As a result, the DMA transfer is executed very efficiently without affecting the real-time processing.

The above embodiment is merely an example and does not limit the present invention. Therefore, of course, the present invention provides various improvements without departing from the gist thereof.
Deformation is possible. Although the DMA control device in the copying machine has been exemplified as the above embodiment, the present invention is not limited to this.
The present invention can be applied to any device that performs A control. If the bus occupancy of the DMA controllers 1 to 3 is not required, the D
DMA is performed based on the presence or absence of the bus use permission signals ack1 and ack2 (or request signals req1 and req2) of the MA control units 1 and 2.
It is also possible to change the transfer method of the transfer. Further, in the bus monitor unit 8, the bus use permission signal ack
By detecting information of bus 5 instead of 1, ack2,
The operation status of the DMA control units 1 and 2 that require real-time processing may be detected.

Further, in the above-described embodiment, as an example of the change of the transfer word unit, the change of the large-capacity and small-capacity transfer word units is exemplified. However, the present invention is not limited to this. The unit may be changed or the transfer word unit further subdivided may be changed. As a result, DMA transfer can be performed more efficiently. Note that the specific numerical values exemplified in the above embodiment are:
It goes without saying that this is merely an example.

[0037]

As described above, according to the DMA controller of the present invention, the transfer method of the DMA transfer between each device and the memory is changed based on the use status of the shared bus. As a result, DMA transfer with extremely high transfer efficiency is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DMA control device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for describing operations of a bus arbitration unit and a bus monitoring unit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a bus monitor unit of FIG. 1;

FIG. 4 is a timing chart showing states of various signals.

FIG. 5 is a timing chart for explaining a data transfer method.

FIG. 6 is a block diagram showing a schematic configuration of a conventional DMA control device.

FIG. 7 is an explanatory diagram for explaining bus arbitration control in a conventional bus arbitration unit.

FIG. 8 is an explanatory diagram for explaining priorities of bus arbitration control in a conventional bus arbitration unit.

[Explanation of symbols]

 1, 2, 3 DMA control unit 4 access control unit 5 bus 6 bus arbitration unit 7 memory 8 bus monitor unit 10 DMA control unit req request signal ack bus use permission signal SSS occupancy ratio set signal CCS counter clear signal CS clock signal C count Value S Occupancy rate CHT Transfer method change signal

Claims (3)

[Claims] 1. A memory, a shared bus connected to the memory, a plurality of devices connected to the shared bus and accessing the memory, and a bus monitor for detecting a use state of the shared bus by the device Means, at least one based on a detection result of the bus monitor means.
And a transfer method changing means for changing a transfer method of the DMA transfer between the device and the memory. 2. The DMA controller according to claim 1, wherein the plurality of devices include a device that requires real-time processing and a device that does not require real-time processing. DMA detecting operation status of a device to perform
Control device. 3. The DM according to claim 1 or 2,
In the A control device, the transfer method changing means changes a transfer word unit of DMA transfer between at least one of the device and the memory.