JP2538901B2 - Bus coupling device - Google Patents

Description

DETAILED DESCRIPTION [Overview] Two buses (buses having a bus occupancy priority control function. Different types of buses may be used) are coupled, and data is connected between modules connected to the respective buses. In the bus coupler which enables the transmission and reception of the bus, the priority of the occupancy request to the other bus is raised or lowered according to the bus usage status of one bus, so that Data transfer is performed within the range so that the bus occupation time is short and the throughput does not decrease. In addition, it is possible to efficiently perform data transfer with little time delay.

[Industrial applications]

The present invention relates to a bus coupling device that couples buses to each other.

To transfer data between different systems,
When the constituent buses are connected to each other via a coupling device (hereinafter referred to as a bus coupler), more efficient operation is required.

[Conventional technology]

FIG. 3 shows a block diagram for explaining a conventional example. FIG. 3 (A) shows an example of a bus coupler, and FIG. 3 (B) shows another example.

In both FIGS. 3A and 3B, buses (a) and (b) of different systems are connected via a bus coupler 1, and the buses (a) and (b) are connected to the buses. The bus occupancy control units 2a and 2b are provided to control the use of the bus. Data transfer between one central processing unit (hereinafter referred to as CPU) 3 of the module on the bus (a) and one mass storage device (hereinafter referred to as MS) 4 of the module on the bus (b) This is illustrated by way of example when performing.
Although not shown, other modules exist on the buses (a) and (b), and data transfer and communication are performed between them.

The bus coupler 1 (1) shown in FIG.
When data is transferred to MS4, it is transferred via driver 11, and when data is transferred from MS4 to CPU3, it is transferred via driver 12. For example, when sending and receiving data by accessing from the CPU3, the CPU3 first uses the bus (a)
When the bus occupancy controller 2a is requested to accept the bus occupancy, the bus occupancy controller 2b is requested to occupy the bus (b). If this request is also approved, it sends out the address of MS4 and continues to transfer data. In this method, a signal line of a bus is directly coupled via a bus coupler 1 (1) to directly transmit and receive data (this is (1)
It is called a method).

On the other hand, a method in which a buffer is provided in the bus coupler 1 and addresses and data are temporarily stored and transmitted / received is the method shown in FIG. 3 (B) (which is referred to as (2) method). That is, for example, the buffer 13 is used when data is transferred from the MS4 to the CPU3, and the buffer 14 is used when data is transferred from the CPU3 to the MS4, so that the bus (a), ( The occupation request of b) and the transfer of address and data are relayed by the bus coupler 1. In this case, the bus coupler 1 is also one of the modules when viewed from the other modules on each bus.

The arrow lines shown in FIG. 3 (B) are for the purpose of explanation ,,, occupancy request / acceptance, other bus access (memory address set), and address and data transfer, respectively. .

[Problems to be solved by the invention]

In the case of the method (1) shown in FIG. 3 (A), it is necessary to occupy both buses (a) and (b) at the same time during data transfer, and the occupation time is long in order to synchronize the bus occupation. And the throughput decreases.

In the case of the method (2) shown in FIG. 3B, it is not necessary to solve this problem and occupy both buses (a) and (b) at the same time, but when the bus on the data reception side is delayed (others). The buffers 13 and 14 need to have large capacities in order to be waited because there are a lot of other high-priority modules, etc.), which increases the cost.
It also increases the propagation time for large buffers. Further, if the data accumulated in the buffer is continuously transmitted, the access of the module having a lower priority on the receiving side bus will be suppressed for a long time.

It is an object of the present invention to provide a bus coupler with high data transfer throughput, short propagation time, and fair access to other modules on the bus.

[Means for solving problems]

 FIG. 1 is a block diagram showing the principle of the present invention.

The bus coupling device is for coupling buses having at least two levels of bus occupancy priority control functions, and counting means 15 for counting arrival data per unit time from one bus, and preset. Threshold value holding means 16 for holding a threshold value, comparing means 17 for comparing the count value of the counting means and the value of the threshold value holding means, when the comparing means indicates that the count value exceeds the threshold value,
Bus occupancy request signal generating means 22 for changing the bus occupancy request to the other bus (data arrival side bus) from high priority to low priority is provided for each data transfer direction.

Hereinafter, the counting means (counter) 15, the threshold value holding means (threshold value register) 16, the comparing means for each direction of the data transfer.
17, the bus occupancy request signal generating means 22, the data buffer and others are called unit bus couplers 10a and 10b.

[Action]

In the unit bus couplers 10a and 10b, the counting means 15 counts the number of arrival data per unit time.

The comparing means 17 compares the count value of the counting means with the value of the threshold value holding means. Then, when the count value exceeds the threshold value, the bus occupation request signal generation means 22 is notified.

When the bus occupancy request signal generation means 22 receives the signal from the comparison means 17, it changes the priority of the bus occupancy request signal, which has been high up to that time, to the bus on the data arrival side to low. In this way, the priority of the bus occupation request to the bus on the data arrival side is changed from high to low according to the transfer status from the bus on the data transmission side.

Therefore, at this time, if another module on the bus on the data arrival side issues a bus occupation request, that module can easily use the bus. That is, each module does not have to wait too long. At this time, the data buffer 20 is used to hold the data while the apparatus waits.

If it is within the range of the set bus occupancy rate of the unit bus couplers 10a and 10b (determined by the value of the threshold value holding means 16), the bus occupancy request signal is output in a higher priority order, so that the data transfer is accelerated. Data can be sent out as soon as possible). Therefore, it is possible to reduce the delay in data transfer.

Since the bus occupancy can be changed by changing the value of the threshold value holding means 16, it can also be dynamically changed according to the situation of the entire system.

〔Example〕

 The present invention will be specifically described below with reference to examples.

FIG. 2 is a block diagram illustrating an embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

This embodiment will be described by taking as an example the case where data transmission / reception between the CPU 3 and the MS 4 described in FIG. 3 is performed via a bus coupler composed of unit bus couplers 10a and 10b.

The unit bus coupler 10a is used to transfer data from the CPU 3 (the bus (a) to which it belongs) to the MS 4 (the bus (b) to which it belongs), and the unit bus coupler 10b is used to transfer the data to the opposite. Are basically the same, and if both buses have the same standard, they may have the same configuration.
The unit bus coupler 10a will be described below. Since 10b is the same, it is omitted.

The unit bus coupler 10a includes a counting unit (counter) 15, a threshold value holding unit (threshold value register) 16, a comparing unit (comparing circuit) 17, and the arrival data from the bus (a) as a command or a status. Separately, a decoder 18 for converting into a predetermined signal, a bus buffer 19 for receiving unit data from the bus (a) and temporarily holding it, and a data buffer for storing the data from the bus buffer 19 in a FIFO system (FIFO data buffer: The number of stages is about 6) 20, a clock generator 21 for generating a clock signal synchronized with the bus (b) for operating most circuits of the unit bus coupler 10a in synchronization, and the value of the counter 15 is a threshold value. Over (OV
ER) signal generating comparison circuit 17 and FIFO data buffer
20) A bus occupation request signal generation unit 22 that outputs a bus occupation request signal to the bus (b) according to another state is provided.

Next, the operation of this embodiment will be described by taking as an example the case of transferring data from the bus (a) to the bus (b). Although not shown, each of the buses (a) and (b) has other modules (CPU, MS, input / output device, communication control device, etc.) for performing data transfer and communication between them. ing.
Further, there are a plurality of priority levels of the bus occupancy request signal, and each module determines the priority as necessary and outputs the bus occupancy request signal.

The data from the bus (a) is received by the bus buffer 19 in the unit bus coupler 10a, and is sequentially stored in the FIFO data buffer 20 having a six-stage structure. At this time, the counter 15 counts the number of received data (which is detected by the decoder 18 as being data). The counter 15 is reset at regular time intervals so that the count value indicates the number of data per unit time.

This count value is preset in the threshold value register 16 from a resource management module (not shown, which is one of the modules on the bus. The CPU may also serve as the resource.) Which allocates the transfer capability of the bus (b). When the count value is compared with the threshold value and exceeds the threshold value, the comparison circuit 17 sends an over signal to the bus occupation request signal generation unit 22.

As a result, the bus occupation request signal generating unit 22
The bus occupancy control unit 2b is requested by changing the priority of the occupancy request signal of the bus (b) to the lower level.

For example, when the threshold value preset in the threshold value register 16 is "3", and when three pieces of data from the bus (a) arrive within the unit time, the over (OVER) signal is not sent,
Can occupy the bus with a high priority. Therefore, it is possible to perform transfer with less delay. In this case, it falls within the assigned transfer rate on the bus (b) side. In addition, bus (a)
The bus occupancy in is determined by the source of the data, so the bus coupler is not directly involved.

On the other hand, when four pieces of data from the bus (a) arrive within the unit time, if they are transferred as they are, the allocated transfer capacity on the side of the bus (b) will be used, and the over (OV
The ER) signal changes the occupancy request of the bus (b) to a low priority and processes it. As a result, when the bus (b) is occupied by another module and the FIFO data buffer 20 becomes full, the transfer on the bus (a) side is suppressed by the BUSY response. When such a situation occurs, or after a certain period of time after the priority becomes the lowest, the priority may be set again to the highest.

The threshold value may be set at the time of setting the initial value, but the resource management modules (not shown) of the bus (a) and the bus (b) communicate with each other to set the direction of each data. The transfer capability can be adjusted for each. It can be dynamically changed in this way, and the capacity of the bus system can be fully utilized.

〔The invention's effect〕

According to the present invention as described above, efficient use is made of the capability of the bus system so that the throughput of data transfer is high, the propagation time is short, and access to other modules on the bus is fair. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a block diagram illustrating a conventional example. In the figure, 1,1 (1) and 1 (2) are bus couplers (bus couplers), 10
a and 10b are unit bus couplers, 2a and 2b are bus occupation control units, 3 is a central processing unit (CPU), 4 is a storage device (MS), 11,12 are drivers, 13,14 are buffers, 15 are counters, 16 Is a threshold register, 17 is a comparison circuit, 18 is a decoder, 19 is a bus buffer (temporary buffer), 20 is a data buffer (FIFO data buffer), 21 is a clock generator, 22 is a bus occupation request signal generator, .

Claims (1)

(57) [Claims] 1. A bus combiner for connecting buses having at least two levels of bus occupancy priority control functions, and counting means for counting the number of arrival data per unit time from one bus, and preset. The threshold value holding means for holding the threshold value, the comparing means for comparing the count value of the counting means with the value of the threshold value holding means, and the other bus when the comparing means indicates that the count value exceeds the threshold value. Bus occupancy request signal generating means for changing a bus occupancy request to a lower priority from a higher priority.