KR100464989B1 - Control bus system and bus arbitration method - Google Patents

Abstract

The present invention relates to a control bus system and a bus arbitration method. In particular, by incorporating address signals and data signals by modifying the asynchronous transmission scheme of the conventional control buses, the VME and PCI buses, the number of edge pins of the backplane is minimized. Improved signal interference due to signal patterns. In addition, by implementing a modular control bus that can arbitrate the bus in a round-robin manner by a counter and enable stable operation and easy application, the system design can be easily implemented, stability, speed and cost can be reduced.

Description

Control bus system and bus arbitration method

The present invention relates to a control bus structure and a bus arbitration method that integrates an address signal and a data signal to reduce the number of signal patterns on a back plane.

Typically, the physical connection that exists between the interface processor or card and the data bus or the bus for power supply in the main body is called the backplane. At this time, there are various kinds of buses, and VME (Versa Module Eurocard) is a computer card system called Versa Module that is adapted to the Eurocard standard and is widely used in the field of industrial communication control. It is a standard computer control bus system. Peripheral Component Interconnect (PCI) is also an interconnect control bus system between devices attached to expansion slots located close to the microprocessor for high speed operation. The VME, PCI bus described above is an asynchronous transmission scheme.

However, the current transmission system using the VME or PCI bus as described above is being integrated day by day, the complexity of the analog signal and high frequency signal is mixed, resulting in a lack of quantity and margin of edge connector pins on the backplane Interference between signals due to the phenomenon and the excessive number of signal patterns is occurring.

The present invention is to solve the above problems, an object of the present invention is to modify the asynchronous transmission scheme of the existing VME, PCI bus by integrating the address signal and the data signal, reducing the number of signal patterns on the backplane, each node The present invention provides a control bus system that implements a stable data transmission method.

Another object of the present invention is to provide a bus arbitration method for arbitrating bus access in a round-robin manner by a counter in a control bus system in which an address signal and a data signal are integrated.

1 is a block diagram illustrating an overall configuration of a bus control system according to the present invention.

2 is a timing diagram of data write operation at a node that acquires a bus of the present invention.

3 is a timing diagram of data read operation at a node that acquires a bus of the present invention.

4 is a flowchart illustrating a data transmission operation in a node obtaining a bus license of the present invention.

5 is a flowchart illustrating data reception at a node selected by an address signal of a bus of the present invention.

6 is a view showing an example of the use of parallel transmission and reception of serial communication data, such as HDLC and IP with the CPU via the control bus of the present invention

Explanation of symbols for main parts of the drawings

100: master 101 ~ 131: node

The control bus system according to the present invention for achieving the above object, the bus arbitration control and the master for checking the abnormality of each node, and the number of N on the backplane to obtain bus license and transmit and receive data under the control of the master The master and each node are provided with a first counter for bus arbitration and a second counter for data transmission and reception after bus acquisition, and an integrated address of a mux structure, between the master and each node through a data bus. And transmitting and receiving addresses and data.

The master supplies a bus synchronization clock NCLK signal and an NCLR signal for clearing a first counter for bus arbitration to each node, and the first counter of each node acquires a bus by counting an NCLK signal after being cleared by the NCLR signal. The second counter may start counting to control data transmission and reception when the NAS is low.

The number of edge pins of the backplane may include a NAS signal indicating that a bus acquirer occupies the bus to read or write data, an NDTACK signal indicating that an operation is terminated at a selected node, a bus synchronization clock NCLK signal provided by a bus master, NMST signal controlled by the node to use the bus, NCLR signal clearing the first counter for bus arbitration, parity NPARITY signal for N (00:15), 16-bit address, data bus N (00:15) It is characterized by consisting of 22 signal lines.

The first counter in each node loads the slot ID of the backplane as an initial value and counts up in synchronization with the NCLK signal. When the count value reaches 'FF', the first counter is acquired.

The node acquiring the bus right activates the NMST signal low when there is data to be transmitted to stop the operation of the first counter in all nodes on the bus and informs the use of the bus, and the second counter informs the NCLK signal. And starts counting in synchronization.

When the master transfers data from the bus-licensed master to each node, the NAS is activated low so that each node on the bus operates its own second counter in synchronization with the NCLK received from the master. Is '00', the node whose match occurs by comparing the upper N15 to N11 bits with its slot ID is selected by the master, and the selected node is provided by the master when the second counter value becomes '00'. The value of N15 to N00 is latched to the upper address register. When the value is '01', the master muxes and changes the lower address to N15 to N00, and the selected node latches the value of N15 to N00 to the lower address register. The master transmits data to N15 to N00 when it is '02', and the selected node decodes the value of N15 to N00. Characterized in that for latching to the emitter resistor.

In the bus arbitration method according to the present invention, the master supplies a bus synchronization clock NCLK signal and an NCLR signal for clearing the bus counter first counter to each node, and the first counter of each node is cleared by the NCLR signal. After that, the slot ID of the backplane is loaded to an initial value and counted up in synchronization with the NCLK signal. When the count value reaches 'FF', the bus is licensed, and the address is addressed through the integrated bus by the count value of the second counter. And sequentially transmitting data to the master, and when transmitting data from the bus-licensed master to each node, each node on the bus to operate its second counter in synchronization with the NCLK received from the master. A node is matched by comparing its slot ID with the upper N15 to N11 bits and addressed through the integrated bus at the master. And sequentially transmitting data.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

1 is a block diagram illustrating the overall configuration of a control bus system according to the present invention. The bus arbitration control and the master 100 checking the abnormality of each node and the bus 100 are acquired and controlled by the control of the master 100. N slaves on the backplane, that is, nodes 101 to 131. The master 100 and each of the nodes 101 to 131 are provided with a counter a for bus arbitration and a counter b for data transmission and reception after bus acquisition. Here, the master 100 may be a CPU or an engine.

That is, the master 100 supplies NCLK and NCLR to each of the nodes 101 to 131 to control bus arbitration, and each node 101 to 131 receives the NCLK and NCLR from the master 100 to provide bus arbitration. The logic acquires a license and transmits and receives data. At this time, 'counter a' counts NCLK to acquire the bus, and 'counter b' operates when the NAS is low.

Hereinafter, the control bus of the present invention is referred to as N-bus for convenience of description. That is, the signals of the N-bus are defined as a total of 22 signal lines including the mux structure addresses and data buses of N00 to N15 in addition to the control signals NAS, NCLK, NDTACK, NPARITY, NMST, and NCLR.

Table 1 below summarizes the functions of the signals of the N-bus system of FIG.

Name function Other NAS Indicates that the bus acquirer has occupied the bus to read or write data. Activate 'counter b' when active. Active low NDTACK Indicates that the operation ended with the bus acquirer on the selected node side of the bus. Active-low (1 NCLK) NCLK Bus synchronous clock provided by the bus master. 1/2 CPU Clock NMST Control at the node you want to use the bus. Active low NCLR Initialize 'counter a' for bus arbitration. Active-low (1 NCLK) NPARITY Parity for N (00:15). Even parity N (00:15) 16-bit address, data bus

Table 2 below shows the definition of the N (00:15) data format when the value of 'counter b' is 00.

Signal name N15 N14 N13 N12 N11 N10 N09 N08 N07 N06 N05 N04 N03 N02 N01 N00 Internal signal name A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 X X 0/1 0/1 function Slot selection Reserved Size R / W

Size signal: 0: 8 bit transmission, 1: 16 bit transmission

R / W Signal: 0: Light, 1: Lead

Table 3 below shows the definition of the N (00:15) data format when the value of 'counter b' is 01.

Signal name N15 N14 N13 N12 N11 N10 N09 N08 N07 N06 N05 N04 N03 N02 N01 N00 Internal signal name A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 function CPU address Table 4 below shows the definition of the N (00:15) data format when the value of 'counter b' is 02 (that is, writing only).

Signal name N15 N14 N13 N12 N11 N10 N09 N08 N07 N06 N05 N04 N03 N02 N01 N00 16 bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 8 bit X X X X X X X X D31 D30 D29 D28 D27 D26 D25 D24 function CPU data FIG. 2 is a timing diagram of the write operation at the node acquiring the bus, and FIG. 3 is a timing diagram of the read operation at the node acquiring the bus. When the R / W signal is low, the write operation occurs. It can be seen. In addition, 'counter b' counts up in synchronization with NCLK when the NAS is 0. At this time, the operation shown in Table 2 to Table 4 occurs according to the 'counter b' value.

Next, a bus arbitration in a round-robin manner by a counter in the N-bus system of the present invention in which an address signal and a data signal are integrated as described above will be described.

4 is a flowchart illustrating a data transmission process in a node obtaining a bus of the present invention, and shows an example of a bus acquisition and data transmission process of each node.

In the bus arbitration method of the present invention, the master 100 and each of the nodes 101 to 131 have a 'counter a' synchronized with the NCLK. The bus arbitration method loads the slot ID of the backplane to an initial value and counter-ups the counter value. A node reaching 'will be able to obtain a license for the bus.

That is, 'counter a' of the node where NMST is 1 (NMST = 1) and NCLR is 0 loads the corresponding slot ID with an initial value (step 401). In the case of 'counter a', when NMST is 1 (NMST = 1) and NCLR is 1, the process of increasing the count value by 1 in synchronization with NCLK is repeated until the count value becomes FF (step 402). If the above step is repeated and the value of 'counter a' becomes FF, the node acquires a bus right and checks whether there is data to be transmitted, that is, Tx_data_flag is 1 (step 403).

If there is data to be transmitted in step 403, the NMST signal is activated low to stop the operation of 'counter a' in all nodes on the bus and inform the use of the bus. In addition, the NAS signal is activated low so that 'counter b' counts in synchronization with NCLK (step 404).

If the count value of 'counter b' becomes '00', the node transfers the value in the upper address register (RH) to N00 to N15 to the bus of the present invention. When the count value of 'counter b' becomes '01', the value in the lower address register RL is loaded into N00 to N15 and transferred to the bus of the present invention. When the count value of 'counter b' becomes '02' again, the value in the data register RD is loaded into N00 to N15 and transferred to the bus of the present invention (step 405).

Then, it is checked whether the NDTACK signal is low (step 406). The NDTACK signal is an active low signal indicating that the operation is terminated by the bus acquirer at the selected node side of the bus. Accordingly, when the NDTACK signal is low in step 406, that is, when the use of the bus is normally terminated, the NMST signal is inactive (non-active or negate) to operate the 'counter a' in all nodes on the bus. Since 'counter a' has been counter terminated to FF, it is in a waiting state until NCLR, which is a counter clear signal, is activated from the master 100 (step 407). At this time, the NAS signal is inactive to clear 'counter b'. This ends with a normal bus operation (step 408).

However, if the NDTACK signal is high in step 406, it is checked whether the 'counter b' value is 32 (step 409). If the NDTACK signal does not go low until the value of 'counter b' becomes 32, the NMST signal and the NAS signal are inactivated high (step 410), and the node which has obtained the license of the bus detects the bus operation as an error. The data is retransmitted or treated as an exception (step 411).

Meanwhile, 'counter a' existing in the master 100 starts counting at '00', which is an initial value, and when the value reaches '64', activates the NCLR signal at the next clock to 'counter a' of all nodes in the bus. It clears and resumes operation at the initial slot ID value. In the case of 'counter a' in the master 100, a value that is counted may be adjusted according to the number of nodes that may occupy a bus, and '64' in the above description assumes a maximum of 32 nodes.

In addition, the operation mode of 'counter a' is divided into two modes: a single mode in which one data is transmitted when occupying one bus and a multi mode in which a large amount of data can be transmitted by occupying one bus. The mode can be selected and used.

FIG. 5 is a flowchart illustrating a data reception process at a node selected by an address signal provided by a node that has obtained a right to use a bus of the present invention. The NAS signal and the NDTACK signal of each node 100 to 131 are high. In the inactive state, 'counter b' is initialized to the clear state (step 501).

At this time, if the CPU or the engine, which is the node that has obtained the bus right by the bus arbitration logic, transmits data to each of the nodes 100 to 131, the address strobe (NAS) is activated low (step 502). Nodes 100 to 131 operate their respective 'counter b' synchronized with the NCLK received from the master 100, and this 'counter b' is the same as the 'counter b' of the node that obtained the bus license. (Step 503).

When the NAS is low and the 'counter b' value is '00', when a match occurs by comparing the upper N15 to N11 bits and its slot ID, the matched node is recognized as the selected node and N15 to N00. Is latched into the upper address register RH. Subsequently, when the node having obtained the license of the bus and the 'counter b' value of the corresponding node become '01', the node having obtained the license of the bus muxes the lower address from N15 to N00, and at this time, the selected node changes the N15 to N15. The value of ˜N00 is latched in the lower address register RL to be transmitted to the respective decoder logic.

When the node that has obtained the license of the next bus and the value of 'counter b' of the selected node becomes '02', the node that has obtained the license of the bus muxes the data from N15 to N00, and the selected node changes the N15 to N00. Is latched in the data register RD (step 504).

Then, when the value 'counter b' becomes '03' (step 505), a data parity check is performed (step 506). At this time, it checks whether there is an abnormality in data transmission by comparing with the received NPARITY value, and when there is no error, processes data at each device access time and transmits a NDTACK, which is a transmission completion signal, to a node that has obtained a license for the bus.

That is, if the value of the received NPARITY and the parity check result match, it is determined that data transmission is normally performed (step 507). In this case, the NDTACK signal is activated low and transmitted to the node that has obtained the license of the bus. Clear (step 508). In other words, if the node having obtained the right to use the bus normally receives the NDTACK, that is, if the NDTACK signal is low, the NAS is inactive to clear 'counter b' of all nodes on the master and the backplane and terminate the transmission.

On the other hand, if it is determined in step 507 that there is an error in the parity check, the selected node does not transmit the NDTACK, and if the value of 'counter b' becomes 32, the node that obtained the license of the bus detects the bus operation as an error and retransmits it. Or, handle it as an exception. For example, the NAS is inactive to clear 'counter b' of all nodes on the master and backplane and terminate the transfer (step 509).

As such, the N-bus of the present invention can be effectively used in a system composed of one control board and a plurality of I / O boards, such as most transmission equipment or IP routers. In this case, 'counter a' is not used and is always configured to occupy the bus on the control board, allowing direct access to DPRAM or devices on the I / O board, which is effective for the application.

In particular, in systems with multiple control boards, the bus arbitration time can be adjusted by adjusting the count period of 'counter a' according to the number of control boards, which enables efficient bus arbitration. It is possible to improve the performance of the system, which enables simple and efficient system configuration.

FIG. 6 is a diagram illustrating a usage example of transmitting and receiving serial communication data such as HDLC (High-level Data Link Control) or IP to the CPU in parallel through the N-bus of the present invention. The control bus of the CPU can be configured, and in addition, it can be applied to the transmission of packet data.

In FIG. 6, the HDLC / IP packet handler refers to a queue capable of storing data packets and a module capable of serial transmission and reception, and glue logic refers to serial or parallel. Means a module that can convert to serial.

Table 5 below compares the existing bus (eg, VME, PCI bus) with the N-bus of the present invention.

Item Existing Method (VME, PCI Bus) N-bus Number of data signals 8 to 32, 64-bit 8 to 16 bits Address signal number 32 bit 27 bit Control signal Four 6 Edge Pins Required 45 to 69 22 Error check none 1 bit parity Bus earner One or multiple nodes available All nodes available Bus performance 16-bit standard: 20 to 60 Mbyte / sec 16 bits * 50 MHz (5 clocks required) = 24 Mbyte / sec

As described above, according to the control bus system and the bus arbitration method according to the present invention, by modifying the asynchronous transmission scheme of the conventional control buses VME and PCI bus to integrate the address signal and the data signal, the number of edge pins of the backplane is minimized In addition, the interference of the signal due to the excessive signal pattern is improved.

In addition, by implementing a modular control bus that can arbitrate the bus in a round-robin manner by a counter and enable stable operation and easy application, the system design can be easily implemented, stability, speed and cost can be reduced.

In addition, it can be applied to most systems having a plurality of slaves and masters, and can be easily used for IP routers as well as various transmission devices such as xDSL and VOIP by easily interfacing with a Motorola CPU which is widely used in transmission equipment.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (16)

A master for checking bus arbitration control and abnormality of each node; And It is composed of N nodes on the backplane to obtain a bus license and transmit and receive data under the control of the master, The master and each node are provided with a first counter for bus arbitration and a second counter for data transmission and reception after bus acquisition. Control bus system, characterized in that. The method of claim 1, The master, A bus synchronous clock NCLK signal and an NCLR signal for clearing the first counter for bus arbitration are supplied to each node, and the first counter of each node is counted by the NCLK signal to obtain a bus after being cleared by the NCLR signal. The counter is a control bus system, characterized in that when the NAS is low, it starts counting to control data transmission and reception. The method of claim 1, The number of edge pins of the backplane is A NAS signal indicating that the bus acquirer has taken over the bus to read or write data, an NDTACK signal indicating that the operation has ended on the selected node, a bus synchronous clock NCLK signal provided by the bus master, or a node to use the bus. NMST signal for controlling, NCLR signal for clearing the first counter for bus arbitration, parity NPARITY signal for N (00:15), 16-bit address, data bus N (00:15), and a total of 22 signal lines Characterized by a control bus system. The method of claim 1, The first counter in each node, And loading the slot ID of the backplane to an initial value and counting up in synchronization with the NCLK signal, and acquiring a license for the bus when the count value reaches 'FF'. The method of claim 4, wherein The node obtaining the bus license is If there is data to be transmitted, the NMST signal is activated low to stop the operation of the first counter in all nodes on the bus and to inform the use of the bus, and the second counter starts counting in synchronization with the NCLK signal. Control bus system. The method of claim 5, wherein When the second counter value is '00', the node acquiring the bus transfers the value in the upper address register RH to the master by N00 to N15, and when the second counter value is '01', the node in the lower address register RL The control bus system characterized in that the value is transferred to the master by loading a value in N00 ~ N15, and the value in the data register (RD) is transmitted to the master when '02'. The method of claim 4, wherein The node obtaining the bus license is When the use of the bus is terminated normally, the operation of the first counter in all nodes on the bus resumes, and its first counter value remains in the FF state until the NCLR signal is active at the master. . The method of claim 4, wherein The first counter of the master, If there are 32 nodes, start counting at the initial value '00', and when it reaches '64', activate the NCLR signal at the next clock to clear the first counter of all nodes in the bus and operate at the initial slot ID value. Control bus system, characterized in that the resumption. The method of claim 1, When data is transferred from the master, which is bus-licensed by the bus arbitration logic, to each of the nodes, the NAS is activated low so that each node on the bus operates its own second counter in synchronization with the NCLK received from the master. And a node whose match occurs by comparing the upper N15 to N11 bits with its slot ID when the second counter value is '00'. The method of claim 9, The selected node, When the second counter value is '00', the master latches the value of N15 to N00 provided by the master to the upper address register RH. When the second counter value is '01', the master muxes and changes the lower address to N15 to N00. The node latches the values of N15 to N00 in the lower address register RL and transmits them to the decoder logic. When '02', the master muxes and changes the data to N15 to N00. A control bus system characterized by latching values of N15 to N00 in a data register (RD). The method of claim 10, The selected node, When the second counter value is '03', data parity check is performed to check whether there is an error in data transmission. If there is no error, processing the data at each device access time and transmitting the transmission completion signal NDTACK to the master is performed. Control bus system characterized by. It is composed of a master to check the bus arbitration control and abnormality of each node, and N nodes on the backplane to obtain a bus license and transmit and receive data under the control of the master, the master and each node has a first for bus arbitration In the bus arbitration method of the control bus system is provided with a counter and a second counter for transmitting and receiving data after bus acquisition, and the address and data between the master and each node through the integrated address, data bus of the mux structure, (a) the master supplying a bus synchronization clock NCLK signal and an NCLR signal for clearing a first counter for bus arbitration to each node; (b) After the first counter of each node is cleared by the NCLR signal, it loads the slot ID of the backplane to the initial value and counts up in synchronization with the NCLK signal. Acquiring and sequentially transmitting an address and data to the master through an integrated bus by a count value of a second counter; And (c) When data is transferred from the master who has obtained the bus license to each node, each node on the bus operates its own second counter synchronized with NCLK received from the master, and the second counter value is '00'. And sequentially transmitting the address and data from the master through the integrated bus to the node where a match occurs by comparing the upper N15 to N11 bits with its slot ID. The method of claim 12, The node obtaining the bus license in step (b) When the second counter value is '00', the node acquiring the bus transfers the value in the upper address register RH to the master by N00 to N15, and when the second counter value is '01', the node in the lower address register RL A bus arbitration method comprising transferring a value from N00 to N15 to the master, and when the value is '02', transfers a value from the data register (RD) to the master from N00 to N15. The method of claim 12, In step (b), the node obtaining the bus license is The bus arbitration method resumes operation of the first counter in all nodes on the bus when the bus is normally terminated, and its first counter value is maintained in the FF state until the NCLR signal is activated at the master. . The method of claim 12, The node selected by the master in step (c) is When the second counter value is '00', the master latches the value of N15 to N00 provided by the master to the upper address register RH. When the second counter value is '01', the master muxes and changes the lower address to N15 to N00. The node latches the values of N15 to N00 in the lower address register RL and transmits them to the decoder logic. When '02', the master muxes and changes the data to N15 to N00. A bus arbitration method comprising latching values of N15 to N00 in a data register (RD). The method of claim 12, The node selected by the master in step (c), When the second counter value is '03', data parity check is performed to check whether there is an abnormality in data transmission. If there is no abnormality, the data is processed at each device access time and a transmission completion signal is transmitted to the master. Bus arbitration method.