CN116094867B

CN116094867B - Time-sensitive network control protocol design method based on MLVDS bus

Info

Publication number: CN116094867B
Application number: CN202310374662.4A
Authority: CN
Inventors: 陈建中; 胡宇波; 陶伟; 汤刚刚; 汤玮珉; 杨宏博; 朱湘兰; 吕亚静; 张玉奇
Original assignee: Hunan Jingling Zhilian Information Technology Co ltd
Current assignee: Hunan Jingling Zhilian Information Technology Co ltd
Priority date: 2023-04-10
Filing date: 2023-04-10
Publication date: 2023-06-16
Anticipated expiration: 2043-04-10
Also published as: CN116094867A

Abstract

The application relates to a time-sensitive network control protocol design method based on an MLVDS bus. The method comprises the following steps: defining a frame structure of a data frame transmitted by an MLVDS bus; setting an inter-frame space between continuous data frames, when a bus is in a bus idle state in the inter-frame space, adopting a carrier sense multiple access method to realize nondestructive bitwise arbitration of a plurality of bus sending nodes in an arbitration field, and after arbitration success, if the same bus sending node obtaining a bus floor needs to send a plurality of periodic data, carrying out transmission scheduling on the plurality of periodic data with different priorities; and if a plurality of bus sending nodes obtaining the bus floor at the current moment all need to send the aperiodic data, adopting a dynamic priority algorithm to carry out transmission scheduling on each aperiodic data. The method can realize distributed, completely centerless multi-point-to-multi-point high-speed Mesh network transmission.

Description

Time-sensitive network control protocol design method based on MLVDS bus

Technical Field

The application relates to the technical field of communication, in particular to a time-sensitive network control protocol design method based on an MLVDS bus.

Background

The speed of the traditional serial buses such as RS485, CAN and 1553B buses is too low to support high-speed, self-adaptive and deterministic transmission of services, the Ethernet interface needs a centralized switch, single-point failure risks exist in high-reliability occasions, and because the traditional method cannot support the requirements of some miniaturized novel electronic information processing platforms on multi-node large-bandwidth high-speed time sensitivity and deterministic transmission of services, a MLVDS bus-based high-speed time sensitivity and deterministic network of services is provided.

The LVDS interface is also called RS-644 bus interface, and is a data transmission and interface technology which is only developed in the 90 th year of the 20 th century. LVDS is a low-voltage differential signal, and the core of the technology is that extremely low voltage swing high-speed differential transmission data is adopted, so that point-to-point or point-to-multipoint connection can be realized, and the technology has the characteristics of low power consumption, low bit error rate, low crosstalk, low radiation and the like. Whereas conventional LVDS applications are a high-speed point-to-point application communication standard, in recent years multi-drop LVDS (MLVDS) is a point-to-multi application oriented standard, MLVDS specifies a higher differential output voltage relative to LVDS in order to allow for higher loads from a multi-drop bus, typical applications of MLVDS are typically widely used for high-speed backplane, cable and board-to-board data transmission and clock distribution, as well as low-power high-speed communication links within a single PCB, i.e. star-structured.

The time sensitive network (time-sensitive networking, TSN) is used as a product of the integration of the control (operation technology, OT) network and the information (information technology, IT) network, so that the real-time performance and the certainty of industrial control can be met, the Ethernet can be compatible, and the mixed transmission of industrial control data and Ethernet data can be realized. The high-speed time-sensitive and business deterministic network based on the MLVDS bus is developed for adapting to the standardized high-speed transmission system of the novel electronic information processing platform, and each device of the high-speed time-sensitive and business deterministic network based on the MLVDS bus performs point-to-point or point-to-multiple data interaction based on the data bus interface, so that the distributed control and the state monitoring of the novel electronic information processing platform are realized. However, conventional MLVDS buses still present a single point failure risk when performing point-to-point or point-to-multiple data interactions.

Disclosure of Invention

Based on this, it is necessary to provide a time-sensitive network control protocol design method based on an MLVDS bus in order to solve the above technical problems.

A time sensitive network control protocol design method based on an MLVDS bus, the method comprising:

defining a frame structure of a data frame transmitted by an MLVDS bus; the frame structure includes a frame start, an arbitration field, a control field, a data field, a CRC field, a response field, and a frame end; the arbitration field includes an identifier, a destination address, and a source address; the identifier comprises a device ID number and a priority segment;

setting an inter-frame space between continuous data frames, when a bus is in a bus idle state in the inter-frame space, adopting a carrier sense multiple access method to realize nondestructive bitwise arbitration of a plurality of bus sending nodes in the arbitration field, and after arbitration success, adopting a preset bus time sensitive message transmission scheduling mechanism based on priority to carry out transmission scheduling on a plurality of periodic data with different priorities if the same bus sending node obtaining a bus floor needs to send a plurality of periodic data;

and if the plurality of bus sending nodes obtaining the bus floor at the current moment all need to send the aperiodic data, adopting a preset dynamic priority algorithm to carry out transmission scheduling on each aperiodic data.

In one embodiment, the method further comprises: classifying the plurality of periodic data according to the periods corresponding to the plurality of periodic data to obtain a plurality of transmission queues with different periods; the shorter the period of the specified transmission queue is, the higher the priority of data transmission is, when the transmission of the transmission queue with high priority is completed in the corresponding period, the data transmission of the transmission queue with next priority is entered, and when the transmission of the transmission queues is completed, the transmission of the periodic data is completed.

In one embodiment, the method further comprises: initializing a priority section of a data frame corresponding to each aperiodic data, wherein the initial priority corresponding to the initialized priority section is 0x00, and if the aperiodic data is a control instruction, defining the priority section of the control instruction according to the initial priority and the arbitration failure times; the aperiodic data includes control class instructions; judging the priority of the aperiodic data transmission according to the value of the identifier in the data frame corresponding to each aperiodic data; the bus sending nodes for sending the aperiodic data sequentially send the aperiodic data in one period according to the order of the priorities from large to small; when the non-periodic data failure of the bus sending node exists, the bus sending node with the failed sending actively promotes the priority of the bus sending node so as to ensure that the bus sending node sends the non-periodic data in the next non-periodic sending time window.

In one embodiment, the method further comprises: and after the clock signal continuously generates a preset number of idle periods, judging that the bus is in a bus idle state.

In one embodiment, the method further comprises: the bus transmitting node judges whether the bus is in a bus idle state, and when the bus is in the bus idle state, a certain bus transmitting node transmits a frame start bit on a bus data line; the frame start bit is a dominant bit; after the clock module of the FPGA detects the frame start bit on the bus data line, the clock module starts to send a clock signal; the other bus nodes synchronize to the first rising edge of the clock signal, wherein the other bus transmitting nodes transmit new data frames on the bus data lines, and the other bus nodes which do not transmit new data frames transmit recessive bits on the bus signal lines, so that frame synchronization is realized.

In one embodiment, the method further comprises: the acknowledgement field includes an acknowledgement gap, an acknowledgement delimiter, an overload result, and a reserved bit.

In one embodiment, the method further comprises: the method of intra-frame confirmation is adopted to confirm the received data frame; the method for intra-frame acknowledgement comprises the following steps: the bus sending node sends a data frame to the bus receiving node, and reads back the data on the bus and judges the response field delimiter; and the bus receiving node confirms the correctness of the message in the sending process of the data frame, and makes the position of the response delimiter on the bus dominant so as to inform the bus sending node that the data frame is normally received, otherwise, informs the bus sending node to resend the data frame.

In one embodiment, the method further comprises: the method further includes an error detection mechanism; the error detection mechanism comprises bit monitoring, response detection and CRC check; when the bit monitoring comprises the step of reading back the transmitted level at a transmitter of a bus transmitting node, if the read bit level is different from the transmitted bit level, a signal is sent to indicate bit errors; the response detection comprises that a bus sending node detects whether a dominant level exists in a response time slot, if the dominant level is not detected, an error signal is sent, and the bus sending node retransmits a currently transmitted data frame; the CRC check comprises that when the bus node detects CRC different from the calculated CRC in the sending message, the current data frame is discarded, and a negative acknowledgement result is sent in an acknowledgement field.

In one embodiment, the method further comprises: the bus coding mode of the MLVDS bus is a line or logic non-return-to-zero coding mode.

In one embodiment, the method further comprises: the maximum bus transmission rate of the MLVDS bus is 100Mbps.

According to the time-sensitive network control protocol design method based on the MLVDS bus, by adopting the self-adaptive multi-master-station arbitration mechanism, any node on the bus can send own data to the bus when the bus is idle, and when a plurality of nodes need to send data to the bus at the same time, only the node with the highest current priority can obtain the sending right. According to the embodiment of the invention, distributed, completely centerless multi-point-to-multi-point high-speed Mesh network transmission is realized based on the MLVDS bus, and up to 32 nodes are allowed to be connected to one bus.

Drawings

FIG. 1 is a flow chart of a time sensitive network control protocol design method based on an MLVDS bus in one embodiment;

FIG. 2 is a schematic diagram of a protocol hierarchy in one embodiment;

FIG. 3 is a schematic diagram of NRZ encoded lines or logic in one embodiment;

FIG. 4 is a bit sync pattern diagram in one embodiment;

FIG. 5 is a schematic diagram of a correspondence between Wen Lvbo devices in one embodiment;

FIG. 6 is a schematic diagram of the structure of a data link frame in one embodiment;

FIG. 7 is a diagram of a bus interframe space structure in one embodiment;

FIG. 8 is a diagram of a frame synchronization process in one embodiment;

FIG. 9 is a schematic diagram of a protocol control flow in one embodiment;

FIG. 10 is a logic diagram of a bus state machine FSM when the node state is bus detection in one embodiment;

FIG. 11 is a logic diagram of a bus state machine FSM when node status is not bus detection in one embodiment;

FIG. 12 is a schematic diagram of a priority promotion flow in one embodiment;

FIG. 13 is a schematic diagram of a bus reply process in one embodiment;

FIG. 14 is a schematic workflow diagram of a data link layer in one embodiment;

FIG. 15 is a schematic diagram of a bus send workflow in one embodiment;

FIG. 16 is a schematic diagram of a bus reception workflow in one embodiment;

FIG. 17 is a schematic diagram of a maximum number of delays for node collisions in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In one embodiment, as shown in fig. 1, there is provided a time sensitive network control protocol design method based on an MLVDS bus, including the steps of:

step 102, defining a frame structure of a data frame transmitted by the MLVDS bus.

The time-sensitive network control protocol design method based on the MLVDS bus follows the architecture of OSI reference model, and the simplified layered structure comprises a physical layer, a data link layer and an application layer. In the bus protocol design of the invention, the content related to the physical layer and the data link layer is mainly considered, and standard interface encapsulation call is provided for the application layer. The MLVDS transceiver only performs the functions of the physical layer, while the functions of the data link layer and the network management need to be supported by separate software or hardware. Since the bus is designed for high-speed real-time applications, it should be implemented by a hardware FPGA.

As shown in fig. 6, the frame structure of the data link frame includes a frame start, an arbitration field, a control field, a data field, a CRC field, an acknowledgement field, and an end of frame. Wherein the start of frame bit represents the beginning of a data frame and is composed of an dominant bit. Only when the bus is idle, the frame start bit can be sent; the arbitration field consists of a 16-bit identifier, an 8-bit target address and an 8-bit source address, wherein the identifier comprises a device ID number and a priority section; the control field is 16-bit data length, and the data length is an integer between 0 and 4096; the data field is data to be transmitted, the length of the data field is 0-4096 bytes, and the data field is transmitted from the highest bit of the bytes; the CRC field adopts CRC-CCITT cyclic redundancy code check, and the check code length is 16 bits; the length of the response field is designed to be 8 bits, and comprises a 1-bit response gap, a 1-bit response delimiter, a 1-bit overload result and 5-bit reserved bits; the end of the frame is fixed to a flag sequence consisting of 7-bit full recessive bits.

Step 104, setting an inter-frame space between consecutive data frames, when the bus is in a bus idle state in the inter-frame space, implementing non-destructive bitwise arbitration of a plurality of bus sending nodes by adopting a carrier sense multiple access method in an arbitration field, and after arbitration success, if the same bus sending node obtaining the bus floor needs to send a plurality of periodic data, adopting a preset bus time sensitive message transmission scheduling mechanism based on priority to perform transmission scheduling on the plurality of periodic data with different priorities.

As shown in the schematic diagram of the inter-frame space of the bus in fig. 7, the inter-frame space is used for isolating continuous data frames, and includes two parts of intermittent and bus idle, the intermittent part includes 3 recessive bits, during the intermittent part, all MLVDS nodes cannot transmit data frames, the idle length of the bus can be defined according to the requirement, and any node needing to transmit data can start transmitting only when the bus is judged to be idle.

The collision detection method of the method adopts a non-destructive bitwise arbitration mechanism and is realized by a carrier sense multiple access method (CSMA/BA, carrier Sense Multiple Access/Bitwise Arbitration). The mechanism utilizes the line or logic of the MLVDS to enable the conflict detection and bus arbitration of the bus to be simple and efficient, and meanwhile, the problem of network performance degradation of CSMA/CD under the condition of heavy load is avoided, so that the mechanism is the basis and key for supporting multi-master communication.

And 106, if a plurality of bus sending nodes obtaining the bus floor at the current moment all need to send the aperiodic data, adopting a preset dynamic priority algorithm to carry out transmission scheduling on each aperiodic data.

The real-time performance of the non-periodic data transmission can be greatly improved by formulating a corresponding arbitration competition mechanism, however, when a plurality of nodes transmit the non-periodic data at the same time point, competition can be generated on the bus. If the frame structure is not set, the device with larger identifier can send preferentially, the device with smaller node identifier can only delay sending, if such phenomenon exists all the time, the device with larger node number can not occupy the bus for data transmission all the time. Therefore, the 16-bit Identifier (IDE) in the LLC data frame is divided into two parts, the first part represents an 8-bit device ID number, the second part is an 8-bit priority promotion segment, wherein the initial value of the priority segment is 0x00, a dynamic priority algorithm is introduced, and when there is a node on the bus to send data to generate collision competition, the node with failed transmission can actively promote its priority, so that the node can be preferentially sent in the next non-periodic transmission time window.

The time-sensitive network control protocol design method based on the MLVDS bus can realize the following beneficial effects:

(1) Realizing distributed, completely centerless, multipoint-to-multipoint high-speed Mesh network transmission based on an MLVDS bus, allowing up to 32 nodes to be connected to one bus;

(2) A half duplex mechanism and an adaptive multi-master arbitration mechanism are commonly used, and any node can send own data to the bus when the bus is idle. When a plurality of nodes need to transmit data to the bus at the same time, only the node with the highest current priority can obtain the transmission right.

(3) The bus rate is high, the highest bus transmission rate can reach 100Mbps, and the node interconnection relation, the data volume and the communication frequency can be arbitrarily configured and adapted. Based on a high-speed time sensitive and service deterministic mechanism, the transmission delay of any node is less than 500us.

In one embodiment, as shown in fig. 2, a protocol hierarchy is provided, and the bus encoding mode of the MLVDS bus is a line or logic non-return-to-zero encoding mode.

In this embodiment, the physical layer is based on the MLVDS interface standard, and defines the characteristics of the drive receiver, bus coding, frame synchronization, and the like, and according to the IEEE802.3 standard, the physical layer includes a physical signaling sub-layer (PLS, physical Signaling), a physical media attachment (PMA, physical Medium Attachment), and a media related interface (MDI, medium Dependent Interface), where the PLS layer includes functions of coding and decoding, timing, and frame synchronization; the PMA layer defines the electrical interface such as the drive receiver; the MDI layer defines the mechanical interface of the connector, cable, etc.

In designing PLS sublayers, mainly for bus coding and bit synchronization modes, as shown in the NRZ encoded line or logic diagram of fig. 3, the bus may have one of two complementary logic values: "dominant" or "recessive". The bus adopts a ' line ' or ' mode, and when the ' dominant ' bit and the ' recessive ' bit are transmitted simultaneously, the result value of the bus is ' dominant '. A logic 0 (low) represents a "dominant" level and a logic 1 (high) represents a "recessive" level. The encoding of the bus uses non return to zero (NRZ) encoding, that is to say at the same instant the bus value is either "explicit" or "implicit". NRZ coding is a very common data coding method, which is easy to implement and has the highest efficiency, and has the disadvantage that the coding itself does not contain synchronous clock information, and self-synchronization between a transmitting end and a receiving end cannot be realized. In order to realize synchronous receiving, a synchronous clock is needed to be sent together with the codes, and in the invention, no self-synchronous problem of bits is needed to be considered no matter a message channel or a data channel is provided with the synchronous clock, and compared with coding modes such as Manchester coding and the like, the NRZ coding does not need to change the level in a single bit period, which is beneficial to improving the data transmission rate of a bus.

As shown in the bit synchronization pattern diagram of fig. 4, the present invention is a source clock pattern in which the bit synchronization is relatively simple because the clock and data are bit differences transmitted simultaneously. In the receiving process, the synchronous clock is only needed to be used for receiving.

As shown in fig. 2, the data link layer includes a logical link control sublayer (LLC, logicLinkControl) and a medium access control sublayer (MAC, media Access Control). The application layer message is packed into LLC frame format through LLC layer, LLC frame format includes 16 bit Identifier (IDE, identifier), 8 bit destination address (DSAP), 8 bit source address (SSAP), 16 bit Data Length (DLC) and 0-4096 byte Data text (Data), wherein the Identifier contains the attribute of the frame, the higher the value is, the higher the priority is, the specific division of the Identifier is determined by upper layer protocol; the destination address (DSAP) comprises an 8-bit address of the destination node; the source address contains 8-bit address information of the sending node, the address of each node in the bus is unique, the priority of the address is related to the absolute value of the address, and the higher the value is, the higher the priority is; the data length represents the length of the data body, the maximum allowable length is 4096 bytes at present in units of byte number, the length of the data body is variable, and the specific length is determined by the value of DLC.

The LLC sub-layer functions include a received message filtering function, a recovery management function and a buffer management function. The received message filtering function refers to that the receiver can determine whether the received message frame is related to itself through the message Wen Lvbo unit so as to determine whether the message is received; the recovery management function refers to that during transmission, for frames that are lost or interfered by errors, the LLC sub-layer has an automatic retransmission function; the buffer management function is to manage a sending buffer and a receiving buffer, for the sending buffer, the messages with high priority are guaranteed to be sent first according to the priority order of the messages, and for the receiving buffer, an overload notification is generated when the buffer overflows.

The LLC layer message filter has the function of judging whether the received message or data is related to the LLC layer message filter, and discarding the message or the data if the received message or the data is related to the LLC layer message filter and the received message or the data is not related to the LLC layer message filter. The reasonable design of the message filter can ensure that the message or data can correctly reach the target address, and ensure that other nodes on the bus do not receive the influence. The message Wen Lvbo is composed of a receiving code register ACR (Acceptance Code Register) and a receiving mask register AMR (Acceptance Mask Register), and has the same message filtering design as the CAN bus. The ACR and AMR are respectively 32-bit registers, and as shown in the corresponding relation diagram of the Wen Lvbo device in fig. 5, the corresponding relation between the ACR and AMR of the channel and the identifier IDE, the destination address DSAP and the source address SSAP of the LLC frame is shown. According to the corresponding relation, each bit of the frame head sequentially performs the following operation:

，

before each data reception, the filter state is set to 1, each bit is sequentially operated in the frame header receiving process, and if the operation result shows 0, the filter is not passed. If the frame header is received, the status is always 1, which means that the frame is filtered by the filter.

The MAC sublayer is located between the LLC sublayer and the physical layer and describes the underlying content of the data link layer. The MAC sublayer mainly functions as a transmission rule, i.e., control frame structure, performing arbitration, error detection, error calibration, and fault definition. According to the function of the MAC sublayer, two parts of transmission control and reception control may be divided, the transmission control including transmission data encapsulation and transmission medium access management, the transmission data encapsulation including: receiving LLC frames and interface control information; CRC calculation; appending a CRC and an ACK for the LLC frame to construct a MAC frame; transmitting media access management includes: confirming that the bus is idle, and starting a transmission process; MAC serialization/parallelization; in the case of lost arbitration, exit arbitration is only monitored; error detection; response checking; an overload condition is confirmed. The receiving control comprises receiving data analysis and interface media access management, wherein the receiving data analysis comprises: extracting MAC specific information from the received frame; outputting LLC frame and interface control information to LLC sub-layer; interface media access management includes: receiving, by a physical layer, a serial bit stream; releasing the serial/parallel structure and reconstructing the frame structure; error detection; transmitting a response; an overload condition is confirmed.

In one embodiment, the bus is determined to be in a bus idle state after a predetermined number of idle cycles of the clock signal occur consecutively. In this embodiment, each node that is ready to send a message sends a start of frame bit that attempts to occupy the bus when the bus is idle, and the start of frame bit completes the function of sending a request to the bus. The bus idle state is determined by the idle period of the clock signal. After the clock module sends the last frame of message, the clock module stops sending clock signals, the clock line state is 'recessive', and after 4 idle periods appear on the clock line, the bus is considered to be idle, and all nodes can start sending new messages.

In one embodiment, as shown in fig. 8, a schematic diagram of a frame synchronization process is provided, and before implementing non-destructive bitwise arbitration of multiple bus transmission nodes by using a carrier sense multiple access method, the method further includes: the bus transmitting node judges whether the bus is in a bus idle state, and when the bus is in the bus idle state, one bus transmitting node transmits a frame start bit on a bus data line at random; the frame start bit is dominant bit; after a clock module of the FPGA detects a frame start bit on a bus data line, starting to send a clock signal; the other bus nodes synchronize to the first rising edge of the clock signal, wherein the other bus transmitting nodes transmit new data frames on the bus data lines and the other bus nodes not transmitting new data frames transmit recessive bits on the bus signal lines to achieve frame synchronization.

In this embodiment, frame synchronization of the bus is performed by both the bus clock line and the data line. When a bus node is ready to transmit a new data frame, a one-bit "dominant" start of frame bit is transmitted on the bus data signal line to request transmission of the new data frame whenever bus idleness is detected at any time. After the clock module detects the "dominant" frame start bit on the data line, it starts to send the clock signal. All other nodes on the bus synchronize to the first rising edge of the clock and begin sending data frames. The messaging node is not ready, and the "recessive" bit is always sent. As can be seen from fig. 8, the duration of the start of frame bit is less than one cycle of the hour clock signal, and the clock module starts the messaging clock when the bus is idle and the "dominant" state on the data line is detected. The node 2 does not need to send a frame start bit, only needs synchronous clock signals, and sends message frames according to clock beats.

Fig. 9 is a schematic diagram describing a protocol control flow, and fig. 10 and 11 are schematic diagrams describing a bus state machine FSM logic when the node state is detected by a bus, where each node object has its own complete set of parameter space, including a series of parameters for controlling access to the bus, and each parameter is defined as follows according to the attribute of the node object:

node.no.: counting the number of times the node tries to access the bus;

node. Rs: bus transmission rate in Mbps;

node. Simdt: the node bus detects cycle beat time in microseconds;

node. Last_status: the last state of the node;

node.status: the current state of the node;

node. Detect_time: the node detection time is calculated according to the transmission time convention of 16 bus transmission bits (bits), namely 2 bytes in total, and the calculation formula is node (k), detect_time=16/node (k). Rs;

node. Detect_t0: the node bus detection starting time takes microseconds as a unit;

node. Detect_num: the number of times of collision detection of the node bus;

node.max_column_num: maximum collision times of node bus collision;

node. Idle_time: the node periodically transmits waiting interval duration in milliseconds;

node. Idle_t0: the node periodically transmits a waiting time counter in milliseconds;

node. Tx_time: the node periodically transmits the duration in milliseconds. If the node sends data quantity in each period to be XByte, node. Tx_time=X 8/node. Rs;

node. Tx_t0: node current data transmission start time, unit microsecond;

node. Tx_num: the node data accumulates the sending times;

node.t: node local clock counting;

defining the properties of the MLVDS bus object means that the parameters are defined as follows:

lvds_bus.status: the current state of the mlvds bus;

lvds_bus.txnode: the mlvds bus object currently sends the data node;

the node states are 5 kinds in total and are defined as follows:

1: detecting a state of a node bus;

2: node data transmission state, busy bus;

3: node idle state;

4: a node data reception state;

5: a data bus collision status;

node.status initial state is 1 (node bus detection state).

In one embodiment, the step of performing transmission scheduling on the plurality of periodic data with different priorities by adopting a preset bus time sensitive message transmission scheduling mechanism based on priority comprises the following steps: classifying the plurality of periodic data according to the periods corresponding to the plurality of periodic data to obtain a plurality of transmission queues with different periods; the method comprises the steps that the shorter the period of a specified transmission queue is, the higher the priority of data transmission is, when the transmission of a transmission queue with high priority is completed in a corresponding period, the data transmission of a transmission queue with next priority is entered, and when the transmission of a plurality of transmission queues is completed, the transmission of a plurality of periodic data is completed; the step of carrying out transmission scheduling on each aperiodic data by adopting a preset dynamic priority algorithm comprises the following steps: initializing a priority section of a data frame corresponding to each aperiodic data, wherein the initial priority corresponding to the initialized priority section is 0x00, and if the aperiodic data is a control instruction, defining the priority section of the control instruction according to the initial priority and the arbitration failure times; the aperiodic data includes control class instructions; judging the priority of the aperiodic data transmission according to the value of the identifier in the data frame corresponding to each aperiodic data; a plurality of bus transmitting nodes for transmitting the aperiodic data sequentially transmit the aperiodic data in one period according to the order of priority from big to small; when the non-periodic data failure of the bus sending node exists, the bus sending node with the failed sending actively promotes the priority of the bus sending node so as to ensure that the bus sending node sends the data preferentially in the burst time window of the next non-periodic data.

In this embodiment, a bus time sensitive message transmission scheduling mechanism based on priority is adopted for data transmission with different priorities in the same node. According to the bus interface summary table, according to the data quantity required to be transmitted by each module, calculating the transmission time required by each module, simulating the bus load condition in the early stage, and completing bus transmission by adopting a competitive random access mechanism. On bus message transmission scheduling, the method is realized based on a strategy combining competitive random access with dynamic priority promotion. The transmitted data is divided into two types for bus interface requirements: the periodic data are taken as examples for interconnection of buses of electronic systems in aircrafts such as missiles, satellites and the like, and the periodic data comprise telemetry parameters and measurement information of each subsystem; the other type is non-periodic data such as control instructions, and the frequency of sending such data is low.

Specifically, for periodic data, different transmission queues are formed according to different periods of data transmission by the nodes. In different queues, tasks with short period have high priority, and tasks with long period have low priority. The next stage of queue transmission is entered only after the task list of the higher stage completes transmission within its cycle period.

As shown in the priority promotion flow chart of fig. 12, for non-periodic data, when designing a dynamic priority algorithm, it is to ensure that a part of control class instructions have the highest priority whenever, for which the priority of the design of the control class instructions can be expressed as initial priority+number of arbitration failures. I.e. the more blanking failures, the higher the priority will be. If the node still cannot transmit the control command within one period, the priority of the priority segment in the extended frame is set to 0xFF, and the predetermined time in fig. 12 is a predetermined transmission period.

In one embodiment, the method further comprises: the method of intra-frame confirmation is adopted to confirm the received data frame; the method for intra-frame acknowledgement comprises the following steps: the bus sending node sends a data frame to the bus receiving node, and reads back the data on the bus and judges the response field delimiter; the bus receiving node confirms the correctness of the message in the process of sending the data frame, and makes the position of the response delimiter on the bus dominant so as to inform the bus sending node that the data frame is normally received, otherwise, informs the bus sending node to resend the data frame.

In this embodiment, the transmission control of the high-speed time-sensitive and service deterministic network based on the MLVDS bus adopts a bus response mechanism, and the data cannot be obtained correctly by the receiving end due to possible errors in the transmission of the data on the bus, thereby causing the loss of the data. To ensure reliable transmission of data, it is necessary to acknowledge the received data frame. For frames for which no corresponding acknowledgement is received, the sender may retransmit the frame. The intra-frame acknowledgement refers to that the sending node can read back the data on the bus and judge the response field delimiter when sending the data; the receiving node needs to confirm the correctness of the message in time and make the position of the response delimiter on the bus 'explicit' in the sending process of the sending node so as to inform the sending node that the data is normally received. Otherwise, indicating an error, the frame will be retransmitted. The intra-frame confirmation method effectively utilizes the line or characteristic of the MLVDS, so that the confirmation of data transmission does not need to construct an additional confirmation frame, and the efficiency of data transmission is improved.

Specifically, as shown in the schematic diagram of the bus response process in fig. 13, the response field length of the MAC frame is 3 clock cycles, and when the sender sends the CRC check bit, it immediately follows to send the "recessive" bit of 3 cycles, and starts to monitor the state of the bus from the second bit. After receiving the CRC check bit, the receiver sends an 'implicit' bit in the first period of the response field, sends the CRC check result in the second period, checks to correctly send the 'explicit' bit, sends the 'implicit' bit in the check error, sends the overload result in the third period, sends the 'implicit' bit if the buffer memory of the receiver is full or other reasons refuses to receive the frame, and sends the 'explicit' bit if the buffer memory is capable of normally receiving the frame. When the sender reads the dominant bit in the last two periods of the response field, the frame is indicated to be sent correctly, the LLC layer is sent to confirm the normal state, and otherwise, the abnormal state is sent. The recovery management mechanism of the LLC layer determines whether to retransmit or not based on the acknowledgement status.

In one embodiment, the method further comprises an error detection mechanism; error detection mechanisms include bit snooping, acknowledgement detection, and CRC checking. Specifically, bit snoop refers to the signal level transmitted by each transmitter on the bus that is read back, and if the read bit level is different from the transmitted bit level, a signal indicating a bit error is sent (no bit error is sent during arbitration). The reply detection means that the node on the bus which correctly receives the message expects to send a dominant level in the reply time slot in the message, and the sending node sends the dominant level in the reply time slot after sending a frame, if the sender cannot detect the dominant level in the reply time slot, an error signal can be sent, and the frame needs to be retransmitted. The CRC check means that each message contains a 16-bit CRC, and if a node detects a CRC different from the CRC calculated by itself in the message, the node discards the frame data and sends a negative acknowledgement result in the acknowledgement field.

The workflow diagram of the data link layer shown in fig. 14, wherein the bus transmission mainly comprises a transmission controller, a transmission shift register, a CRC generation function module, a bus collision detection function module, a response detection function module, and the like. The bus receiving is mainly composed of a receiving controller, a receiving shift register, CRC detection, message filtering, response generation and other functional modules.

The bus transmit workflow diagram shown in fig. 15, the bus receive workflow diagram shown in fig. 16,

when a node on the MLVDS bus starts to transmit data, each node will receive the data through the receiving module. The receiving module reads the value of the MLVDS bus according to the bits under the cooperation of the bit timing module, and the bit decoding is needed to be firstly carried out in the field coded by the bits and then the bit is stored in the register. After receiving the CRC field, checking the CRC sequence, if the check is successful, sending a dominant bit in the gap of the response field to indicate that the data is correctly received, continuing to receive the response delimiter and the end of the frame, and if the check is wrong, discarding the frame. And after the data frame is completely received, checking the identifier, and determining whether the data frame is received or not by each receiving node through the identifier. If the node receives the data frame, the data is stored in a register to wait for being read and used.

In one embodiment, a frequency of communication for an electronic system requires a period of 1ms at maximum. Establishing an array model of data volume and transmission frequency:

x=[207,27,25,26,20,168,390,25,40,26,75,27,201,220,1500,1500,30,44,30,30]；

y=[50,1,10,1,1,1,100,100,10,1,1,1,50,50,10,10,1,1,20,20]；

where x is the data amount, the unit is bytes, y is the transmission frequency, and the unit is ms.

The states of the simulation nodes comprise five types of bus detection, data transmission, node idleness, node receiving and bus collision. The sequence of the simulation node random detection buses respectively simulate the maximum delay times of node collision and the bus collision distribution, the simulation detection interval is 1us, the state detection time is 16us, the simulation result is shown in fig. 17, which shows a schematic diagram of the maximum delay times of node collision, fig. 17 is a simulation of the bus transmission collision conditions of 20 nodes transmitted according to the set traffic, the collision times of each node can be seen to be about 300 times, and the collision delay is about 300us due to the simulation interval, so that the transmission frequency requirement of 1ms is met. And (3) carrying out experiments on time distribution of bus transmission collision of 20 simulation nodes in a simulation time length of 1-5000 us. Further, the total bus traffic aggregate rate is about 6.18Mbps calculated from the data amount and the transmission frequency, and the bus idle rate is about 93% according to the design index MLVDS bus transmission rate of 100Mbps.

It should be understood that, although the steps in the flowcharts of fig. 14, 15, and 16 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 14, 15, and 16 may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, or the order of execution of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least some of the other steps or sub-steps of other steps.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A time-sensitive network control protocol design method based on an MLVDS bus, the method comprising:

if a plurality of bus sending nodes obtaining the bus floor at the current moment all need to send aperiodic data, carrying out transmission scheduling on each aperiodic data by adopting a preset dynamic priority algorithm;

the step of carrying out transmission scheduling on each aperiodic data by adopting a preset dynamic priority algorithm comprises the following steps:

initializing a priority section of a data frame corresponding to each aperiodic data, wherein the initial priority corresponding to the initialized priority section is 0x00, and if the aperiodic data is a control instruction, defining the priority section of the control instruction according to the initial priority and the arbitration failure times; the aperiodic data includes control class instructions;

judging the priority of the aperiodic data transmission according to the value of the identifier in the data frame corresponding to each aperiodic data;

the bus sending nodes for sending the aperiodic data sequentially send the aperiodic data in one period according to the order of the priorities from large to small;

when the non-periodic data failure of the bus sending node exists, the bus sending node with the failed sending actively promotes the priority of the bus sending node so as to ensure that the bus sending node sends the non-periodic data in the next non-periodic sending time window.

2. The method of claim 1, wherein the step of using a pre-set priority-based bus time sensitive message transmission scheduling mechanism to schedule transmission of a plurality of periodic data of different priorities comprises:

classifying the plurality of periodic data according to the periods corresponding to the plurality of periodic data to obtain a plurality of transmission queues with different periods;

the shorter the period of the specified transmission queue is, the higher the priority of data transmission is, when the transmission of the transmission queue with high priority is completed in the corresponding period, the data transmission of the transmission queue with next priority is entered, and when the transmission of the transmission queues is completed, the transmission of the periodic data is completed.

3. The method according to claim 1, wherein the method further comprises:

and after the clock signal continuously generates a preset number of idle periods, judging that the bus is in a bus idle state.

4. The method of claim 1, further comprising, prior to implementing the non-destructive bitwise arbitration of the plurality of bus sending nodes using a carrier sense multiple access method:

the bus transmitting node judges whether the bus is in a bus idle state, and when the bus is in the bus idle state, a certain bus transmitting node transmits a frame start bit on a bus data line; the frame start bit is a dominant bit;

after the clock module of the FPGA detects the frame start bit on the bus data line, the clock module starts to send a clock signal;

the other bus nodes synchronize to the first rising edge of the clock signal, wherein the other bus transmitting nodes transmit new data frames on the bus data lines, and the other bus nodes which do not transmit new data frames transmit recessive bits on the bus signal lines, so that frame synchronization is realized.

5. The method of claim 1, wherein the acknowledgement field comprises an acknowledgement gap, an acknowledgement delimiter, an overload result, and a reserved bit.

6. The method of claim 5, wherein the method further comprises:

the method of intra-frame confirmation is adopted to confirm the received data frame; the method for intra-frame acknowledgement comprises the following steps:

the bus sending node sends a data frame to the bus receiving node, and reads back the data on the bus and judges the response field delimiter;

and the bus receiving node confirms the correctness of the message in the sending process of the data frame, and makes the position of the response delimiter on the bus dominant so as to inform the bus sending node that the data frame is normally received, otherwise, informs the bus sending node to resend the data frame.

7. The method of claim 6, further comprising an error detection mechanism; the error detection mechanism comprises bit monitoring, response detection and CRC check;

when the bit monitoring comprises the step of reading back the transmitted level at a transmitter of a bus transmitting node, if the read bit level is different from the transmitted bit level, a signal is sent to indicate bit errors;

the response detection comprises that a bus sending node detects whether a dominant level exists in a response time slot, if the dominant level is not detected, an error signal is sent, and the bus sending node retransmits a currently transmitted data frame;

the CRC check comprises that when the bus node detects CRC different from the calculated CRC in the sending message, the current data frame is discarded, and a negative acknowledgement result is sent in an acknowledgement field.

8. The method of claim 1, wherein the bus encoding of the MLVDS bus is a line or logic non-return to zero encoding.

9. The method of claim 1, wherein the MLVDS bus has a highest bus transfer rate of 100Mbps.