KR100455115B1 - De-interleaving circuit of grand alliance hdtv for using memory effectively - Google Patents

Abstract

PURPOSE: A de-interleaving circuit of a grand alliance HDTV(High Definition Television) is provided to apply change of a memory allocation according to the progress of time such as a convolutional type when performing the de-interleaving, thereby removing an unnecessary occupying period and using the memory effectively. CONSTITUTION: An address control member(100) is synchronized by a received data frame SYNC(SYNChronization) signal and data SYNC signal, transmits the received data according to a VSB(Vestigial SideBand) mode and also designates an inherent memory of a memory bank(200). When the address control member designates the inherent memory through a logical combination of a write enable signal and a read enable signal, the memory bank stores/outputs data transmitted from the address control member to/from the memory. A multiplexer(300) is enabled by the logical combination of a read enable signal of the address control member and read address signals and outputs finally the output signal of the memory bank.

Description

Grand Alliance HDTV Decoding Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit of a Grand Alliance High Definition TV (HDTV), and in particular, to implement a de-interleaving in a convolutional manner in decoding, thereby making it suitable for improving the efficiency of memory. The Grand Alliance is about the high definition TV's decoding circuit.

Referring to FIG. 1, the operation of a conventional Grand Alliance high definition TV decoding circuit is as follows.

In the Grand Alliance high-definition TV, residual sideband (VSB) modulation is performed. In this case, as shown in FIG. 3, a modulation modulation is performed to disperse cluster errors concentrated in one codeword into irregular errors in multiple codewords.

Therefore, the receiving end performs decoding even when decoding the data. If data is received, the data is stored in the corresponding memory 201-20n in the enabled memory bank 20 under the control of the address controller 10.

At this time, as shown in FIG. 2, one-third of the 312 segments, ie, 103 segments, excluding the frame synchronization among the 313 segments, are distributed and stored in each memory 201-20n.

To implement this, the capacity of the memory bank 20 requires at least 2704 bytes * 4, that is, 10 kilobytes or more.

When the storage is completed as described above, the multiplexer 30 is controlled to select the output signal of the corresponding memory in which data corresponding to one frame is stored and to be output in order.

As described above, since the conventional circuit is interval interpolation decoding, even a section without actual data occupies the memory, thereby reducing the efficiency of the memory.

The object of the present invention is to solve the conventional problems by applying a change in memory allocation over time, such as in convolutional stitching modulation, in decoding, thereby eliminating unnecessary occupancy intervals so that the memory can be efficiently used. It is to provide a decoding circuit of the TV.

1 is a block diagram of a conventional Grand Alliance high-definition TV decoding circuit.

2 is a schematic diagram of a residual side band (VSB) frame.

3 is a conceptual diagram of weaving stitching modulation;

4 is a decoding circuit diagram of the present invention Grand Alliance high-definition TV.

5 is a VHDFL implementation of DEINTCTL-P-mksc of an address control unit;

***** Description of the symbols for the main parts of the drawings *****

100: address control unit 200: memory bank

300: multiplexer

To achieve the object of the present invention, the Grand Alliance high-definition TV decoding circuit is synchronized according to the received data frame synchronization signal (Fsync) and the data synchronization signal (DSsync), and received according to the remaining side band (VSB) mode. Address control means for transferring data and designating a unique memory of the memory means; Memory means for storing / outputting data transmitted from said address control means when a unique memory is designated by a logical combination of a write enable signal WEN and a read enable signal RENB in said address control means; And a switching means which is enabled by a logical combination of the lead enable signal RENB and the lead address signals 12 and 11 of the address control means and finally outputs the output signal of the memory means.

Hereinafter, an embodiment will be described with reference to the operation and effects of the present invention.

4 is an exemplary embodiment of the present invention, as shown in FIG. 4, which is synchronized according to the received data frame synchronization signal Fsync and the data synchronization signal DSsync, and is received according to the remaining side band VSB mode. An address controller 100 which transmits data and designates a unique memory of the memory bank 200; When the address controller 100 designates a unique memory through a logical combination of the write enable signal WEN and the read enable signal RENB, the address controller 100 stores / outputs data transmitted from the address controller 100 in the corresponding memory. A memory bank 200; The multiplexer 300 is enabled by a logical combination of the read enable signal RENB and the read address signals 12 and 11 of the address controller 100 to finally output the output signal of the memory bank 200. do.

Operation of one embodiment of the present invention configured as described above is as follows.

The address controller 100 is synchronized according to the frame sync signal Fsync and the data sync signal DSsync according to the remaining side band VSB data frame, and receives 8-bit data according to the remaining side band VSV mode. Transfer it to the memory bank 200.

At this time, the write enable signal WEN is activated when writing to the memory, and the read enable signal RENB is activated when reading.

Each of them generates a valid write address and lead address.

In particular, the upper two bits of the write address and the read address are logically combined with the write enable signal WEN and the read enable signal RENB in the address controller 100 to designate a unique memory of the memory bank 200.

In the memory bank 200, the first memory is activated and written when the write enable signal WEN and the write address signals 12 and 11 are both 'low' in the case of the write operation.

At this time, the address causes the column address to repeatedly increase as the row address increases.

On the contrary, in the case of the read operation, when both the read enable signal RENB and the read addresses 12 and 11 are 'low', the first memory is activated and read. At this time, as the address increases, the row address is repeatedly increased.

The multiplexer 300 is enabled by the logical combination of the read enable signal RENB and the read address signals 12 and 11 to output the final signal y [7: 0].

This reduces the memory capacity by half compared to the conventional one.

If the DEINTCTL-P-mksc of the address controller 100 is implemented with VHDFL, it is as shown in FIG.

As described in detail above, the present invention has the effect that the memory can be efficiently used by eliminating the unnecessary occupation period by applying the change in memory allocation over time as in the convolutional fit modulation.

Claims (1)

Address control means for synchronizing according to the received data frame synchronization signal Fsync and the data synchronization signal DSsync, transmitting the received data according to the remaining side band VSB mode, and designating a unique memory of the memory means. and; Memory means for storing / outputting data transmitted from said address control means when a unique memory is designated by a logical combination of a write enable signal WEN and a read enable signal RENB in said address control means; A grand alliance high-definition comprising a switching means which is enabled by a logical combination of the lead enable signal RENB and the lead address signals 12 and 11 of the address control means and finally outputs the output signal of the memory means. TV's decoding circuit.

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