KR100285420B1 - Variable length coder in HDTV - Google Patents

Abstract

According to the present invention, a variable definition of a high-definition television is provided such that the read / write times of a part generating a video code by variable encoding the input video data and a part outputting the code at a desired bit rate are appropriately adjusted without overlapping by a time division method. The present invention relates to an encoder. In accordance with the present invention, 128 cycles are divided in time based on a macroblock according to a header signal and a synchronization signal input from a timing signal generator, and 117 cycles are allocated as cycles for writing data to RAM. The cycle is allocated to read the data stored in the RAM, and the remaining one cycle is allocated to the slice header data generation cycle, and the 117 cycles allocated for recording are 3 cycles when the color difference signal structure is 4: 2: 0. Allocates to generate a macroblock (MB) header, and assigns six blocks (predetermined 19 cycles are allocated to each block, and the 19 cycles allocated to each block are read using unidirectional SRAM by generating a timing signal such that 1 cycle for DC processing and 18 cycles for AC processing are generated. Coded data can be processed without duplication of writes.

Description

Variable length coder in HDTV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable encoder in a high-definition television (HDTV). In particular, the time / division method of the read / write time of a portion generating a video code by variably encoding input video data and outputting the code at a desired bit rate. The present invention relates to a variable encoder of a high-definition television that can be adjusted appropriately without being duplicated.

In general, the parts of variable encoding in a video encoder of a high-definition television (HDTV) are roughly divided into portions for variable encoding of video data that is largely input to generate a video code and portions for outputting the encoded code at a desired bit rate. Because these two parts operate independently of each other, their clocks are different.

In the conventional video encoder, a variable encoding method includes a timing in which a portion of a bit generated using a memory capable of bidirectional read / write is written into a memory and a portion of data read from the memory and output at a desired bit rate is overlapped. Do not

However, this conventional method is subject to the constraint that the memory size must be quite large when high bit rates are required. For example, 4Mbit of memory is required to support 120Mbps video rate.

In addition, since the memory capable of bidirectional read / write is small, a large number of memories are required to support a high bit rate, which causes a lot of space and cost problems in system design.

Accordingly, the present invention has been proposed to solve various problems occurring in the conventional video encoder as described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-definition image that is appropriately adjusted without overlapping the read / write times of a portion generating a video code by variably encoding the input video data and a portion outputting the code at a desired bit rate by a time division method. The present invention provides a variable encoder of a television.

The present invention for achieving the above object,

Header information and timing signal for generating video data and slice header data by adding slice header information to input macroblock data, and generating a timing signal for processing the generated video data by time division based on the macroblock. A generator;

A picture header generator for generating a picture header according to the header information and a timing signal obtained from the timing signal generator;

A data packing unit for packing macroblock data, slice header data, and picture header data generated by the header information and timing signal generator and the picture header generator;

An address generator for generating a write / read address for storing and reading the video data packed by the data packing unit according to the header information and the timing signal obtained from the timing signal generator;

A RAM for recording and reading the packed video data according to a write / read address obtained from the address generator;

First and second first-in, first-out and first-in-first-out units for storing video data obtained from the RAM and outputting the stored data in predetermined units under the control of a buffer controller;

Characterized in that the buffer control unit for controlling the recording and reading of the first and second first-in-first-out and output the read data in byte unit.

1 is a block diagram of a variable encoder of a high definition television according to the present invention;

2 is a picture processing timing diagram and a macroblock processing timing diagram in FIG.

<Explanation of symbols for main parts of the drawings>

10: header information and timing signal generator

20: picture header generator 30: data generator

40: address generator 50: RAM

61, 62: first and second first-in, first-out machines

70: buffer control unit

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

1 is a block diagram of a variable encoder of a high definition television according to the present invention.

Here, reference numeral 10 denotes video data and slice header data by adding slice header information to the input macroblock data (MB Data), and time division based on the macroblock to process the generated video data. Header information for generating a timing signal and a timing signal generator, 20 is a picture header generator for generating a picture header according to the header information and a timing signal obtained from the timing signal generator 10, and 30 is the header information and The data packing unit packs macroblock data, slice header data, and picture header data generated by the timing signal generator 10 and the picture header generator 20, respectively.

Further, reference numeral 40 is an address generation for generating a write / read address for storing and reading the video data packed by the data packing unit 30 according to the header information and the timing signal obtained from the timing signal generator 10. 50 is a RAM for recording and reading the packed video data according to the write / read address obtained from the address generator 40, 61, 62 stores video data obtained from the RAM 50, First and second first-in, first-out first-out machines that output the stored data in predetermined units under the control of the buffer controller 70 at a later stage, and 70 denotes recording of the first and second first-in first-out machines 61 and 62. And a buffer control unit for controlling the reading and outputting the read data in byte units.

The variable encoder according to the present invention configured as described above first adds slice header data to the input macroblock data MB Data according to the header information and the synchronization signal sync [4] input from the timing signal generator 10. Generate macroblock data and header data, and generate timing signals capable of processing data by time division based on the macroblocks.

That is, the header information and timing signal generator 10 generates a timing signal by using the input synchronization signal. Since the synchronization signal is generated every 128 cycles, the counter is operated according to the synchronization signal to write a recording cycle. And read cycles. In other words, since each macroblock consists of 128 cycles as shown in (d) of FIG. 2, the macroblocks are divided in time, and 117 cycles divided as shown in (e) are allocated as cycles for writing data to the RAM 50, and ( The divided 10 cycles as in f) are allocated to cycles for reading the data stored in the RAM 50. Here, 117 cycles allocated as write cycles for writing data to the RAM 50 are allocated three cycles to generate a macroblock (MB) header as in (g) when the color difference signal structure is 4: 2: 0. 19 cycles are allocated for 6 blocks (blocks in which macroblocks are divided into predetermined blocks). In addition, 19 cycles allocated to each block are allocated 1 cycle for DC processing and 18 cycles for AC processing. In this case, the maximum possible bit is 6816 bits per macroblock, which satisfies the maximum number of bits 4608 bits per macroblock proposed by MPEG2. In addition, 10 cycles allocated for reading data recorded in the RAM 50 generate 640 bits per macroblock when the data processing is 64 bits. Thus, up to 160Mbps can be supported for 1920 * 1080 images. One cycle out of the 128 cycles of the macroblock is allocated to generate slice header information. When data is generated and stored at this timing and the stored data is read out, data is generated only during the write cycle as a whole of the system, and no data is generated during the read cycle.

On the other hand, the picture header generator 20 generates picture header information according to the header information and the timing signal obtained from the timing signal generator 10, where the picture header information is also generated only during the recording cycle.

Next, the data packing unit 30 packs the slice header information obtained from the header information and the timing signal generator 10, the macroblock data, and the picture header information obtained from the picture header generator 20 into 64 bits.

The packed 64-bit data is transferred to the RAM 50 through the address generator 40, and the address generator 40 writes the address according to the synchronization information obtained from the header information and the timing signal generator 10. And a read address.

The write address and read address generated as described above are transferred to the RAM 50 to store the packed 64-bit or read the stored data. The RAM 50 here is a one-way SRAM. As in the prior art, the use of bidirectional esram has the advantage of independently performing read / write without time division. On the other hand, bidirectional esram has a problem that a large number of data is used due to the small storage size of data. In the present invention, by using unidirectional SRAM and controlling the write / read address, high bit rate data processing is possible without duplication of write / read time.

On the other hand, the 64-bit data output from the RAM 50 is stored in the first and second first-in first-out (61) 62 (62), respectively, in order to make the final output in the byte unit and then output in the byte unit.

Here, the first and second first-in, first-out (61) 62 has a characteristic of outputting data by 1 byte after receiving 4 bytes of data, respectively, which is controlled by the buffer controller 70. In other words, the buffer controller 70 performs four reads for the first-in, first-out machine 61, and performs four reads for the second first-in, first-out machine 62 for the next four cycles. By using two first-in, first-outs as described above, a complicated read timing that requires reading data one by one while sequentially buffering 64-bit data can be avoided.

In addition, the buffer controller 70 outputs the read data in 8 bits, and also outputs a data clock when the data is output.

As described above, according to the present invention, by processing the data by time division, the processing time per block, processing time per macroblock, processing time per slice, and processing time per picture can be fixedly allocated to each processing block. It is possible to avoid party timing conflicts and to avoid write / read duplication, thereby improving the stability of system operation.

In addition, since video data can be processed using a low-cost one-way memory instead of a high-cost two-way memory, hardware cost can be reduced when configuring a system.

Claims (4)

In the encoder for variably encoding the input video data to generate a video code, and outputs the generated code at a desired bit rate, Header information and timing signal for generating video data and slice header data by adding slice header information to input macroblock data, and generating a timing signal for processing the generated video data by time division based on the macroblock. A generator; A picture header generator for generating a picture header according to the header information and a timing signal obtained from the timing signal generator; A data packing unit for packing macroblock data, slice header data, and picture header data generated by the header information and timing signal generator and the picture header generator; An address generator for generating a write / read address for storing and reading the video data packed by the data packing unit according to the header information and the timing signal obtained from the timing signal generator; A RAM for recording and reading the packed video data according to a write / read address obtained from the address generator; First and second first-in, first-out and first-in-first-out units for storing video data obtained from the RAM and outputting the stored data in predetermined units under the control of a buffer controller; And a buffer controller for controlling the recording and reading of the first and second first-in-first-out machines and outputting the read data in byte units. The high-definition television set as claimed in claim 1, wherein the header information and timing signal generator generates data write and read timing signals by time-dividing 128 cycles based on a macroblock according to an input synchronization signal. Variable encoder. The method of claim 2, wherein the header information and timing signal generator divides 128 cycles in time, allocating 117 cycles as cycles for writing data to RAM, and 10 cycles as cycles for reading data stored in the RAM. And one remaining cycle is allocated to slice header data generation cycles. The method of claim 3, wherein the 117 cycles allocated for recording are allocated three cycles to generate a macroblock (MB) header when the color difference signal structure is 4: 2: 0. 19 cycles are assigned to each block, and 19 cycles assigned to each block are allocated 1 cycle for DC processing and 18 cycles for AC processing.