KR100418584B1 - Method for fabrication of capacitor of ferroelectric random access memory - Google Patents
Method for fabrication of capacitor of ferroelectric random access memory Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
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- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 74
- 239000011229 interlayer Substances 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 12
- 229910052697 platinum Inorganic materials 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
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- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
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- 238000003860 storage Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 19
- 230000010287 polarization Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
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- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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Abstract
본 발명은 전기화학적 박막 성장방법을 이용하여 3차원 구조의 강유전체 캐패시터의 제조방법에 있어서, 서로 다른 습식식각률을 가지는 절연막을 반복하여 증착하여 형성된 굴곡을 가진 스토리지노드 홀에서, 캐패시터의 하부전극 스택을 ECD법으로 성장시킴으로서, 캐패시터의 유효 표면적을 늘리는 효과가 있으며, 또한 스택 구조의 캐패시터로서 전기적 특성이 우수하고, 단차피복성이 우수한 효과가 있다.The present invention provides a method for manufacturing a ferroelectric capacitor having a three-dimensional structure by using an electrochemical thin film growth method, wherein the lower electrode stack of the capacitor is formed in a storage node hole having a curved formed by repeatedly depositing insulating films having different wet etch rates. By growing by the ECD method, there is an effect of increasing the effective surface area of the capacitor, and also has an effect of excellent electrical characteristics as a capacitor of the stack structure and excellent step coverage.
Description
본 발명은 FeRAM(Ferroelectric Random Access Memory)의 캐패시터 제조방법에 관한 것으로 특히 캐패시터의 하부전극의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a FeRAM (Ferroelectric Random Access Memory), and more particularly, to a method of manufacturing a lower electrode of a capacitor.
FeRAM은 강유전체(Ferroelectric Material)의 분극반전과 히스테리시스(Hysteresis) 특성을 이용한 비휘발성(Nonvolatile) 기억소자의 일종으로서 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 DRAM과 같은 고속, 대용량, 저전력을 가질 수 있는 이상적인 메모리이다.FeRAM 소자의 강유전체 유전물질로는 SrBi2Ta2O9(이하 SBT라 한다), (SrxBi2-y(TaiNbj)2O9-Z)(이하 SBTN라 한다), Pb(ZrxTi1-X)O3(이하 PZT라 한다), SrTiO3(이하 ST라 한다), Bi4-xLaxTi3O12(이하 BLT라 한다)박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(Remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(Nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.FeRAM is a nonvolatile memory device that uses the polarization reversal and hysteresis characteristics of ferroelectric material. It has the advantage of storing the stored information even when the power is cut off. The ferroelectric dielectric material of the FeRAM device is SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT), (Sr x Bi 2-y (Ta i Nb j ) 2 O 9-Z ) ( (Hereinafter referred to as SBTN), Pb (Zr x Ti 1-X ) O 3 (hereinafter referred to as PZT), SrTiO 3 (hereinafter referred to as ST), Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT) This is mainly used. Ferroelectrics have hundreds to thousands of dielectric constants at room temperature and have two stable Remnant polarization states, making them thinner and realizing their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
FeRAM은 집적도가 향상될수록 잔류분극값의 향상이 요구된다. 잔류분극값의 향상에는 분극값이 높은 물질을 사용하는 방법과 캐패시터의 구조를 3차원으로 하는 방법이 있다.As the degree of integration of FeRAM increases, the residual polarization value needs to be improved. There are two methods for improving the residual polarization value: a method using a material having a high polarization value, and a method of making the capacitor structure three-dimensional.
이 중 캐패시터의 전극구조를 3차원으로 하는 방법은 기판의 활성영역(active region)과 도전물질로 연결되는 콘택플러그 상에 캐패시터를 바로 형성한다. 3차원 캐패시터의 구조로는 크게 스택 구조, 컨캐이브 구조로 구분된다.Among these methods, a three-dimensional electrode structure of a capacitor forms a capacitor directly on a contact plug connected to an active region of a substrate and a conductive material. The structure of the three-dimensional capacitor is classified into a stack structure and a convex structure.
그런데 스택형 구조가 컨캐이브 구조보다 캐패시터의 전기적 특성 확보 측면에서 유리하다. 그 이유는 스택 구조가 컨캐이브 구조보다 우수한 단차피복성(Step coverage) 특성 및 스택의 상부와 하부 사이의 조성 차이를 최소화 할 수 있기 때문이다. 하지만 단순 스택(Simple stack) 캐패시터는 금속 하부전극을 기존의 CVD(Chemical Vapor Deposition)법으로 하부전극 증착 후 식각 공정에 의해 패터닝(Patterning) 하는 경우 식각의 어려움이 있다. 그 이유는 하부전극으로 쓰이는 노블 금속은 매우 단단하고 안정된 내열성(Refractory) 금속이기 때문에 다른 화학물질과 반응하기 어렵기 때문이다. 비록 하부전극을 반응성 이온 식각(Reactive Ion Etching, RIE)으로 패터닝하는 것이 가능하나 현실적으로 장비의 성숙도(Maturity)로는 측벽경사(Sidewall slope) 문제가 있다. 또한 노블 금속의 식각 난이성으로 인해, 이보다 낮은 식각률을 갖는 식각마스크 재료를 확보하는 것이 어려운 문제점이 있다.However, the stacked structure is advantageous in terms of securing the electrical characteristics of the capacitor than the concave structure. This is because the stack structure can minimize the step coverage characteristics superior to the concave structure and the difference in composition between the top and bottom of the stack. However, a simple stack capacitor has difficulty in etching when the metal lower electrode is patterned by an etching process after depositing the lower electrode by a conventional chemical vapor deposition (CVD) method. The reason is that the noble metal used as the lower electrode is very hard and stable refractory metal, and thus it is difficult to react with other chemicals. Although it is possible to pattern the lower electrode by reactive ion etching (RIE), in reality, there is a sidewall slope problem as the maturity of the equipment. In addition, due to the etching difficulty of the noble metal, it is difficult to secure an etching mask material having a lower etching rate than this.
따라서, 현재 스택구조는 전기화학적 박막성장(Electro-Chemical Deposition; 이하 ECD법이라 한다)으로 스택구조를 형성하는 방법이 다양하게 연구되고 있다.Therefore, the stack structure is currently being studied in various ways to form the stack structure by the electrochemical thin film growth (ECD method).
ECD법은 하부전극 도전층이 시드층 도체 상에만 석출되고, 부도체상에서는 석출되지 않는다는 선택적 성장의 특징을 이용하여 하부전극을 스택 구조로 성장시킨다. 따라서 전기적 특성과 단차피복성이 우수한 스택 구조의 하부전극을 형성할 수 있다.The ECD method grows the lower electrode in a stack structure by utilizing the characteristic of selective growth that the lower electrode conductive layer is deposited only on the seed layer conductor and not on the insulator. Therefore, the lower electrode of the stack structure having excellent electrical characteristics and step coverage can be formed.
도 1a 내지 도 1d는 종래 ECD법에 의한 IrOx시드층 상에 백금 하부전극 스택의 캐패시터 형성 공정을 도시한 단면도로서, 이를 참조하여 종래의 캐패시터 형성 공정을 살펴 본다.도 1a는 종래기술에 따른 ECD법으로 백금 하부전극(155)을 성장시킨 단면도이다.1A to 1D are cross-sectional views illustrating a capacitor forming process of a platinum lower electrode stack on an IrO x seed layer by a conventional ECD method, with reference to this. FIG. 1A illustrates a conventional capacitor forming process. It is sectional drawing which grew the platinum lower electrode 155 by ECD method.
반도체기판(100) 상의 소정영역에 활성영역(110)과 비활성영역을 한정하는 소자분리막(105)을 형성한다. 그리고 도면에는 도시되어 있지 않지만 모스트랜지스터와 비트라인을 형성하고, 제1 층간절연막(115)을 형성한다. 제1 층간절연막(115)을 형성한 후, 제1 층간절연막(115)을 관통하여 반도체기판(100)의 활성영역(Active region, 110)과 연결되는 스토리지 콘택홀(도시하지 않음)을 형성한다. 콘택홀을 폴리실리콘(120), 실리사이드층(125)으로 채워 도전성 플러그를 형성한다. 상기 도전성 플러그 상부에 TiN층(130)/Ir층(135)을 패터닝하고, 제2 층간절연막(140)을 증착하고 평탄화 한다.평탄화된 전체 구조 상에 IrOx시드층(145)과 제3 층간절연막(150)을 형성하고, 제3 층간절연막(150)을 선택적으로 식각하여 하부전극이 형성될 부분을 개방한다. 다음으로 IrOx시드층(145)에 전류를 공급하여 백금 하부전극(155)을 성장시킨다.An isolation layer 105 is formed in a predetermined region on the semiconductor substrate 100 to define the active region 110 and the inactive region. Although not shown in the drawing, a MOS transistor and a bit line are formed, and a first interlayer insulating film 115 is formed. After forming the first interlayer insulating film 115, a storage contact hole (not shown) connected to the active region 110 of the semiconductor substrate 100 is formed through the first interlayer insulating film 115. . The contact hole is filled with the polysilicon 120 and the silicide layer 125 to form a conductive plug. The TiN layer 130 / Ir layer 135 is patterned on the conductive plug, and the second interlayer insulating layer 140 is deposited and planarized. The IrO x seed layer 145 and the third interlayer are formed on the entire planarized structure. The insulating layer 150 is formed, and the third interlayer insulating layer 150 is selectively etched to open a portion where the lower electrode is to be formed. Next, the platinum lower electrode 155 is grown by supplying a current to the IrO x seed layer 145.
도 1b는 종래기술에 따른 백금 하부전극 패턴(155a)을 형성한 단면도이다.1B is a cross-sectional view of the platinum lower electrode pattern 155a according to the related art.
제3 층간절연막(150)을 습식식각(Wet etch)으로 제거하여 백금 하부전극 패턴(155a)을 형성한다.The third interlayer insulating layer 150 is removed by wet etching to form the platinum lower electrode pattern 155a.
도 1c는 종래기술에 따른 IrOx시드층 패턴(145a)이 형성된 단면도이다.1C is a cross-sectional view of the IrO x seed layer pattern 145a according to the related art.
백금 하부전극 패턴(155a)을 형성하고 기판(100) 전면을 에치백(Etch back) 공정을 이용하여 IrOx시드층(145)을 분리하여 IrOx시드층 패턴(145a)을 형성한다.The platinum lower electrode pattern 155a is formed and the IrO x seed layer 145 is separated from the entire surface of the substrate 100 by using an etch back process to form an IrO x seed layer pattern 145a.
도 1d는 종래기술에 따른 유전체막(160)과 상부전극(165) 형성한 단면도이다. IrOx시드층 패턴(145a)을 형성하고 유전체막과 상부전극 도전층을 증착하고 패터닝한다1D is a cross-sectional view of the dielectric film 160 and the upper electrode 165 according to the related art. IrO x seed layer pattern 145a is formed, and a dielectric film and an upper electrode conductive layer are deposited and patterned.
상술한 종래 ECD법에 의하여 형성되는 스택구조는 식각의 어려움을 피할 수 있는 장점이 있지만, 하부전극이 단순한 스택 구조로서 캐패시터의 유효 표면적이 작다는 문제점이 있다.Although the stack structure formed by the above-described conventional ECD method has an advantage of avoiding the difficulty of etching, there is a problem that the effective surface area of the capacitor is small as the lower electrode is a simple stack structure.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 전기화학적 박막 성장방법을 이용하여 캐패시터의 하부전극 유효 표면적을 극대화한 3차원 스택 구조의 강유전체 메모리 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, to provide a method of manufacturing a capacitor of the ferroelectric memory device of the three-dimensional stack structure to maximize the effective surface area of the lower electrode of the capacitor using an electrochemical thin film growth method. have.
도 1a 내지 도 1d는 종래 ECD법에 의한 IrOx시드층 상에 백금 하부전극 스택의 캐패시터 형성 공정을 도시한 단면도.1A to 1D are cross-sectional views illustrating a process for forming a capacitor of a platinum lower electrode stack on an IrO x seed layer by a conventional ECD method.
도 2a 내지 도 2e는 본 발명에 따른 ECD법에 의한 강유전체 캐패시터 형성 공정을 도시한 단면도.2A to 2E are sectional views showing a ferroelectric capacitor forming process by the ECD method according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
200 : 반도체기판 245 : IrOx시드층200: semiconductor substrate 245: IrO x seed layer
260 : 제3 층간절연막 270 : 하부전극260: third interlayer insulating film 270: lower electrode
275 : 유전체막 280 ; 상부전극275: dielectric film 280; Upper electrode
상기 목적을 달성하기 위한 본 발명은, 반도체 기판 전면에 IrOx시드층을 형성하는 단계; 상기 IrOx시드층 상에 상대적으로 습식식각률이 느린 절연막과 상대적으로 습식식각률이 빠른 절연막을 반복하여 증착한 층간절연막을 형성하는 단계; 상기 층간절연막을 선택적으로 식각하여 IrOx시드층을 개방하는 단계; 상기 층간절연막의 습식식각률 차에 의해 상기 층간절연막의 측벽에 굴곡이 생기도록 습식세정하는 단계; 상기 층간절연막이 식각되어 굴곡이 형성된 영역에 상기 IrOx시드층을 전극으로 하는 ECD법을 이용하여 그 측면에서 굴곡을 가진 캐패시터의 하부전극을 형성하는 단계; 상기 층간절연막을 제거하는 단계; 상기 IrOx시드층을 식각하여 IrOx시드층 패턴을 형성하는 단계; 및 상기 결과물 전면에 유전체막과 캐패시터의 상부전극을 형성하고 패터닝하는 단계를 포함하는 강유전체 메모리 소자의 캐패시터 제조방법을 제공한다.The present invention for achieving the above object, forming an IrO x seed layer on the entire surface of the semiconductor substrate; Forming an interlayer dielectric layer by repeatedly depositing an insulating layer having a relatively low wet etch rate and an insulating layer having a relatively high wet etch rate on the IrO x seed layer; Selectively etching the interlayer insulating film to open an IrO x seed layer; Wet-cleaning the curved sidewalls of the interlayer dielectric layer by a difference in wet etching rates of the interlayer dielectric layers; Forming a lower electrode of a capacitor having a curvature at a side thereof by using an ECD method using the IrO x seed layer as an electrode in an area where the interlayer insulating layer is etched and curved; Removing the interlayer insulating film; Forming the IrO x seed layer pattern by etching the IrO x seed layer; And forming and patterning an upper electrode of the dielectric film and the capacitor on the entire surface of the resultant.
본 발명은 3차원 구조의 강유전체 캐패시터 제조방법에 있어서, 하부전극 스택을 형성하기 위하여 증착하는 제3 층간절연막을 기존의 SiOx막으로 증착하는 것이 아니라, 서로 다른 습식 식각률(etch rate)을 갖는 서로 다른 절연물질을 반복하여 적층한다. 그리고 일반적인 사진식각공정에 의하여 제3 층간절연막을 선택적으로 식각하여 하부전극 형성 부위를 개방한다. 그 다음 BOE(Buffered Oxide Etchant), HF 등의 화학 세정제를 이용하여 세정을 하는데, 이 때 서로 다른 습식식각률로 인하여 개방된 제3 층간절연막의 측벽에 굴곡을 형성시킬 수 있다. 그 다음 단차피복률이 우수한 CVD법, ALD법으로 유전체막 및 상부전극을 형성하고 패터닝하면 캐패시터의 유효면적을 극대화 시킬 수 있다.In the method of manufacturing a ferroelectric capacitor having a three-dimensional structure, the present invention does not deposit a third interlayer insulating film deposited to form a lower electrode stack with a conventional SiO x film, but has a different wet etch rate. Repeat another stack of insulation. The third interlayer insulating layer is selectively etched by a general photolithography process to open the lower electrode forming region. Subsequently, chemical cleaning agents such as BOE (Buffered Oxide Etchant) and HF may be used for cleaning. At this time, bending may be formed on sidewalls of the third interlayer insulating layer opened due to different wet etching rates. The effective area of the capacitor can be maximized by forming and patterning the dielectric film and the upper electrode by the CVD method and the ALD method with excellent step coverage.
상술한 목적, 특징들 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일실시예를 상세히 설명한다.The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 ECD법에 의한 강유전체 캐패시터 형성 공정을 도시한 단면도이다.2A to 2E are sectional views showing a ferroelectric capacitor forming process by the ECD method according to the present invention.
먼저, 도 2a은 본 발명에 따른 도전성 플러그를 형성한 후의 단면도이다.First, Figure 2A is a cross-sectional view after forming the conductive plug according to the present invention.
반도체기판(200) 상의 소정영역에 활성영역(210)과 비활성영역을 한정하는 소자분리막(205)을 형성한다. 그리고 도면에는 도시되어 있지 않지만 모스트랜지스터와 비트라인을 형성하고, 제1 층간절연막(215)을 형성한다. 제1 층간절연막(215)을 관통하여 반도체기판(200)의 활성영역(210)과 연결되는 스토리지 콘택홀(도시하지 않음)을 형성한다. 스토리지 콘택홀 형성 후 화학기상증착법(CVD법)으로 도핑된 폴리실리콘막을 증착한다. 그리고, 폴리실리콘막을 에치백하여 제1 층간절연막(215)의 표면을 노출시켜 폴리실리콘 플러그(220)를 형성한다.An isolation layer 205 defining an active region 210 and an inactive region is formed in a predetermined region on the semiconductor substrate 200. Although not shown in the drawing, a MOS transistor and a bit line are formed, and a first interlayer insulating film 215 is formed. A storage contact hole (not shown) connected to the active region 210 of the semiconductor substrate 200 is formed through the first interlayer insulating layer 215. After the formation of the storage contact holes, the doped polysilicon film is deposited by chemical vapor deposition (CVD). The polysilicon film is etched back to expose the surface of the first interlayer insulating film 215 to form the polysilicon plug 220.
다음으로 전면적으로 Ti, Co, 및 Ni로 구성된 금속물질 중에서 하나를 증착하며, 증착방법으로는 CVD법으로 한다. 증착 후 급속열처리(RTP, Rapid Thermal Processing) 또는 로(Furnace)를 이용한 열처리를 실시한다. 열처리에 의하여 제1층간절연막(215) 상에 있는 금속물질 중의 하나는 실리사이드 반응을 일으키지 않으나, 폴리실리콘 상에 있는 금속물질 중의 하나는 실리콘과 실리사이드화 반응하여 TiSi2, CoSi2또는 NiSi2등의 실리사이드(225)를 형성한다. 열처리가 완료된 반도체기판(200)에 SC-1(Standard Cleaning-1, 암모니아와 과산화수소와 물의 혼합물)으로 세정 공정을 진행함으로써 제1 층간절연막(215) 상에 실리사이드화 반응을 일으키지 않았던 금속물질을 제거한다. 이 실리사이드층은 폴리실리콘과 오믹콘택(Ohmic Contact)을 형성하여 접촉저항을 감소시키기 위함이다.Next, one of the metal materials composed entirely of Ti, Co, and Ni is deposited, and the deposition method is CVD. After deposition, heat treatment is performed using Rapid Thermal Processing (RTP) or Furnace. By heat treatment, one of the metal materials on the first interlayer insulating film 215 does not cause a silicide reaction, but one of the metal materials on the polysilicon is silicided with silicon, such as TiSi 2 , CoSi 2 or NiSi 2 . Silicide 225 is formed. The semiconductor substrate 200 subjected to the heat treatment is cleaned with SC-1 (Standard Cleaning-1, a mixture of ammonia, hydrogen peroxide and water) to remove the metal material that did not cause the silicide reaction on the first interlayer insulating film 215. do. This silicide layer is intended to reduce contact resistance by forming ohmic contacts with polysilicon.
이어서, 반도체기판(200) 전면에 TiN층(230)과 Ir층(235)을 증착하고, 사진식각 공정을 진행하여 플러그 위쪽으로 Ir/TiN층 패턴을 형성하고, 나머지는 제거한다.다음으로 기판 전면에 제2 층간절연막(240)을 증착하고, 제2 층간절연막을 CMP공정으로 Ir층(235) 표면이 나올때까지 평탄화 한다.Subsequently, a TiN layer 230 and an Ir layer 235 are deposited on the entire surface of the semiconductor substrate 200, and a photolithography process is performed to form an Ir / TiN layer pattern on the upper side of the plug, and the rest is removed. The second interlayer insulating film 240 is deposited on the entire surface, and the second interlayer insulating film 240 is planarized until the surface of the Ir layer 235 comes out by a CMP process.
도 2b은 본 발명에 따른 스토리지노드 콘택홀(265)이 형성된 단면도이다.2B is a cross-sectional view of the storage node contact hole 265 according to the present invention.
IrOx시드층(245)과 식각률이 다른 절연막을 반복하여 증착하여 제3 층간절연막(260)을 형성하고, 제3 층간절연막(260)을 선택적 식각하여 하부전극이 형성될 부위를 개방하여 스토리지노드 콘택홀(265)을 형성한다.An insulating layer having an etch rate different from that of the IrO x seed layer 245 is repeatedly deposited to form a third interlayer insulating layer 260, and the third interlayer insulating layer 260 is selectively etched to open a portion where the lower electrode is to be formed, thereby opening the storage node. The contact hole 265 is formed.
IrOx시드층(245)은 하부전극 스택 성장을 위한 전류를 공급하는 시드층의 역할 뿐만 아니라 하부전극의 접착층(Glue layer)과 Pt/Ir 상호 확산 방지막의 역할을 한다. IrOx시드층(245)의 두께는 50Å ∼ 1000Å으로 하며, 증착방법은 PVD법, CVD법, ALD법을 사용한다.The IrO x seed layer 245 not only serves as a seed layer for supplying current for growing the lower electrode stack, but also serves as a Pt / Ir interdiffusion prevention layer of the lower electrode. The thickness of the IrO x seed layer 245 is 50 kPa to 1000 kPa, and the deposition method is PVD, CVD or ALD.
제3 층간절연막(260)은 단일 산화막으로 증착하는 것이 아니라, 서로 다른 습식 식각률을 갖는 서로 다른 절연물질을 반복하여 적층한다. 여기서 상대적으로 습식식각률이 느린 절연막(250)은 USG(Undoped-Silicate Glass), SiON 또는 Si3N4등을 사용하고, 상대적으로 습식식각률이 빠른 절연막(255)은 PSG(Phospho-Silicate Glass), BPSG(Boro-Phospho-Silicate Glass) 등을 사용한다.The third interlayer insulating film 260 is not deposited as a single oxide film, but repeatedly stacked with different insulating materials having different wet etch rates. Here, the insulating film 250 having a relatively slow wet etch rate uses USG (Undoped-Silicate Glass), SiON, or Si 3 N 4 , and the insulating film 255 having a relatively fast wet etch rate is PSG (Phospho-Silicate Glass), BPSG (Boro-Phospho-Silicate Glass) is used.
제3 층간절연막(260)의 증착방법은 PVD법, CVD법, ALD(Atomic Layer Deposition)법, 스핀온(Spin-on)법 등의 방법을 사용하며, 총 두께는 5000Å ∼ 20000Å 범위로 한다. 서로 다른 식각률을 가지는 각각의 절연막의 두께는 1000Å ∼ 3000Å 정도로 한다.As the deposition method of the third interlayer insulating film 260, a method such as PVD method, CVD method, ALD (Atomic Layer Deposition) method, spin-on method or the like is used, and the total thickness is in the range of 5000 kPa to 20000 kPa. The thickness of each insulating film having different etching rates is about 1000 kPa to 3000 kPa.
도 2c는 본 발명에 따른 ECD법으로 하부전극(270)을 성장시킨 단면도이다.2C is a cross-sectional view of growing the lower electrode 270 by the ECD method according to the present invention.
상기 스토리지노드 콘택홀(265)을 개방하고, BOE, HF 등으로 10초 ∼ 10분간 습식 세정을 수행한다. 습식 세정시에는 제3 층간절연막(260)의 반복하여 적층된 각각의 절연막의 습식식각률(Wet etch rate)이 다르기 때문에 절연막 표면에 굴곡이 생기게 된다.The storage node contact hole 265 is opened, and wet cleaning is performed for 10 seconds to 10 minutes with BOE, HF, or the like. During wet cleaning, since the wet etch rate of each of the insulating layers repeatedly stacked on the third interlayer insulating layer 260 is different, bending occurs on the surface of the insulating layer.
다음으로 IrOx층(245)을 시드층으로 하여 하부전극을 ECD 법으로 성장시킨다. 여기에서 하부전극은 Pt, Ir, Ru 중에서 선택된 물질로 형성한다.Next, the bottom electrode is grown by ECD method using the IrO x layer 245 as a seed layer. The lower electrode is formed of a material selected from Pt, Ir, and Ru.
도 2d는 본 발명에 따른 제3 층간절연막(260)을 제거하고, IrOx시드층 패턴(245a) 형성한 단면도이다.2D is a cross-sectional view of the IrO x seed layer pattern 245a formed by removing the third interlayer insulating film 260 according to the present invention.
제3 층간절연막(260)을 습식식각으로 제거하여 백금 하부전극 패턴(270a)를 형성한다. 다음으로 IrOx시드층(245)을 블랑켓 에치백(Blanket etchback)하여 IrOx시드층(245a)을 패터닝한다.The third interlayer insulating layer 260 is removed by wet etching to form the platinum lower electrode pattern 270a. Next, the IrO x seed layer 245 is blanket etched back to pattern the IrO x seed layer 245a.
도 2e는 본 발명에 따른 유전체막(275)과 상부전극 도전층(280)을 증착하고 패터닝 한 단면도이다.2E is a cross-sectional view of depositing and patterning a dielectric film 275 and an upper electrode conductive layer 280 according to the present invention.
유전체막(275)으로는 SBT, SBTN, PZT, ST, BLT 중에서 선택된 유전물질을 사용한다. 증착방법은 단차피복성이 우수한 CVD법, ALD법 등을 사용하며, 두께는 50Å ∼ 2000Å의 범위로 한다. 유전체막(275)을 증착한 후에는 급속열처리 또는 로를 이용한 열처리를 O2, N2, Ar, O3, He, Ne 또는 Kr 등의 분위기에서 실시한다. 열처리 온도는 400℃ ∼ 800℃의 범위에서 실시하며, 열처리 시간은 10분 ∼ 5시간의 범위에서 실시한다.As the dielectric film 275, a dielectric material selected from SBT, SBTN, PZT, ST, and BLT is used. The vapor deposition method uses a CVD method, an ALD method, or the like, which has excellent step coverage, and has a thickness in the range of 50 kPa to 2000 kPa. After the dielectric film 275 is deposited, rapid heat treatment or heat treatment using a furnace is performed in an atmosphere of O 2 , N 2 , Ar, O 3 , He, Ne, or Kr. The heat treatment temperature is performed in the range of 400 ° C to 800 ° C, and the heat treatment time is performed in the range of 10 minutes to 5 hours.
상부전극 도전층(280)은 Pt, Ir, Ru, IrOx, RuOx, W, WNx또는 TiN 중에서 선택된 물질 또는 이들의 조합으로 사용한다. 증착방법은 CVD법, ALD법 등을 사용하며, 두께는 100Å ∼ 2000Å의 범위로 한다.The upper electrode conductive layer 280 is used as a material selected from Pt, Ir, Ru, IrO x , RuO x , W, WN x, or TiN, or a combination thereof. The vapor deposition method uses the CVD method, the ALD method and the like, and the thickness is in the range of 100 kPa to 2000 kPa.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어진 본 발명은, FeRAM의 캐패시터를 ECD법으로 스택 구조의 하부전극을 제조하는 과정에서, 하부전극 스택 표면에 굴곡을 생성시켜, 캐패시터의 유효 표면적을 늘리는 효과가 있다.The present invention made as described above, in the process of manufacturing the lower electrode of the stack structure of the capacitor of the FeRAM by ECD method, there is an effect of increasing the effective surface area of the capacitor by generating a bend on the surface of the lower electrode stack.
또한 스택 구조의 캐패시터를 형성함으로써, 전기적 특성이 우수하고, 단차피복성이 우수한 효과가 있다.In addition, by forming a capacitor having a stack structure, there is an effect excellent in electrical characteristics and excellent step coverage.
Claims (21)
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0936324A (en) * | 1995-07-24 | 1997-02-07 | Sony Corp | Manufacture of semiconductor device |
| JPH09237874A (en) * | 1996-02-29 | 1997-09-09 | Nkk Corp | Semiocnductor device and its manufacture |
| KR19980036488A (en) * | 1996-11-18 | 1998-08-05 | 김광호 | Pin Capacitor Manufacturing Method |
| KR20000001619A (en) * | 1998-06-12 | 2000-01-15 | 윤종용 | Capacitor having a lower electrode of a winding container shape and method of forming the same |
| KR20000010040A (en) * | 1998-07-29 | 2000-02-15 | 클라크 3세 존 엠. | Circuit board having a protecting material of a static electricity discharge |
| KR20000031055A (en) * | 1998-11-03 | 2000-06-05 | 윤종용 | Structure of capacitor for semiconductor device and production method thereof |
-
2001
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0936324A (en) * | 1995-07-24 | 1997-02-07 | Sony Corp | Manufacture of semiconductor device |
| JPH09237874A (en) * | 1996-02-29 | 1997-09-09 | Nkk Corp | Semiocnductor device and its manufacture |
| KR19980036488A (en) * | 1996-11-18 | 1998-08-05 | 김광호 | Pin Capacitor Manufacturing Method |
| KR20000001619A (en) * | 1998-06-12 | 2000-01-15 | 윤종용 | Capacitor having a lower electrode of a winding container shape and method of forming the same |
| KR20000010040A (en) * | 1998-07-29 | 2000-02-15 | 클라크 3세 존 엠. | Circuit board having a protecting material of a static electricity discharge |
| KR20000031055A (en) * | 1998-11-03 | 2000-06-05 | 윤종용 | Structure of capacitor for semiconductor device and production method thereof |
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