KR100403620B1 - Communication system and method for raising coefficient of utilization of channels - Google Patents

Abstract

A communication system and method for increasing channel utilization are disclosed. A communication system according to the present invention for storing data received through a communication channel composed of a plurality of channels in a memory or transmitting packet data stored in the memory through the communication channel, respectively, is to receive or transmit through a communication channel. A plurality of buffer descriptors storing information about the packet data, the packet data is stored in each of the buffer descriptors, and a marker bit is assigned to each of the buffer descriptors, so that the buffer descriptor is configured or received on the communication channel. Check the marker bits of the central processing unit (CPU) and buffer descriptors to indicate whether an error has occurred in the packet data being processed or the configuration of the buffer descriptor is completed, and then stop processing the buffer descriptor that you want to access and access the next buffer descriptor. Or A direct memory access (DMA) controller for processing packet data in which information is stored in a buffer descriptor that is currently accessed, and in a communication system for transmitting / receiving packet data over a plurality of communication channels, one or more Even if an error occurs in the communication channel, the DMA controller can process packet data received on another channel in which the error does not occur, thereby increasing channel utilization.

Description

Communication system and method for raising channel utilization rate {Communication system and method for raising coefficient of utilization of channels}

The present invention relates to a communication system, and more particularly, to a communication system and a method for increasing the utilization of the communication channel in a communication system for transmitting and receiving data through two or more communication channels.

In general, a direct memory access (DMA) controller is called without interference from a central processing unit (CPU) for fast data transmission / reception in a communication system. I use it. That is, the DMA controller stores data received in a packet unit through the communication channels into the memory or transmits data stored in the memory to the communication channels in the packet unit. As such, storing data received in the communication channel in the memory using the DMA controller or transmitting data stored in the memory in the communication channel may be accomplished by the DMA controller accessing a buffer descriptor in the memory. Buffer descriptors preconfigure information about packets that the CPU will send / receive over a communication channel in memory. Here, information about one packet is stored in one buffer descriptor.

The DMA controller has a start buffer descriptor pointer set by the CPU, and processes packet data while accessing consecutive buffer descriptors starting from the buffer descriptor indicated by the start buffer descriptor pointer.

1 is a diagram illustrating an example of a buffer descriptor structure configured by a CPU.

Referring to FIG. 1, one buffer descriptor includes a data pointer (Data Pointer, DP), an owner bit (Ownership bit, O), a command bit (Command, C), a status bit (Status, S), and a next buffer descriptor pointer ( Next Buffer Descriptor Pointer, NBDP).

Here, the data pointer DP indicates an address of a memory in which the packet data received from the communication channel is stored or an address of a memory in which packet data to be transmitted to the communication channel is recorded. The owner bit (O) is a bit indicating whether the buffer descriptor is a CPU mode usable by the CPU or a DMA mode usable by the DMA controller. The command bit C is a bit representing a packet data processing command. The status bit S is a bit that indicates the status and the type of error when an error occurs as a result of packet data transmission / reception. The next buffer descriptor pointer (NDBP) indicates the next buffer descriptor to be accessed by the DMA controller.

Now, a packet data processing method of the DMA controller using the buffer descriptor shown in FIG. 1 will be described.

The DMA controller has a buffer descriptor start pointer set by the CPU as described above, and for convenience of explanation, it is assumed that the buffer descriptor start pointer of the DMA controller indicates the first buffer descriptor. The DMA controller accesses the first buffer descriptor 10 indicated by the start pointer, and the mode of the buffer descriptor 10 indicates whether the first buffer descriptor 10 is the CPU mode or the DMA mode through the owner bit O. Check it.

Here, the buffer descriptor is a CPU mode in which the CPU is configuring a buffer descriptor for data transmission / reception. When the configuration of the buffer descriptor is completed, the CPU sets the owner bit (O) to change the mode of the buffer descriptor to the DMA mode. To convert. The DMA controller checks the owner bit O of the first buffer descriptor 10, and if the owner bit O is set (or reset), the packet data received from the communication channel is stored in the memory indicated by the data pointer DP. After the transfer, the owner bit O is reset to switch the mode of the buffer descriptor to the CPU mode. As such, when the buffer descriptor enters CPU mode, the CPU can construct a buffer descriptor with information about the new packet.

Subsequently, the DMA controller checks the next buffer descriptor pointer (NBDP) and accesses the buffer descriptor indicated by the next buffer descriptor pointer. At this time, if the next buffer descriptor pointer of the first buffer descriptor 10 indicates the address "104h", the DMA controller accesses the buffer descriptor 20 whose start address is "104h" and performs data processing.

If the owner bit O of the first buffer descriptor 10 to be accessed by the DMA controller is not set, that is, in the CPU mode, the DMA controller waits until the buffer descriptor 10 becomes the DMA mode.

2 is a diagram showing another structure of the buffer descriptor implemented by the CPU.

Compared with the structure shown in FIG. 1, it can be seen that there is no next buffer descriptor in the buffer descriptor shown in FIG. 2. The DMA controller for accessing a buffer descriptor as shown in FIG. 2 has a buffer descriptor start pointer indicating a buffer descriptor to be accessed first and a current buffer descriptor pointer indicating a buffer descriptor currently accessed. And, the initial value of the current buffer descriptor pointer has the same value as the buffer descriptor start pointer.

Referring to FIG. 2, assuming that the start pointer of the DMA controller indicates 100h, the DMA controller accesses the first buffer descriptor 20 and first confirms whether the first buffer descriptor 10 is in the CPU mode or the DMA mode. do. When the DMA controller completes the data processing for the first buffer descriptor 20, the DMA controller adds an address corresponding to the size of the buffer descriptor to the value of the current pointer to change the value of the current pointer. Accordingly, the current pointer value of the DMA controller is changed from 100h to 102h, and the DMA controller accesses the second buffer descriptor 22 by the current pointer.

As such, in the case of the buffer descriptor shown in FIG. 2, the DMA controller increases the address by the size of the buffer descriptor to the current pointer so that the pointer to be accessed next can be known. When the processing up to the n-th buffer descriptor 28 is completed sequentially, the current pointer of the DMA controller becomes a start pointer again, and the first buffer descriptor 20 is accessed to access the first buffer descriptor 20 indicated by the start pointer. Do data processing.

As described above, each of the buffer descriptors shown in FIGS. 1 and 2 has an owner bit (O) indicating whether a DMA controller is available. If the DMA controller checks the owner bit (O) and the buffer descriptor currently being accessed is in CPU mode, the DMA controller will not be able to process the packet data to be transmitted / received through the communication channel until the buffer descriptor is in DMA mode. .

In a communication system having two or more channels and receiving packet data, if an error occurs in one packet due to an error in one channel, the CPU resets (or sets) the owner bit of the buffer descriptor. Let's do it. In this way, when the owner bit O of the buffer descriptor is reset (or set) to set the mode of the buffer descriptor to the CPU mode, the DMA controller cannot use the buffer descriptor. Therefore, it is possible to prevent packet data received on an error channel from being transmitted to the memory through the DMA controller. At this time, the DMA controller continues to wait until the buffer descriptor becomes available, that is, until the buffer descriptor is in the DMA mode. As such, packet data to be transmitted or received over other channels that do not fail while the DMA controller is idle is also not processed.

As a result, in a communication system that transmits / receives packet data through two or more communication channels, when an error occurs in one channel and the DMA controller becomes idle, the DMA controller transmits or transmits through another channel in which no error occurs. The problem is that the packet data to be received cannot be processed.

The technical problem to be achieved by the present invention is that the channel utilization rate is high because the DMA controller can process packet data transmitted / received through other channels which do not cause an error even if an error occurs in one or more channels in a multi-channel communication system. The present invention provides a communication system.

Another object of the present invention is to provide a communication method made in the communication system.

1 is a diagram illustrating an example of a buffer descriptor structure configured by a CPU.

2 is a diagram showing another structure of the buffer descriptor implemented by the CPU.

3 is a block diagram schematically illustrating a communication system for increasing the utilization of a channel according to the present invention.

4 is a flowchart according to an embodiment of a communication method performed in the communication system shown in FIG. 3.

FIG. 5 is a diagram showing another embodiment of the DMA controller 64 shown in FIG. For convenience of description, FIG. 5 shows the buffer descriptors 66 and the system bus 68 together.

FIG. 6 is a diagram showing another example of the configuration of the buffer descriptor 66 shown in FIG. 3 and a DMA controller that accesses it.

In order to achieve the above object, the communication system according to the present invention for storing the data received through the communication channel consisting of a plurality of channels in the memory or the packet data stored in the memory through the communication channel, each communication channel Store the packet data in each of the plurality of buffer descriptors and the buffer descriptors that store the information about the packet data to be received or transmitted through the system, and assign a marker bit to each of the buffer descriptors to configure the buffer descriptor. Or stop the processing of the buffer descriptor that you are currently accessing by checking the marker bits of the central processing unit (CPU) and buffer descriptors to indicate whether an error occurred in the packet data received on the communication channel or the configuration of the buffer descriptor is completed. And then buffer disk Accessing the site, or include a DMA (Direct Memory Access) controller that processes paekkit data information is stored in a buffer descriptor to the current access.

In order to achieve the above another task, the CPU configures a buffer descriptor that stores information on packet data to be received or transmitted through a communication channel, and the DMA controller stores packet data received through a plurality of communication channels through the buffer descriptor. A communication method according to the present invention, which is performed in a communication system for storing in a memory or transmitting packet data stored in a memory through a plurality of communication channels, when the CPU constructs a buffer descriptor, indicates the current state of the buffer descriptor using marker bits. In step (a), the DMA controller checks the marker bit to determine whether the buffer descriptor to be processed is being configured by the CPU, an error has occurred in the communication channel, or the configuration of the buffer descriptor is completed. In steps (b) and (b) If the buffer descriptor to be accessed is being configured by the CPU, if it is confirmed that an error has occurred in the communication channel in steps (c) and (b) of continuously checking the marker bit until the configuration of the buffer descriptor is completed, If it is determined in step (d) and step (b) that the currently accessed buffer descriptor is skipped in step (b) to skip the buffer descriptor to be currently accessed and process the next buffer descriptor, the DMA controller When (e) processing the packet data in which the information is stored in the buffer descriptor being accessed and the processing of the packet data is completed, the DMA controller converts the buffer descriptor processed in step (e) into a CPU mode that the CPU can use. Thereafter, step (f) moves to the next buffer descriptor to be processed.

Hereinafter, a communication system having a high channel utilization rate and a method thereof according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram schematically illustrating a communication system for increasing the utilization of a channel according to the present invention. The communication system according to the present invention comprises a CPU 60, a DMA controller 64 and a plurality of buffer descriptors 66. Although not shown, the buffer descriptors 66 occupy a part of the memory where the packet data is stored. 3 shows a system bus 68 together, with data transfer between the CPU 60, the DMA controller 64 and the buffer descriptors 66 via the system bus 68.

Referring to FIG. 3, the buffer descriptors 66 store information about the packet data received or transmitted in packet units through the communication channel 62 by the CPU 60. Each buffer descriptor stores information about one packet data. Each of the buffer descriptors 66 is composed of a data pointer DP, a command bit C and a status bit S, and a marker bit composed of an owner bit O and a skip bit SK.

The CPU 60 configures the buffer descriptors 66 in a partial region of the memory for storing the packet data. Here, the CPU 60 constructs a buffer descriptor means that the CPU 60 stores information about packet data transmitted / received through the communication channel 62. At this time, the CPU 60 assigns a marker bit to each buffer descriptor, and displays the current state of the buffer descriptors 66 using the marker bit. That is, the CPU 60 uses the marker bit to determine whether the buffer descriptor is being configured by the CPU 66, whether an error has occurred in the packet data received through the communication channel 62, or the configuration of the buffer descriptor is completed. Display the status.

The CPU 60 allocates 2 bits as marker bits, one of which is assigned to the owner bit (O) and the other to the skip bit (SK).

The owner bit (O) indicates whether the buffer descriptor is in CPU mode or DMA mode. That is, the CPU 60 buffers the owner bit O by setting (or resetting, hereinafter, assumed to be set) when the buffer descriptor is configured or an error occurs in the packet data received through the communication channel 62. Indicates that the descriptor is currently in CPU mode. As such, if the buffer descriptor is in CPU mode, the DMA controller 64 cannot use the buffer descriptor. Further, when the configuration of the buffer descriptor is completed, the CPU 60 resets the owner bit O (or assumes to be three, or less, reset) to indicate that the buffer descriptor is a DMA mode available by the DMA controller 64. .

The skip bit SK indicates whether the CPU 60 is constructing a buffer descriptor or if an error has occurred in the packet data received on the communication channel 62. That is, the CPU 60 resets the skip bit SK (or assumes to be three or less resets) when configuring the buffer descriptor. On the other hand, when an error occurs in the communication channel 62 and an error occurs in the packet received through the communication channel 62, the CPU 60 assumes that the skip bit SK is set (or reset, hereinafter, reset). )do.

The DMA controller 64 has a start pointer and a current pointer of the buffer descriptor. The start pointer 64a is set by the CPU 60 and indicates the buffer descriptor that the DMA controller 64 accesses for the first time. The current pointer 64b indicates the buffer descriptor that the DMA controller 64 is currently accessing, and initially has the same value as the start pointer. The current pointer 64b obtains the value by increasing the address corresponding to the size of the unit buffer descriptor to the pointer value of the previously processed buffer descriptor. Thus, the value of the current pointer 64b of the DMA controller 64 initially indicates the first buffer descriptor 70 equal to the value of the start pointer 64a, and in turn, the second, third, ..., The nth buffer descriptors 72, 74, ..., 78 are indicated. The DMA controller 64 processes the first, second, third, ..., n-th buffer descriptors 70, 72, 74, ..., 78 sequentially according to the current pointer 64b.

The DMA controller 64 checks the marker bit of each of the buffer descriptors 66 to stop processing the buffer descriptor that is currently being accessed and to access the next buffer descriptor or to use the information stored in the buffer descriptor that is currently being accessed. Packet data to be transmitted / received through the communication channel 62. Here, the packet data processing is to transmit the packet data received from the communication channel 62 through the buffer descriptor to the memory or the packet data stored in the memory to the communication channel 62.

4 is a flowchart according to an embodiment of a communication method performed in the communication system shown in FIG. 3.

Now, a communication method according to the present invention performed in the system shown in FIG. 3 will be described with reference to FIGS. 3 to 4.

3 and 4, the CPU 60 stores information on the packet data transmitted / received on the communication channel 62 composed of n channels in the buffer descriptors 66 (step 98). At this time, information about one packet data is stored in one buffer descriptor, and the CPU 60 allocates two bits of marker bits indicating the status of the buffer descriptor to each buffer descriptor. The CPU 60 uses the marker bit to store information about the packet data in the buffer descriptor, has an error occurred in the communication channel 62 that has received the currently stored packet data, or does not store the information about the packet data. Indicates that it is complete.

After step 98, the DMA controller 64 accesses the buffer descriptor indicated by the current pointer 64b (step 100). For convenience of explanation, it is assumed that the current pointer 64b points to the i-th buffer descriptor 76.

The DMA controller 64 checks the marking bit of the i-th buffer descriptor 76 to be accessed to confirm the current state of the i-th buffer descriptor 76 currently being accessed (step 175). That is, the DMA controller 64 checks the marker bit, and is the information on the packet data being stored in the ith buffer descriptor 76, has an error occurred in the communication channel for transmitting / receiving the packet data, or the packet data? Check whether the information storage is completed.

Specifically, the DMA controller 64 checks the owner bit O of the marker bit to determine whether the mode of the i-buffer descriptor 76 currently being accessed is the CPU mode or the DMA mode in which information storage for the packet data is completed. Determination (step 110). For example, if the owner bit O is set, the DMA controller 64 determines that the i-th buffer descriptor 76 is in the CPU mode, and if it is reset, determines that the DMA mode is in the DMA mode.

In operation 110, when it is determined that the i-th buffer descriptor 76 is in the CPU mode, the skip bit SK is checked and information about the packet data received through the communication channel 62 is stored in the i-buffer descriptor 76. It is checked whether or not an error has occurred in the communication channel 62 that receives the packet data (step 150). For example, if the skip bit SK is set, the DMA controller 64 determines that an error has occurred in the communication channel 62. If the DMA controller 64 is reset, the information on the packet data received in the communication channel 62 is i. It is determined that the buffer descriptor 76 is being stored.

Subsequently, when it is confirmed in step 175 that the i-buffer descriptor 76 accessed by the DMA controller 64 is in the DMA mode, the packet data in which the information is stored in the i-buffer descriptor 76 is processed. Step 120). Here, processing the packet data means that the DMA controller 64 stores the packet data at the address of the memory indicated by the data pointer DP of the i-th buffer descriptor 76 or the memory indicated by the data pointer DP. Packet data stored at an address of P is transmitted to the communication channel 62.

When the processing of the packet data in which the information is stored in the ith buffer descriptor 76 is completed, the DMA controller 64 converts the mode of the ith buffer descriptor 76 into the CPU mode, and accesses the buffer descriptor to be processed next. (Step 130). That is, when the processing of the packet data in which the information is stored in the i-th buffer descriptor 76 is completed, the DMA controller 64 sets the owner bit O of the marker bit to change the mode of the i-th buffer descriptor 76 to CPU. Switch to mode. As such, when the owner bit O is set, the CPU 60 stores information on new packet data in the ith buffer descriptor 76. Further, when the processing of the packet data in which the information is stored in the i-th buffer descriptor 76 is completed, the current pointer 64b of the DMA controller 64 indicates the (i + 1) th buffer descriptor. DMA controller 64 accesses the (i + 1) th buffer descriptor with reference to current pointer 64b.

On the other hand, if it is determined in step 175 that the CPU 60 is storing information on the packet data to be transmitted / received in one of the communication channels 62 in the i-buffer descriptor 76, the DMA controller 64 The storage waits for the packet data information to be completed in the buffer descriptor (step 160).

On the other hand, if it is determined in step 175 that an error has occurred in the packet data currently storing the information, the DMA controller 64 stops processing of the i-buffer descriptor 76 that is currently being accessed and the next buffer descriptor, i (i). +1) Access the buffer descriptor (step 170). That is, the DMA controller 64 checks the skip bit SK, and if an error occurs in the communication channel 62 that transmits / receives the packet data to be processed currently, the DMA controller 64 stops processing the buffer descriptor currently being accessed. Then, the packet data is processed by accessing another buffer descriptor that stores information on packet data transmitted / received on the communication channel where no error occurred.

As described above, in the communication system according to the present invention, the CPU 60 allocates a skip bit SK indicating whether an error occurs in the communication channel when configuring the buffer descriptor. The DMA controller 64 can confirm whether an error has occurred in a communication channel for transmitting / receiving packet data to be processed through this skip bit SK. That is, if an error occurs in the communication channel for transmitting / receiving the packet data to be processed, the DMA controller 64 first processes the packet data to be transmitted / received through another communication channel in which the error has not occurred. It can effectively increase the utilization rate of.

FIG. 5 is a diagram showing another embodiment of the DMA controller 64 shown in FIG. For convenience of description, FIG. 5 shows the buffer descriptors 66 and the system bus 68 together.

The DMA controller 200 has a start pointer 200a and an address counter 200b. The start pointer 200a is set by the CPU 60 and indicates the buffer descriptor that the DMA controller 64 accesses for the first time. The address counter 200b counts the start address of the buffer descriptor that the DMA controller 200 is currently accessing, and is initialized to the value indicated by the start pointer 200a. That is, the address counter 200b adds the address corresponding to the size of the unit buffer descriptor to the start address of the previously processed buffer descriptor to obtain the start address of the next buffer descriptor to be accessed.

Specifically, the DMA controller 200 first accesses the first buffer descriptor 80 indicated by the start pointer 200a. For example, if the start pointer 200a indicates 100h, the DMA controller 200 accesses the address 100h to process packet data. When the processing of the packet data for the first buffer descriptor 80 is completed, the address counter 200b adds an address (for example, 004h) corresponding to the size of the unit buffer descriptor to the current counter value, and the next buffer descriptor to be accessed. Start address 104h is counted. The DMA controller 200 accesses the second buffer descriptor 82 with reference to the address counter 200b.

As such, when the DMA controller 200 obtains the start address of the buffer descriptor to be accessed next by using the address counter 200b, the pointer processing that the DMA controller 200 needs to manage in software is one start pointer. Programming can be simplified.

Since the DMA controller 200 processes the packet data using the buffer descriptors 66 is the same as that described with reference to FIG. 4, the detailed description thereof is omitted here.

FIG. 6 is a diagram showing another example of the configuration of the buffer descriptor 66 shown in FIG. 3 and a DMA controller that accesses it.

3 and 6, one buffer descriptor includes a data pointer DP, a command bit C, a status bit S, a next buffer descriptor pointer NBDP, an owner bit O, and a skip bit It consists of a marker bit consisting of SK). Here, the next buffer descriptor pointer NBDP indicates the next buffer descriptor to be accessed by the DMA controller 64. That is, since each buffer descriptor is provided with a next buffer descriptor pointer, the DMA controller 300 only needs a start pointer 300a indicating the buffer descriptor to be first accessed, which is set by the CPU 60.

Since the DMA controller 200 processes the packet data using the buffer descriptors 66 is the same as that described with reference to FIG. 4, the detailed description thereof is omitted here.

Table 1 below shows the probability of continuous frame reception in a communication channel having an error probability of 5% and 10%, respectively.

Number of consecutive frames Reception probability of communication channel with 5% error probability Reception probability of communication channel with 10% error probability 10 60% 35% 20 36% 12.3% 50 8% 0.5% 100 0.64% 0.003%

Referring to Table 1, when the probability of error in the communication channel is 5% or 10%, as the number of frames that can be continuously received increases, the probability of normally receiving the continuous frames becomes very small. This indicates that the probability of error occurring in packet data received over a communication channel is as high.

Table 2 below shows channel utilization rates according to the prior art and the present invention when 10 frames are continuously received and each communication channel has a 5% error probability.

Number of channels Channel utilization (conventional) Channel utilization (invention) 2 36% 84% 3 22% 93% 5 8% 99% 10 0.64% 100%

Referring to Table 2, even when a number of channels is conventionally used, if an error occurs in one channel, all of the other channels in which the error does not occur due to the error channel cannot be used. Therefore, as the number of channels increases, the channel utilization drops sharply. However, in the present invention, even if an error occurs in one or more communication channels, it is possible to process packet data received through another channel that does not generate an error, thereby increasing channel utilization as the number of channels increases.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the communication system and method for increasing the channel utilization rate according to the present invention, in a communication system for transmitting / receiving packet data through a plurality of communication channels, even if an error occurs in one or more communication channels, the DMA The controller can process the packet data received on another channel where no error has occurred, thereby increasing channel utilization.

Claims (11)

A communication system for storing data received through a communication channel consisting of a plurality of channels in a memory or transmitting packet data stored in a memory through the communication channel, Each comprising: a plurality of buffer descriptors storing information about packet data to be received or transmitted via the communication channel; Store information about the packet data in each of the buffer descriptors, and assign a marker bit to each of the buffer descriptors to configure the buffer descriptor, or whether an error occurs in the packet data received through the communication channel. A central processing unit (CPU) indicating whether the configuration of the buffer descriptor is completed; And Direct Memory Access (DMA) control controller that checks the marker bit of the buffer descriptor and stops processing of the buffer descriptor to be accessed currently, accesses the next buffer descriptor, or processes packet data whose information is stored in the buffer descriptor that is currently accessed. Communication system comprising a. The method of claim 1, wherein the marker bit is DMA that is available to the DMA controller when the CPU is configuring the buffer descriptor or an error occurs in the packet data received on the communication channel, and the buffer descriptor is in CPU mode and the configuration of the buffer descriptor is completed by the CPU. Owner bit indicating mode; And And a skip bit indicating whether the CPU is configuring the buffer descriptor or whether an error has occurred in the packet data received on the communication channel. The method of claim 1, And the CPU allocates a next buffer descriptor pointer to the buffer descriptor, and the DMA controller identifies a next buffer descriptor pointer configured in the buffer descriptor and accesses a buffer descriptor to be processed next. The method of claim 1, When the processing of the currently accessed buffer descriptor is completed, the DMA controller updates the current pointer value by adding an address corresponding to the size of the buffer descriptor to the value of the current pointer indicating the currently accessed buffer descriptor. Communication system. The method of claim 1, wherein the DMA controller is A start pointer indicating a buffer descriptor to first access; And An address counter initialized to a value of the start pointer and counting a start address of the buffer descriptor, And the address counter adds an address corresponding to the size of the unit buffer descriptor to a value of the current address counter to update the value of the current address counter. The CPU configures a buffer descriptor that stores information about packet data to be received or transmitted through a communication channel, and the DMA controller stores the packet data received through a plurality of communication channels through the buffer descriptor in a memory or memory. A communication method in a communication system for transmitting packet data stored in a plurality of communication channels, (a) when the CPU configures the buffer descriptor, displaying a current state of the buffer descriptor by using a marker bit; (b) The DMA controller checks the marker bit to determine whether the buffer descriptor to be processed is currently being configured by the CPU or if an error has occurred in the communication channel or the configuration of the buffer descriptor is completed so that the DMA controller can be used. Checking whether it is in DMA mode; (c) if the buffer descriptor to be accessed currently in step (b) is being configured by the CPU, continuously checking the marker bit until the configuration of the buffer descriptor is completed; (d) if it is determined in step (b) that an error occurs in the communication channel, skipping the buffer descriptor to be accessed and proceeding to step (b) to process the next buffer descriptor; (e) if it is determined in step (b) that the buffer descriptor currently being accessed is the DMA mode, the DMA controller processes packet data in which information is stored in the buffer descriptor being accessed; And (f) when the processing of the packet data is completed, the DMA controller converts the buffer descriptor processed in step (e) into a CPU mode available to the CPU, and then moves to the next buffer descriptor to be processed. A communication method characterized by the above. The method of claim 6, wherein the marker bit is An owner indicating that the buffer descriptor is in the CPU mode when the CPU is configuring the buffer descriptor or an error occurs in the packet data received through the communication channel, and the DMA mode when the configuration of the buffer descriptor is completed by the CPU. beat; And And a skip bit indicating whether the CPU is configuring the buffer descriptor or whether an error has occurred in the packet data received on the communication channel. The method of claim 7, wherein step (b) (b1) checking, by the DMA controller, whether the mode of the buffer descriptor to be processed currently is the CPU mode or the DMA mode through the owner bit; (b2) If the mode of the buffer descriptor to be processed in step (b1) is determined to be the DMA mode, the process proceeds to step (e). If the mode of the buffer descriptor to be processed is determined to be the CPU mode, the skip bit is skipped. Confirming; And (b3) checking the skip bit, if it is confirmed that an error occurs in the communication channel, proceeds to the step (d); if it is determined that the configuration is performed by the CPU, the process proceeds to the step (c) Communication method. The method of claim 6, And the CPU allocates a next buffer descriptor pointer to the buffer descriptor, and the DMA controller identifies a next buffer descriptor pointer configured in the buffer descriptor and accesses a buffer descriptor to be processed next. The method of claim 6, When the processing of the currently accessed buffer descriptor is completed, the DMA controller updates the current pointer value by adding an address corresponding to the size of the buffer descriptor to the value of the current pointer indicating the currently accessed buffer descriptor. Communication system. The method of claim 1, wherein the DMA controller is A start pointer indicating a buffer descriptor to first access; And An address counter initialized to a value of the start pointer and counting a start address of the buffer descriptor, And the address counter adds an address corresponding to the size of the unit buffer descriptor to a value of the current address counter to update the value of the current address counter.