KR100393106B1 - Acquisition device and method for early synchronization in receiver of code devision multiple access system - Google Patents

Abstract

The present invention provides fast and accurate initial synchronization in a code division multiple access system. In the receiver of the code division multiple access system according to the present invention, an initial synchronization acquisition method includes changing a received code into a digital signal of a predetermined sample. Then decimating the converted value at a constant ratio; Phase shifting the phases of the decimated spreading code by half-chip phase shifting by using a plurality of matched filters so as to generate a phase difference of one chip from each other; Comparing the output value of each matched filter with a predetermined threshold value; Selecting a larger value from a value greater than a threshold as a result of the comparison and performing a verification procedure on the selected value; A phase difference detecting step of detecting a difference between a locally generated code phase and an input code phase after the checking procedure; And a phase difference correction step of changing a generation phase of the local generation code by a phase difference with the input reception signal according to a difference value between the detected phase of the input code and the local generation code.

According to the present invention, a mobile station receiver of a code division multiple access system can simultaneously perform phase acquisition and tracking of a received signal using a plurality of matching filters, thereby reducing initial synchronization time through fast tracking of chip speed. A mobile station receiver is provided.

Description

Acquisition device and method in receiver of code division multiple access system {ACQUISITION DEVICE AND METHOD FOR EARLY SYNCHRONIZATION IN RECEIVER OF CODE DEVISION MULTIPLE ACCESS SYSTEM}

The present invention relates to an initial synchronization acquisition device in a CDMA system, and to configure a phase acquisition and tracking device using a plurality of matching filters to reduce the initial synchronization time in a mobile station receiver through fast tracking of chip speed. An apparatus and method for initial synchronization acquisition in a receiver.

In general, code division multiple access (CDMA) is designed to enable multiple calls over all channels of cellular frequency based on broadband frequency spreading technology. The CDMA method allocates a pseudo random sequence to each user while several users share frequency and time, and each user spreads and transmits a transmission signal, and the receiver uses the same PN sequence as that used by the transmitter. This method is used to synchronize the signal and despread the received signal to restore the signal.

1 illustrates a synchronization channel signal format of a wireless data communication (3GPP) system. As shown therein, one superframe consists of 72 radio frames (10 ms), each radio frame consists of 15 total time slots (0.625 ms), and one time slot totals It consists of ten symbol sections. The symbol rates of the primary and secondary synchronization channels are defined as 15ksps, and these symbols are spread as spread codes having a chip rate of 3.84 Mcps. Therefore, one symbol of the synchronization channel is spread with 256 synchronization codes.

In the first synchronization channel (PSC), the first symbol interval of each time slot is a first synchronization code (Cpsc: Primary Synchronization) common to all cells for speeding up cell selection when powering up the mobile station. Code is spread and transmitted. The second synchronization channel (SSC) is a long scrambling code used in the current base station for the same symbol period as the first synchronization channel over a total of 15 time slots (one radio frame period). An identification code is sent. In this case, the transmitted identification code is expressed as a group identification code (GIC), and a total of 64 group identification codes are used.

2 shows the phase relationship between the transmission timing of the first and second synchronization channels and the scrambling code. As shown in the figure, the scrambling code repeats the phase (38400 chips) up to 10 ms with the starting point of each frame as phase 0. That is, the scrambling code has a period of one wireless frame, and the start point of the second synchronization code in the first time slot period of the group identification code always coincides with the scrambling code phase 0.

The initial synchronization in the code division multiple access system is divided into three stages. The first stage is to find the existence of the first synchronization code, and the second stage is to determine the group identification code and the frame synchronization. The third step is to find out the scrambling code currently used by the base station using the group identification code and the frame information found in the two-step synchronization procedure.

Among these initial synchronization procedures, the first phase, that is, the first synchronization code interval detection procedure using a matched filter, is the most important factor in the overall synchronization performance. If the wrong code interval is detected in step 1, the correct operation cannot be performed in steps 2 and 3. This initial synchronization is a very important factor that determines the overall performance not only in the asynchronous system but also in the synchronous method.

3 is a diagram illustrating an initial synchronization circuit using a conventional matching filter. Referring to FIG. 3, a first PN sequence having a length (L / n) obtained by dividing one period (L) of a received pseudonoise (PN) sequence by an arbitrary partial correlation interval (n) and the first PN sequence A matching filter 20 for performing a logical operation on the second PN sequence generated by the local generator equal to the length until one period L of the PN sequence, and for each result of the logical operation of the matching filter 20. RAM (RAM) 50 whose value is temporarily stored every L / n time under the control of the processor 40, and comparing and controlling each result value stored in the RAM 50 with a predetermined threshold value stored in itself. The sum of the ROMs (ROM) 50 stored in the program and the respective result values stored in the ROM 50 is obtained, and the sum of the initial values is compared according to the threshold values stored in the ROM 60. It consists of a processor 40 to obtain.

Here, the matching filter 20 is a local generator to match the order of the input data shift register 21 for receiving the first PN sequence and the first PN sequence input to the input data shift register 21. A shift register 22 for input data into which a second PN sequence generated according to a clock adjusted in step 1 is input, and a shift register 22 for receiving and a first PN sequence input to the shift register 21 for input data; It consists of a logical operation unit 25 for performing a logical operation to determine whether the second PN sequence generated in the same.

The logic operation unit 25 logically inverts a result of the exclusive OR of each of the correlators 25a including exclusive OR gates for exclusive OR of the first PN sequence and the second PN sequence, and the plurality of correlators 25a. It is determined whether the first PN sequence and the second PN sequence constituted by the inverter 25b are the same.

In order to obtain the initial synchronization time in the receiving unit of the conventional code division multiple access system configured as described above,

The received PN sequence is a random sequence of 0's and 1's, and is repeatedly transmitted with a long period (L), and the combination of 0's and 1's in this period L is determined by the circuitry that produces the particular PN sequence. The received PN sequence is input to the shift register 21 for input data.

At this time, if one period (L) of the PN sequence is 100 bits, the partial correlation interval (n; arbitrary variable function) determined by design among the 100 bits may be set to 10 in the shift register 21 for input data. In this case, a first PN sequence corresponding to a length of L / n = 100/10 is input.

In addition, a second PN sequence is also input to the receiving shift register 22 in order to match the length (number of bits) of the first PN sequence inputted to the input data shift register 21 as well.

The second PN sequence here is preset to match the received first PN sequence, but as described above, the second PN sequence may be out of order and thus may not acquire initial synchronization.

Therefore, in order to achieve this order, the clock of the receiver must be adjusted to move the second PN sequence to the left or the right.

On the other hand, as described above, the shift register 21 for input data is received by dividing by L / n, which is divided by L / n until the time corresponding to one period (L = 100) of the PN sequence is received.

Accordingly, if the first PN sequence input to the shift register 21 for input data is 0001101011 and the second PN sequence input to the reception shift register 22 is 110001101011..., The second PN sequence The two bits do not match from the beginning of. Then, when the left side is moved twice by clock adjustment of the receiver, the order of the first PN sequence and the second PN sequence is correct.

In this case, the logically calculated value is '10' because the logical OR of the plurality of correlators 25a and the inverter 25b are inverted by 1 and equal by 0 due to the inversion of the inverter 25b. This logically calculated value 10 is stored in the RAM 50 via the data bus 30.

Similarly, this operation is repeatedly performed by dividing the PN sequence by L / n corresponding to one period (or length) (L = 100). Correspondingly, the total sum of the values stored in the RAM 50 every L / n time is obtained by the processor 40.

In addition, processor 40 compares the obtained sum value with a threshold value stored in ROM 60 to be equal to or greater than. By this comparison, the processor 40 determines that the initial synchronization is obtained when the total sum value is greater than or equal to the predetermined threshold value.

On the other hand, the processor 40 determines that the initial synchronization is not obtained when the total value is smaller than the predetermined threshold value. In this case, the above operation is repeated until the initial synchronization is obtained.

In such general digital communications, especially spread-band communications, chip synchronization is largely divided into acquisition and tracking. Acquisition means that the phase error between the code phase of the input received signal and the local generation signal falls within ± 0.5 chip. Tracking is an auxiliary circuit that is driven after the acquisition is completed, which reduces the phase error more precisely. That is, the main purpose of the tracking circuit is to make the phase error equal to zero.

Currently used tracking circuits for spread spectrum signals include DLL (Delayed Lock Loop) and TDL (Tau Dither Loop) which induces and outputs a correlation value for a certain chip period. This is known to be advantageous. Therefore, the use of a DLL circuit should be considered for accurate one-step synchronization in the asynchronous method. However, as shown in FIG. 2, a short code is transmitted only in the first symbol period of each time slot as shown in FIG. DLLs that use a correlator make it difficult to track faster.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The present invention uses a plurality of matching filters to capture a received spread code and to change the phase of the local generator by an error between the phase of the input received code and the phase of the local generator. By using the matching filter to track the phase of the input signal, the matching filter is commonly used in the acquisition and tracking circuit to enable the mobile station receiver to quickly and quickly acquire and track the spreading code. An object of the present invention is to provide an initial synchronization acquisition device and method in a receiver of a division multiple access system.

1 is a block diagram showing a synchronization channel signal format in a code division multiple access system.

2 is a diagram illustrating a phase relationship between a synchronization channel and a scrambling code in a code division multiple access system.

3 is a block diagram of an initial synchronization acquisition circuit using a matched filter in a receiver of a conventional code division multiple access system.

4 is a block diagram illustrating an initial synchronization acquisition apparatus in a receiver of a code division multiple access system according to an embodiment of the present invention.

5 is a flowchart illustrating an initial synchronization acquisition method in a receiver of a code division multiple access system according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 Analog-to-digital converter 120 ...

130 Acquisition means 140 Tracking means

131 ... local generator 134 ... comparator

135,136 ... switch 141,142 ... band pass filter

143,144 ... power 145 ... subtractor

146 ... loop filter 147 ... voltage controlled oscillator

In order to achieve the above object, the initial synchronization acquisition device using a matched filter according to the present invention,

Analog / digital conversion means for converting the received code into a digital signal of a predetermined sample; Decimation means for decimating the digitally converted signal to a predetermined ratio; Phase shift the phase of the decimated code with a plurality of matched filters so as to have a phase difference of about one chip from the reference phase of the local code, and compare the phase of the phase shifted received code with a predetermined threshold. Capturing means for selecting an output larger than the value; Tracking is obtained based on an arbitrary phase of each code shifted about one chip input from the capturing means, and the local code phase is changed based on the value of the difference so that the capturing means can track it. It comprises a means.

Specifically, the capturing means includes a local generator for generating an arbitrary reference phase, a first matched filter for phase shifting the decimated received code phase half a chip faster than the arbitrary reference phase and loading it into a memory; A second matching filter for shifting the phase of the decimated received code half a chip later than the predetermined reference phase and loading it into a memory; and each output value phase shifted by the first and second matching filters with a predetermined threshold value. And a comparator for comparing and selecting one value greater than the threshold value.

In detail, the tracking means calculates a square of the output values of the first and second bandpass filters and the first and second bandpass filters for bandpass filtering the respective output values of the first matched filter and the second matched filter. An adder for calculating a difference by adding first and second squares, output values of the first and second squares, and a voltage-controlled oscillator driven according to the difference between the adders to generate any And a loop filter for changing the reference phase.

In the receiver of the code division multiple access system according to an embodiment of the present invention, an initial synchronization obtaining method includes: changing a received code into a digital signal of a predetermined sample and then decimating the converted value at a predetermined ratio;

Phase shifting the phases of the decimated spreading code by half-chip phase shifting by using a plurality of matched filters so as to generate a phase difference of one chip from each other;

Comparing the output value of each matched filter with a predetermined threshold value;

Selecting a larger value from a value greater than a threshold as a result of the comparison and performing a verification procedure on the selected value;

A phase difference detecting step of detecting a difference between a locally generated code phase and an input code phase after the checking procedure;

And a phase difference correction step of changing a generation phase of the local generation code by a phase difference from the input reception signal according to a difference value between the detected phase of the input code and the local generation code.

Hereinafter, with reference to the accompanying drawings as follows.

4 is a block diagram illustrating an initial synchronization acquisition apparatus in a receiver of a code division multiple access system according to the present invention, and FIG. 5 is a flowchart illustrating an initial synchronization acquisition method in a receiver of a code division multiple access system according to the present invention.

Referring to FIG. 4, an analog / digital converter (ADC) 110 for digitally converting a received spread code to 8 samples per chip, and a decimation unit for decimating the digitally converted spread code at 8: 1. 120, capture means 130 for matching filtering the decimated spread code by ± 0.5 chip phase shift based on a locally generated phase signal, and selecting a larger value from the phase shifted value; And a tracking means 140 for changing the locally generated phase by a phase difference between the locally generated phase and the received code according to the output value phase shifted from 130.

Here, the acquisition means 130 receives a local generator 131 for generating a local generation signal having an arbitrary phase, and receives a phase of the local generation signal. (+0.5 chip) The first matching filter (Early MF) 132, which is loaded into a memory (not shown) while matching filtering and shifting, receives the phase of the local generation signal and is half the phase of the received code slower than this phase. A threshold value determined by shifting the output values of the second matched filter (Late MF) 133 and the output values of the first and second matched filters 132 and 133 that are loaded into a memory (not shown) while matching filtering and shifting (-0.5 chip). To a comparator 134 for outputting a large value in comparison with the first and second switches 135 and 136 for selectively outputting the output values of the first and second matching filters 132 and 133 according to the output of the comparator 134. It is composed.

The tracking means 140 may include first and second band pass filters (BPF) 141 and 142 for band pass filtering the values output from the first and second matched filters 132 and 133, and the band pass filtered diffusion code. An adder 145 which adds to obtain a difference value between the first and second squarers 143 and 144 and the output value of the first square 143 from the output values of the second square 144 and the adder ( A loop filter 146 driven according to the output of the power supply 145 and a voltage controlled oscillator (VCO) driven according to the output value of the loop filter 146 to change the local generation phase of the local code generator 131. 147).

The apparatus and method for initial synchronization acquisition in a receiver of a code division multiple access system according to an embodiment of the present invention configured as described above will be described with reference to FIGS. 5 and 6.

First, the PN sequence received by the mobile station receiver is digitally converted into 8 samples by the analog-to-digital converter 110 (S201 and S202), and the digitally converted signal is 8 by the decimation unit (Decimation) 120. The decimation process is performed at 1: 1 (S203).

After receiving the decimated spread code as described above, acquisition and tracking operations are performed for chip synchronization. The acquisition is such that the code phase of the input reception signal and the phase of the locally generated code fall within ± 0.5 chip. Is an auxiliary circuit that is driven after the acquisition is complete to reduce more precise errors. In other words, the purpose is to make the phase error equal to zero.

To this end, the capture unit 130 receives the decimated signal from the matched filters 302 and 303, phase shifts one chip, and performs matched filtering, and outputs a value larger than a threshold value among these values. The local generator 131, the first and second matching filters 132 and 133, the comparator 134, and the first and second switches 135 and 136 may be provided.

Then, the local code generator 131 generates a local generation signal (PN code) having an arbitrary reference phase, outputs it to the first and second matching filters 132 and 133, and the first matching filter (Early MF) 132. In step S204, the decimated phase of the received input code is matched by a half-chip fast filter (+0.5 chip) and shifted into a memory (not shown) while shifting the phase of the received input code. The second matched filter (Late MF) 133 places the decimated received input code into a memory (not shown) by half-chip slow filtering (-0.5 chip) and shifts the phase of the received input code decimated than the reference phase of the local generation signal. (S204). Therefore, the two matched filters 132 and 133 have a phase difference of one chip. At this time, the diffusion code is loaded in the memory of each matching filter 132 and 133 at the same speed as the input signal.

At this time, the mobile station receiver continuously receives the received signal through a shift register (not shown) as the capture of the input reception code phase and compares the output value of the first matched filter 132 and the output value of the second matched filter 133 with each other. It is compared with the threshold determined in (S205). That is, the received and inputted spread code phases are compared with the code phases stored in the memories of the matched filters 132 and 133 and output.

When the output value of the first matching filter 132 exceeds the threshold as a result of the comparison of the comparator 134, the mobile station receiver enters the tracking step through the confirmation procedure (S206) (S209). Similarly, if the output value of the second matching filter 133 exceeds the threshold value, the mobile station receiver enters the tracking step through the confirmation procedure after selecting it (S207) (S209). If the output values of the two matching filters 132 and 133 both exceed the threshold value, the larger one of the two output values is selected and the verification procedure is entered (S208) (S209).

In addition, in a section without a sync code such as an asynchronous method, a chip counter (not shown) is temporarily used to temporarily stop the operation of the tracking circuit to the next sync code section to prevent a malfunction of the tracking means 140. .

The confirmation procedure (S209) is performed because the threshold value may be exceeded even when the phase of the currently received code phase and the code of the matched filter memory are out of phase due to noise added to the channel transmission or fading or signal processing error. It is a process. If the output values of the first and second matched filters 132 and 133 do not exceed the thresholds, the received signals are continuously received through the shift registers of the matched filters 132 and 133, and then output.

When the output values of the first matched filter and the second matched filter 132 and 133 are input to the tracking means 140 through the first and second switches 134 and 135 to compensate for an error with the local generation signal, the system The tracking means 140 is driven by the control logic (S210). In the tracking step, the chip speed can be tracked by changing the local code phase by half chip based on the code phase of the selected first matched filter 132 or the second matched filter 133. That is, the existing DLL derives and outputs a correlation value for a predetermined chip period, but the present invention uses a matched filter, so that the output of the chip speed can be output, thereby enabling faster and more accurate tracking.

To this end, the tracking means 140 includes first and second band pass filters (BPF) 141 and 142, first and second squarers 143 and 144, an adder 145, a loop filter 146, and a voltage. Control oscillator (VCO) 147, and the first and second band pass filters 141 and 142 output the first and second matching filters 131 and 132 by band pass filtering, respectively, and the first and second characters. The multipliers 143 and 144 square the outputs of the bandpass filtered values.

The adder 145 subtracts the output value of the first multiplier 143 from the output value of the second multiplier 144 and inputs the subtracted value to the loop filter 146 (S211). The subtracted value is generated by the difference between the code phase of the input reception signal and the locally generated code phase.

Here, when the output value of the subtractor 145 is negative, the phase of the local generation code is slower than the phase of the input reception code. If the output value of the subtractor 145 is positive, the phase of the local generation code is the input reception code. If the phase is faster than, and if the output value is zero, there is no phase difference.

Then, when the difference between the code phase of the input signal and the code phase of the local code generator 131 is a negative value (S212), the loop filter 146 is driven as the value, and accordingly the loop filter ( 146 drives the voltage controlled oscillator 147 to advance the generation time of the local code generator 131 by its output value (S216).

When the difference between the code phase of the input signal and the code phase of the local code generator 131 is a positive value (S213), the loop filter 146 is driven as the value, and accordingly the loop filter ( 146 drives the voltage controlled oscillator 147 to delay the generation time of the local code generator 131 by its output value (S217).

In addition, when there is no difference between the code phase of the input signal and the code phase of the local code generator 131 (S215), the loop filter 146 is driven as a value (0), and the loop filter 146 according to this value. The voltage-controlled oscillator 147 drives the local code generator 131 to maintain the current local code generation phase at the time of occurrence of the local code generator 131 (S218).

The phase detection characteristic of the tracking means 140 is called a time error discriminator characteristic (S-curve), and its shape has a form similar to a general sine (SIN) function.

Therefore, by changing the reference phase generated by the local code generator 131 by the tracking means 140 and tracking it again with the matching filters 132 and 133 of the capturing means 130, the phase difference of the input received signal is reduced. It will disappear. It tracks phase errors at chip rate, allowing faster phase error tracking in systems with discontinuous code transmissions, such as asynchronous. This is because it is difficult to track faster because the accumulated time of a certain chip period is required in the existing DLL, whereas the phase error is tracked at the chip speed using a matched filter, thereby enabling faster phase error tracking.

That is, in the case of configuring the tracking circuit using the DLL, in particular, if the symbol correlation interval in the DLL is 64 chips, the tracking in the sync code interval existing only in the first symbol interval within one time slot is performed only four times. Since the correlation length is increased to 128 chips, only two phase tracking is possible in one sync code interval.

As such, the use of the correlator becomes difficult to track quickly. In contrast, since the present invention uses a matched filter, it is possible to track 256 times in the chip speed, that is, in one sync code interval. Accordingly, the synchronization code existing only during a very short interval can always be tracked as the minimum phase error.

As described above, in the present invention, since the initial synchronization acquisition apparatus and method in the receiver of the code division multiple access system use two matching filters for the acquisition and tracking of spreading codes, the acquisition and tracking of spreading codes is more effective. This can be done quickly and quickly, reducing the initial synchronization time of the overall system.

In addition, not only continuous signal transmission such as a synchronous method but also fast and accurate acquisition and tracking are possible in a non-continuous code transmission in an asynchronous method, and a reliable system can be constructed through fast and accurate synchronization.

In addition, since two matching filters are used in common in the capturing and tracking means, there is an effect of suppressing an increase in the complexity of hardware.

Claims (7)

Analog / digital conversion means for converting the received code into a digital signal of a predetermined sample; Decimation means for decimating the digitally converted signal to a predetermined ratio; Phase shift the phase of the decimated code with a plurality of matched filters so as to have a phase difference of about one chip from the reference phase of the local code, and compare the phase of the phase shifted received code with a predetermined threshold. Capturing means for selecting an output larger than the value; And a tracking means for obtaining a difference based on an arbitrary phase among each code shifted about one chip input from the capturing means, and changing the local code phase based on the difference value. Initial Sync Acquisition Device in Receiver of Division Multiple Access System. 2. The apparatus of claim 1, wherein the acquiring means comprises: a local generator for generating an arbitrary reference phase, a first matching filter for phase shifting the decimated received code phase half a chip faster than the arbitrary reference phase and loading it into a memory; And a second matching filter for shifting the phase of the decimated received code half a chip later than the arbitrary reference phase and loading it into a memory, and a threshold for determining each output value phase shifted by the first and second matching filters. And a comparator for selecting one value larger than a threshold value in comparison with the value. 2. The apparatus of claim 1, wherein the tracking means includes first and second bandpass filters for bandpass filtering respective output values of the first matched filter and the second matched filter, and a square of the output values of the first and second bandpass filters. The first and second squares to obtain the sum, the adder to calculate the difference by adding the output values of the first and second squares, and the voltage-controlled oscillator is driven in accordance with the value of the difference between the adders generated in the local generator An initial synchronization acquisition device in a receiver of a code division multiple access system comprising a loop filter for varying an arbitrary reference phase. Changing the received code into a digital signal of a predetermined sample and then decimating the converted value at a predetermined ratio; Phase shifting the phases of the decimated spreading code by half-chip phase shifting by using a plurality of matched filters so as to generate a phase difference of one chip from each other; Comparing the output value of each matched filter with a predetermined threshold value; Selecting a larger value from a value greater than a threshold as a result of the comparison and performing a verification procedure on the selected value; A phase difference detecting step of detecting a difference between a locally generated code phase and an input code phase after the checking procedure; And a phase difference correction step of changing a generation phase of a locally generated code by a phase difference from an input received signal according to a difference value between the detected phase of the input code and a locally generated code. Initial synchronization acquisition method in the receiver. 5. The method of claim 4, wherein, in the phase difference correction step, when the difference between the phase of the reception spreading code and the code phase generated by the local generator is a negative value, the local generator occurs at a point in time as much as the negative output value. Initial synchronization acquisition method in a receiver of a code division multiple access system. 5. The method of claim 4, wherein, in the phase difference correction step, when the difference between the phase of the received spreading code and the code phase generated by the local generator is a positive value, the local generator is slowed down by the positive output value. Initial synchronization acquisition method in a receiver of a code division multiple access system. 5. The code division multiple access system according to claim 4, wherein in the phase difference correction step, when the difference between the phase of the received spreading code and the code phase between the local code phase is zero, the current generation phase of the local generator is maintained. Initial synchronization acquisition method in the receiver of the.