KR100369236B1 - Semiconductor device having desired gate profile and Method of making thereof - Google Patents

Abstract

A method of manufacturing a nonvolatile memory device or other semiconductor device in which a control gate made of a conductive material is formed uniformly is disclosed. A silicon layer is formed on the buffer oxide film on the semiconductor substrate. After the buffer oxide film is formed, a stop film is formed. A control gate made of a conductive material such as a floating gate of an EEPROM memory device is provided on the silicon layer, the gate oxide film, and the substrate. The top of the substrate is then etched to form trenches. The sidewalls of the trenches are oxidized to produce even Buzzbees on top and bottom of the control gate material. Next, a field oxide film filling the trench is formed. Since the burrs beak is formed evenly on and under the control gate material during sidewall oxidation of the trench, it is possible to prevent the sidewall of the floating gate from having a positive slope, for example, to achieve uniformity.

Description

Semiconductor device having desired gate profile and method for manufacturing the same

The present invention relates to a control gate such as a floating gate of a memory device and a method of manufacturing the same. More specifically, the present invention relates to a self-aligned shallow trench isolation technique for simultaneously forming a gate and an active region.

In the manufacture of memory devices, the degree of integration of a cell is largely determined by the layout of the cell array and its physical dimensions. Below the half-micron design rule, scalability is limited by the photolithographic resolution that can be achieved during the manufacturing process and the alignment tolerances of the masks used in the process. Alignment tolerance is limited by the mechanical technique used to form the masks and the technique of printing the masks between the layers. It is desirable to use fewer masks as alignment tolerances accumulate in multiple stages of manufacturing. Fewer masks minimize the possibility of misalignment. Thus, "self-aligned" process steps have been developed for manufacturing semiconductor devices.

Device isolation structures, such as field oxide, between individual cells in a memory cell array consume chip areas useful for active circuitry. Therefore, it is desirable to minimize the size of the device isolation structure in order to increase the degree of integration of memory cells and active circuits in the substrate. However, the size of the device isolation structure is limited by its fabrication process or alignment.

Typically, device isolation structures are grown in various regions of the chip by thermal field oxidation processes such as LOCal Oxidation of Silicon ("LOCOS"). According to the LOCOS method, after the pad oxide film and the nitride film are formed in sequence, the nitride film is patterned. Subsequently, the silicon substrate is selectively oxidized using the patterned nitride film as a mask to form a field oxide film region. However, according to the LOCOS device isolation, the growth of the oxide film is eroded from the lower portion of the nitride film provided as a mask during the selective oxidation of the silicon substrate to the side of the pad oxide film, thereby generating a bird's beak at the end of the field oxide film. By such a burj bek, the field oxide film is extended to the active region of the memory cell to reduce the width of the active region, thereby degrading the electrical characteristics of the memory device.

For this reason, a shallow trench isolation structure (hereinafter referred to as "STI") structure is drawing attention in the ultra-high density semiconductor device. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide film is deposited to fill the trench. Next, the oxide film is etched by etch back or chemical mechanical polishing (CMP) to form a field oxide film in the trench.

The above-described LOCOS or STI methods commonly include a mask step for defining an isolation region on a substrate and a field oxide film formed thereon. After forming the device isolation structure, mask steps for forming memory cells are performed. Therefore, the alignment tolerance accompanying the formation of the device isolation structure and the alignment tolerance accompanying the layout of the memory cell are combined to cause misalignment causing device failure.

As one method for solving the alignment problem, a method of self-aligning the LOCOS device isolation structure is formed on the floating gate when forming the floating gate of the nonvolatile memory device. Further, a method of self-aligning and forming an STI structure in a floating gate is disclosed in US Pat. No. 6,013,551 issued to Jong Chen and the like. According to these methods, since the floating gate and the active region are defined and manufactured simultaneously using one mask, alignment tolerances do not accumulate.

Nonvolatile memory devices have an almost indefinite storage capacity. Recently, there is an increasing demand for flash memory capable of electrically input and output of data such as EEPROM. The memory cells of these devices generally have a vertically stacked gate structure with floating gates formed on top of a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate. In flash memory cells having this structure, data is stored by applying an appropriate voltage to the control gate and the substrate to insert or withdraw electrons from the floating gate. At this time, the dielectric film functions to maintain a potential on the floating gate.

The self-aligned STI process has the advantage of being able to form the floating gate and the active region at the same time, but as the aspect ratio of the gap increases, gaps or voids inside the trench during gap filling void) increases the likelihood of creation. In addition, when a high density plasma (hereinafter referred to as "HDP") oxide film having excellent gap filling capability is used, the edge portion of the polishing finish layer existing under the deposition of the HDP oxide is eroded and the field oxide film region is negatively inclined. (negative slope) This produces gate residues under the inclined portions of the field region during subsequent gate etching processes.

However, the above-mentioned problems can be sufficiently solved by optimizing the deposition conditions of the HDP oxide film to improve the gap filling capability, or removing the negative slope of the field region using a wet etchant.

1A to 1E are perspective views illustrating a method of manufacturing a conventional flash memory device using a self-aligned STI technology.

Referring to FIG. 1A, after the gate oxide film (ie, tunnel oxide film) 11 is formed on the silicon substrate 10, the first polysilicon layer 13 and the nitride film 15 are formed on the gate oxide film 11. Deposition in turn.

Referring to FIG. 1B, the nitride layer pattern 15, the first polysilicon layer 13, and the gate oxide layer 11 are patterned by a photolithography process to form the nitride layer pattern 16, the first floating gate 14, and the gate oxide layer pattern. (12) is formed. Next, the exposed portion of the substrate 10 is etched to a predetermined depth to form the trench 18. That is, the active region and the floating gate are simultaneously defined during the trench formation process using one mask.

Referring to FIG. 1C, the exposed portion of trench 18 is heat treated in an oxidizing atmosphere to cure silicon damage caused by high energy ion bombardment during the trench etching process. Then, the trench oxide film 20 is formed on the inner surface including the bottom and sidewalls by an oxidation reaction between the exposed silicon and the oxidant.

During the oxidation process, an oxidant penetrates into the side of the gate oxide layer pattern 12 from under the first floating gate 14, thereby forming a burj beak at both ends of the gate oxide layer pattern 12. As a result of the Buzz beak, the bottom edge portion of the first floating gate 14 is bent to the outside while the both ends of the gate oxide layer pattern 12 are expanded, so that the lower portion of the sidewall of the first floating gate 14 has a positive slope. do. Here, the sidewall having a positive slope means that the sidewall has an inclination with respect to the etchant. That is, as shown, the penetration of the oxidant is suppressed by the presence of the nitride film pattern 16 directly below the nitride film pattern 16 so that the upper sidewall of the first floating gate 14 has a negative slope. On the other hand, the bottom edge portion of the lower portion of the first floating gate 14 is bent to the outside to have a positive slope, so that the bottom edge portion of the first floating gate 14 is eroded by the etchant introduced from the upper direction of the substrate as the sidewall of the mesa structure, It will act as a barrier for the layer.

Referring to FIG. 1D, when an oxide film (not shown) is formed by chemical vapor deposition (hereinafter referred to as “CVD”) method to fill trench 18, when the upper surface of nitride film 16 is exposed. CVD-oxide films are removed by a CMP process. As a result, a field oxide film 22 including the trench oxide film 18 is formed inside the trench 18.

Subsequently, after the nitride film pattern 16 is removed by a phosphate strip process, the first polysilicon layer 13 may be formed to form a second floating gate on the first floating gate 14 and the field oxide film 22. The material is deposited to form a second polysilicon layer (not shown). The second polysilicon layer on the field oxide layer 22 is partially removed by a photolithography process to form a second floating gate 24 separated from neighboring cells. The second floating gate 24 is in electrical contact with the first floating gate 14 and serves to increase the area of the interlayer dielectric film to be formed in a subsequent process.

Subsequently, the ONO interlayer dielectric film 26 and the control gate layer 28 are sequentially formed on the entire surface of the resultant product. The control gate layer 28 is typically formed of a polyside structure in which a doped polysilicon layer and a tungsten silicide layer are stacked.

Referring to FIG. 1E, after the control gate layer 28 is patterned by a photolithography process, the exposed interlayer dielectric layer 26 and the second and first floating gates 24 and 14 are anisotropic dry etched to be fired. Complete the volatile memory device.

At this time, as shown by the dotted line A in FIG. 1D, the lower portion of the sidewall of the first floating gate 14 has a positive slope. Therefore, the bottom edge portion of the first floating gate 14 masked by the field oxide layer 22 is left unetched by the anisotropic etching characteristic of the dry etching process (that is, the etching proceeds only in the vertical direction). . As a result, line-shaped polysilicon residues 14a are formed along the surface boundaries of the field oxide film 22 and the active region. This polysilicon residue 14a forms an electrical bridge between adjacent floating gates, causing electrical failure of the device.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device or other device in which sidewalls of a gate or other conductive structure such as a floating gate structure in a flash memory device can implement a good profile without having a positive slope. It is.

1A to 1E are perspective views illustrating a method of manufacturing a flash memory device having a self-aligned shallow trench device isolation by a conventional method.

2A to 2I are perspective views illustrating a method of manufacturing a floating gate of a nonvolatile memory device according to a first embodiment of the present invention.

3 is an enlarged cross-sectional view of a portion B of FIG. 2D.

4A and 4B are perspective views illustrating a method of manufacturing a floating gate of a memory device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 101 gate oxide film

102 gate oxide film pattern 103 first silicon layer

104: first silicon layer pattern 105: buffer oxide film

106: buffer oxide film pattern 107: stop film

108: stopper pattern 109: trench

110 trench oxide film 112 CVD oxide film

124: field oxide film 126: second silicon layer pattern

128: interlayer dielectric film 130: control gate

140: HTO film 141: HTO film pattern

150: SiON film 151: SiON film pattern

160: photoresist pattern

In order to achieve the above object, the present invention provides a self-aligning method for manufacturing a semiconductor device comprising a floating gate and an active region associated therewith, and a semiconductor device corresponding thereto. The floating gate and the active region are formed in a region of the substrate of the semiconductor memory device defined by a field oxide region formed at least in the trench. The trench is formed with the formation of at least a first segment of the floating gate. The method includes uniformly forming an oxide film on sidewalls of the first fragment of the floating gate, forming a buffer layer on the first fragment of the gate, and forming the buffer film prior to forming the trench. Removing. According to the method, the sidewalls of the first piece can be more evenly oxidized before laminating at least another piece of conductive material on the first piece of the floating gate.

In another embodiment, a gate oxide film is formed on a semiconductor substrate, a first conductive layer is formed on the gate oxide film, and a buffer film (for example, an oxide film) is formed on the first conductive layer. Subsequently, a stop layer is formed on the buffer layer, and the stop layer and the buffer layer are patterned to form a stop layer pattern and a buffer layer pattern. The first conductive layer and the gate oxide layer are patterned to form a floating gate layer and a gate oxide layer, which are first conductive layer patterns, and an upper portion of the substrate is etched to form trenches. The inner surface of the trench is oxidized to form a trench oxide film on the inner surface of the trench, and a burj beak is formed above and below the floating gate layer to prevent the formation of a positive profile on the sidewall of the patterned floating gate layer. Next, a field oxide film filling the trench is formed.

In addition, the object of the present invention is to form a gate oxide film on a semiconductor substrate; Forming a first conductive layer on the gate oxide film; Forming a buffer film such as an oxide film on the first conductive layer; Forming a stop layer on the buffer oxide layer; A floating gate is formed from the first conductive layer by patterning the blocking film, the buffer oxide film, the first conductive layer, the gate oxide film and the substrate using one mask, and at the same time the floating gate in the substrate adjacent to the floating gate. Forming a trench to align with the trench to define an active region of the substrate; Oxidizing an inner surface of the trench to form a trench oxide film on the inner surface of the trench, and forming a burj beak on top and bottom of the floating gate layer to prevent formation of a positive profile on sidewalls of the patterned floating gate layer; And forming a field oxide layer filling the trench.

According to another embodiment of the present invention, a buffer film provided as an oxide mask layer is formed between the floating gate layer and the nitride film so as to generate a buzz beak on the upper and lower portions of the floating gate layer during the subsequent oxidation of the sidewalls of the trench. Then, the sidewalls of the floating gate layer may be prevented from having the positive slope by the Buzzbees, thereby preventing an electrical failure of the device caused by the gate residue during subsequent gate etching.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

2A to 2I are perspective views illustrating a method of manufacturing a nonvolatile memory device in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, a silicon oxide film or a silicon oxynitride film is grown on a semiconductor substrate 100 made of a material such as silicon to form a gate oxide film (eg, a tunnel oxide film) 101 of a cell transistor. . When exposed to air on the semiconductor substrate 100, a natural oxide film is formed by reacting with oxygen in the air. Therefore, in the semiconductor substrate 100 according to the present embodiment, although not shown, a natural oxide film is formed. In the present embodiment, the gate oxide film 101 is formed to have a thickness of about 10 to 500 kV, preferably about 75 kW in the case of a low voltage semiconductor device, and about 300 kW in the case of a high voltage semiconductor device, except for such a natural oxide film. Grow thinly.

A first silicon layer 103 to be used as a floating gate on the gate oxide film 101 is formed by a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 200 to 1500 mW, preferably 500 mW, and a conventional doping method. For example, the first silicon layer 103 is doped with a high concentration of N-type impurities by POCl ₃ diffusion, ion implantation, or in-situ doping. Preferably, the first silicon layer 103 is formed of polysilicon or amorphous silicon. At this time, the first silicon layer 103 is exposed to the air so that a native oxide is formed to a thickness of about 30 to 35 kPa.

A buffer film 105 is formed on the first silicon layer 103 to a thickness of about 10 to 500 microseconds (excluding the thickness of the natural oxide film), which is generally the same thickness as the gate oxide film 102. The buffer film 105 may be an oxide film formed by thermal oxidation or plasma-enhanced chemical vapor deposition (PE-CVD). In addition, the buffer layer 105 may be formed by partially oxidizing a surface portion of the first silicon layer 103 by plasma treatment of an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas. It may be. In addition to oxide films, any buffer material may be used to prevent irregular formation of the gate during trench formation or to planarize the edges or sidewalls of the first or other fragments of the gate. As mentioned above, if the buffer material is not used prior to the oxidation of the trench, the floating gate will be deformed or have an unwanted positive slope.

An etch stopping layer 107 is deposited on the buffer oxide film 105 to a thickness of about 100 to 3000 mW, preferably 1500 mW by LPCVD. The stopper film 107 acts as a polishing finish layer in a subsequent CMP process or an etch back process. The blocking film 107 also covers the buffer oxide film 105 during the subsequent thermal oxidation process of the trench to prevent oxygen and oxidant from penetrating into the first silicon layer 103 through the buffer oxide film 105. . Therefore, the blocking film 107 is preferably formed using a material having oxidation resistance, for example, nitride such as SiN, SiON or BN.

The blocking film 107 may be formed using polysilicon. In this case, the blocking film 107 is partially oxidized in the subsequent oxidation process, but it can be used as an end-point detecting layer in the etch back process or the CMP process.

Optionally, an antireflection film is formed by the CVD method to smoothly perform the subsequent photolithography process on the blocking film 107. The anti-reflection film may be formed using polysilicon, silicon oxide such as high temperature oxide or medium temperature oxide, or silicon oxynitride (SiON). The antireflection film may be formed of a single layer or a plurality of layers.

In this embodiment, a double layer composed of a hot temperature oxide layer (hereinafter referred to as “HTO”) 140 and a SiON film 150 is formed as an antireflection film. The HTO film 140 and the SiON film 150 can be easily formed by a well-known CVD method, and they act as antireflection films to prevent light from being reflected from the lower substrate during the photolithography process. To facilitate formation. The HTO film 140 is formed to a thickness of 200 to 2000 kPa, preferably 500 kPa, and the SiON film 150 is formed to have a thickness of 200 to 3000 kPa, preferably 800 kPa.

Referring to FIG. 2B, a photoresist is applied on the SiON film 150 by spin coating to form a photoresist film (not shown). Next, the photoresist film is exposed and developed using a photo mask to form a photoresist pattern 160 that defines the layout of the floating gate.

Using the photoresist pattern 160 as an etching mask, the SiON film 160, the HTO film 150, the blocking film 107, and the buffer oxide film 105 are sequentially etched, as shown in the figure, and the SiON film pattern 161, a HTO film pattern 151, a blocking film pattern 108, and a buffer oxide film pattern 106 are formed. Next, the photoresist pattern 160 is removed through an ashing and stripping process.

Referring to FIG. 2C, the resultant is transferred to another etching chamber to perform an etching process of polysilicon and oxide. Here, an etching gas for etching polysilicon and oxide is introduced to etch the first silicon layer 103 to form a first silicon layer pattern 104. In this case, the first silicon layer pattern 104 is used as a first floating gate of the nonvolatile memory device.

Subsequently, in the same etching chamber, the gate oxide layer 101 is etched to form the gate oxide layer pattern 102, and the substrate 100 is etched to a depth of about 1000 to 5000 GPa, preferably 2700 GPa to etch the trench 109. Form. As a result, the floating gates defined by the first silicon layer pattern 104 are separated from each other by the trench 109.

In the process of etching the upper portion of the first silicon layer pattern 104 and the semiconductor substrate 100, the SiON layer pattern 151 and the HTO layer pattern 141 formed on the blocking layer pattern 108 are removed.

By the formation of the trench 109, the active region and the floating gate are simultaneously defined using one mask. Thus, the floating gate is self-aligned in the active region.

Referring to FIG. 2D, the inner surface of the trench 109 is treated in an oxidative atmosphere to remove silicon damage caused by high energy ion bombardment during the trench etching process and to prevent the generation of leakage currents. As a result, the trench oxide layer 110 is formed to a thickness of about 10 to 500 kPa, preferably 30 to 40 kPa, along the inner surface of the trench 109, that is, the bottom surface and the sidewalls. The trench oxide film 110 may be formed by a dry oxidation method in a mixed atmosphere of nitrogen (N ₂ ) and oxygen (O ₂ ) at a temperature of 800 to 950 ° C., or may be formed by a wet oxidation method at a temperature of 700 ° C. or more.

As is well known, the formation reaction of the oxide film is as follows.

As can be seen from the above equation, since the oxidant diffuses into the layer having a silicon (Si) source and oxidation of silicon proceeds, an oxide film is grown on the surface of the first silicon layer pattern 104 and the surface of the silicon substrate 100.

3 is an enlarged cross-sectional view of a portion B of FIG. 2D.

When the trench oxide film 110 is formed, as shown in FIG. 3, an oxidant (or an oxidizing gas) penetrates into the side surface of the gate oxide film pattern 102 under the first silicon layer pattern 104 so that the first buzz is formed. Beak a occurs. At the same time, an oxidant penetrates into the side surface of the buffer oxide film pattern 106 from the lower portion of the blocking film pattern 108, and a second buzz bee b is also generated on the first polysilicon layer pattern 104.

According to the conventional method shown in Fig. 1C, the burj beak is generated only under the silicon pattern used as the floating gate. As the oxide film grows at the bottom edge of the floating gate during oxidation, the lower portion of the gate sidewall has a positive slope. In contrast, in the present invention, since the first and second buzzets a and b are formed at the same time under and over the gate sidewall, the bottom edge portion of the gate sidewall does not bend outwardly. That is, the positive slope is prevented by the second buzz beak b formed on the first silicon layer pattern 104. Therefore, according to the present invention, the floating gate formed of the first silicon layer pattern 104 has a desirable profile.

Referring to FIG. 2E, an oxide film 112 having excellent gap filling properties such as USG, O ₃ -TEOS USG, or HDP oxide film is deposited to a thickness of about 5000 kPa by the CVD method to fill the trench 109. Preferably, the HDP oxide film 112 is formed using SiH ₄ , O ₂ and Ar gases as the plasma source.

At this time, the trench 109 is embedded by improving the gap filling capability of the HDP oxide film 112 so that cracks or voids are not formed in the trench 109.

Since the HDP oxide film 112 has a property of simultaneously performing deposition and sputter etching, it is deposited at a constant speed in a wide area but deposited to a certain thickness in a narrow area, and then the deposition rate and the sputter etching rate are the same. No more oxide film is deposited. When the sputter etching capability is increased to improve the gap filling property of the HDP oxide film 112, the edge portion of the stopper film pattern 106 including nitride is eroded so that the field oxide film has a negative slope. In order to prevent this problem, a method of changing the deposition conditions or removing the negative slope of the field oxide film by using a wet etchant may be used when the blocking film 105 is formed.

Subsequently, a capping oxide film (not shown) made of PE-TEOS may be deposited on the HDP oxide film 112 by a plasma method using Si (OC ₂ H ₅ ) ₄ as a source.

Further, if necessary, annealing is performed under a high temperature and inert gas atmosphere of about 800 to 1050 ° C. in order to densify the HDP oxide film 112 to lower the wet etch rate for the subsequent cleaning process.

Referring to FIG. 2F, the HDP oxide layer 112 is planarized by performing an etch back or CMP method until the top surface of the blocking layer pattern 108 is exposed. Thus, the HDP oxide film 112 on the stop film is partially removed to form the field oxide film 124 in the trench 109.

Referring to FIG. 2G, the blocking layer pattern 108 made of silicon nitride is removed by a phosphate strip process. In this case, the buffer oxide layer pattern 106 prevents the first silicon layer pattern 104, which is the first floating gate made of silicon below, from being damaged during the removal of silicon nitride by the phosphate strip.

Subsequently, the substrate is cleaned with an etchant containing hydrofluoric acid for about 30 seconds in advance. The field oxide layer 124 is partially removed due to the strip of the blocking layer pattern 108 and the pre-cleaning process, and the buffer oxide layer pattern 106 formed on the first silicon layer pattern 104 is also removed. At this time, the thickness of the field oxide film 124 is about 250 GPa or more.

Referring to FIG. 2H, a second silicon layer (not shown), such as polysilicon or amorphous silicon, is deposited on the exposed first silicon layer pattern 104 and the field oxide layer 124 to a thickness of about 2000 GPa or more by LPCVD. do. The second silicon layer is formed to be in electrical contact with the first silicon layer pattern 104 which is the first floating gate. The second floating gate 126 is then doped with a high concentration of N-type impurities by conventional doping methods such as POCl ₃ diffusion, ion implantation, or in-situ doping to form a second conductive layer.

In addition, the second conductive layer may be formed by depositing polysilicon doped with impurities by performing a CVD method while injecting impurities during formation of the second silicon layer without performing a separate doping process. The second floating gate formed by the second conductive layer is formed to increase the area of the interlayer dielectric film to be formed in a subsequent step, and is preferably formed as thick as possible.

Subsequently, the second conductive layer on the field oxide layer 124 is partially removed by a conventional photolithography process to form second silicon layer patterns 126 constituting the second floating gate. The second floating gates thus formed are separated from each other with the floating gates of neighboring cells.

Subsequently, an interlayer dielectric film 128 made of ONO is formed on the entire surface of the resultant product so as to completely insulate the second silicon patterns 126 which are the second floating gates. For example, the second floating gate 126 is oxidized to grow a first oxide film having a thickness of about 100 GPa, and a nitride film of about 130 GPa is deposited thereon, and a second oxide film having a thickness of about 40 GPa is formed on the nitride film. An interlayer dielectric film 128 having an equivalent oxide film thickness of about 100 to 200 microseconds is formed.

Subsequently, an N ⁺ doped polysilicon layer and a metal silicide layer such as tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), and tantalum silicide (TaSix) were laminated on the interlayer dielectric film 128. The control gate layer 130, which is the third conductive layer, is formed. Preferably, the polysilicon layer of the control gate layer 130 is formed to a thickness of about 1000 kPa, and the metal silicide layer is formed to a thickness of about 100 to 1500 kPa.

Referring to FIG. 2I, after the control gate layer 130 is patterned by a photolithography process, the exposed interlayer dielectric layer 128, the second floating gate fragment 126, and the first floating gate fragment 104 are dry-etched. By patterning each cell in turn to form a stacked floating gate of a memory cell. In this case, the dry etching is performed until the upper surface of the substrate 100 between the field oxide layers 124 is exposed.

Since the sidewall of the first silicon layer pattern 104 which is the first floating gate does not have a positive slope, the sidewall portion of the first silicon layer pattern 104 is not deformed and does not have an outwardly bent portion. Accordingly, since the portion exposed by the mask pattern of the first silicon layer pattern 104 is completely removed during the dry etching process, no silicon residue is formed on the surface boundary between the field oxide layer 124 and the active region.

Subsequently, although not shown, a source / drain region of the memory cell is formed by an ion implantation process, and then an interlayer insulating film ILD is coated on the resultant. The interlayer insulating layer is etched to form contact holes exposing the source / drain regions, and then contact plugs filling the contact holes are formed. Subsequently, a metallization layer in electrical contact with the contact plug is deposited, and a back-end process is performed using an interlayer insulating film (IMD), vias, and a metal mask.

Example 2

The processes as shown in FIGS. 2B and 2C of Example 1 described above are performed in separate etching chambers, respectively. However, according to the second embodiment of the present invention, the above processes are continuously performed in one etching chamber. Example 2 is the same as Example 1 except that the anti-reflection film is not formed and the substrate etching process is performed in one etching chamber using the photoresist as an etching mask. Here, the same reference numerals as in Example 1 denote the same members.

4A and 4B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a second embodiment of the present invention.

Referring to FIG. 4A, the gate oxide film 101, the first silicon layer 103, the buffer oxide film 105, and the blocking film 107 are sequentially formed on the substrate 100 as in the first embodiment. .

Referring to FIG. 4B, after the photoresist pattern 160 is formed on the blocking layer 107 as in Example 1 using a photo mask for defining a floating gate, the photoresist pattern 160 is formed. Patterning the stop layer 107, the buffer oxide layer 105, the first silicon layer 103, and the gate oxide layer 101 by using the etch mask as an etching mask, and thus the stop layer pattern 108, the buffer oxide layer pattern 106, and the first layer. A pattern structure consisting of the silicon layer pattern 104 and the gate oxide layer pattern 102 is formed.

Subsequently, after the substrate 100 is etched to form the trench 109, the photoresist pattern 160 is removed by performing an ashing or stripping process.

Thereafter, the processes as shown in FIGS. 2C to 2I of Embodiment 1 are performed to provide a floating gate of the nonvolatile memory device according to the second embodiment of the present invention.

As described above, according to the present invention, a buffer oxide film is further formed between the first fragment of the floating gate layer and the blocking film to generate a burj beak on top of the floating gate. On subsequent oxidation of the sidewalls of the trenches, Buzzbeeks created above and below the first fragment of the floating gate planarize the sidewalls of the floating gate. Then, the sidewall of the floating gate layer may be prevented from having an undesirable slope, and a nonvolatile memory device having a gate having a desired profile may be implemented.

In addition, since no silicon residue is formed during dry etching for subsequent gate formation, neighboring gates may be shorted to each other by the silicon residue, thereby preventing electrical failure of the device.

In addition to the uniform formation of the floating gate, it is apparent that the present invention can be applied to the case of forming another conductive layer in a semiconductor device requiring uniformity. That is, the present invention can be applied wherever the above-mentioned suppression of the buzz bee is required.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (45)

A conductive layer and a corresponding active region are fabricated in a region of the semiconductor device at least partially defined by a field oxide region formed in the trench of the substrate, and at least a first fragment of the floating gate is formed on the substrate and the first dielectric material. In the self-aligning method to form, Forming a buffer film over the first fragment of the floating gate before forming the trench; And oxidizing the sidewalls of the first piece more evenly before removing the buffer film to deposit at least another piece of the floating gate over the first piece of the floating gate. The method of claim 1 wherein the first fragment is formed of polysilicon or amorphous silicon. The method of claim 1, wherein the buffer film is an oxide film formed by thermal oxidation. The method of claim 1, wherein the buffer film is formed by plasma-enhanced chemical vapor deposition. The method of claim 1, wherein the buffer layer is formed by oxidizing an oxidizing gas to oxidize a surface of the first piece of the floating gate. The method of claim 5, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrose oxide (N ₂ O) gas. The method of claim 1, wherein the buffer film is formed to a thickness of 10 to 500 kPa. A self-aligning method for forming a floating gate and an active region associated therewith on a substrate of a semiconductor device, Forming a gate oxide film on the semiconductor substrate; Forming a first conductive layer on the gate oxide film; Forming a buffer oxide film on the first conductive layer; Forming a stop layer on the buffer oxide layer; Patterning the stop layer and the buffer oxide layer to form a stop layer pattern and a buffer oxide layer pattern; Patterning the first conductive layer to form a floating gate that is a first conductive layer pattern, and etching the upper portion of the gate oxide layer and the substrate to form a gate oxide pattern and a trench; Oxidizing an inner surface of the trench to form a trench oxide film on the inner surface of the trench, and forming a bird's beak on top and bottom of the floating gate layer to prevent formation of a positive profile on sidewalls of the patterned floating gate layer; And And forming a field oxide film filling the trench. The method of claim 8, wherein the first conductive layer is formed of polysilicon or amorphous silicon. 9. The method of claim 8, wherein the stopper membrane comprises a nitride component. The method of claim 8, wherein the buffer oxide film is formed by a thermal oxidation method. 9. The method of claim 8, wherein the buffer oxide film is formed by plasma-enhanced chemical vapor deposition. The method of claim 8, wherein the buffer oxide film is formed by oxidizing a surface of the first conductive layer by plasma treating an oxidizing gas. The method of claim 13, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrose oxide (N ₂ O) gas. 9. The method of claim 8, wherein the buffer oxide film is formed to a thickness of 30 to 500 kPa. The method of claim 8, wherein the field oxide film forms an oxide film covering the blocking film while filling the trench, and the oxide film is formed by a chemical mechanical polishing method or an etch back method until the surface of the blocking film pattern is exposed. Forming by etching to have. 9. The method of claim 8, further comprising forming an anti-reflection film on the barrier film by chemical vapor deposition. 18. The method of claim 17, wherein the antireflective film is comprised of at least one material selected from the group of polysilicon, silicon nitride, silicon oxynitride, and silicon oxide. The method of claim 17, wherein after forming the photoresist pattern for forming the floating gate on the anti-reflection film, the anti-reflection film, the stop film and the buffer oxide film are formed by using the photoresist pattern as an etching mask in a first etching chamber. After patterning and removing the photoresist pattern, forming the first conductive layer pattern, the gate oxide film pattern, and the trench while removing the anti-reflection film pattern in a second etching chamber. 18. The method of claim 17, After forming a photoresist pattern for forming a floating gate on the blocking film, using the photoresist pattern as an etching mask to perform a continuous etching process in one etching chamber, the blocking film, And patterning a buffer oxide layer, a first conductive layer, and a gate oxide layer, and etching the upper portion of the substrate to form the blocking layer pattern, the first conductive layer pattern, the gate oxide layer pattern, and the trench. Forming a gate oxide film on the semiconductor substrate; Forming a first conductive layer on the gate oxide film; Forming a buffer film on the first conductive layer; Forming a stop layer on the buffer layer; Patterning the blocking film, the buffer film, the first conductive layer, the gate oxide film, and the substrate using a mask to form a floating gate from the first conductive layer, and at the same time the floating gate in the substrate adjacent to the floating gate. Forming a trench in alignment with the substrate to define an active region in the substrate; Oxidizing an inner surface of the trench to form a trench oxide film on the inner surface of the trench, and forming a burj beak on top and bottom of the floating gate layer to prevent formation of a positive profile of sidewalls of the patterned floating gate layer. ; And Forming a field oxide layer filling the trench; and manufacturing a floating gate structure of the nonvolatile memory device. The method of claim 21, wherein the first conductive layer is formed of polysilicon or amorphous silicon. 22. The method of claim 21, wherein the blocking film comprises a nitride component. 22. The method of claim 21, wherein the buffer film is formed of an oxide film formed by thermal oxidation. 22. The method of claim 21, wherein the buffer film is formed by plasma-enhanced chemical vapor deposition. 22. The method of claim 21, wherein the buffer film is an oxide film formed by oxidizing a surface of the first conductive layer by plasma treating a surface of the first conductive layer with an oxidizing gas. 27. The method of claim 26, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrose oxide (N ₂ O) gas. The method of claim 21, wherein the buffer film is formed to a thickness of 30 to 500 kHz. 22. The method of claim 21, wherein after forming the field oxide film, planarizing the field oxide film with a surface of the stop film, removing the patterned stop film, and then interlayer dielectric film and control gate on the floating gate in turn. And forming the memory device. 22. The method of claim 21, further comprising forming an anti-reflection film on the blocking film by chemical vapor deposition. The method of claim 30, wherein the anti-reflection film is formed of at least one material selected from the group consisting of polysilicon, silicon oxynitride, and silicon oxide. delete delete delete delete delete delete delete Semiconductor substrates; A gate oxide film formed on the substrate; Forming a first conductive layer on the gate oxide layer, forming a buffer layer on the first conductive layer, forming a stop layer on the buffer layer, patterning the stop layer and the buffer layer, and forming a stop layer pattern; Forming a buffer layer pattern, patterning the first conductive layer to form a first fragment of a floating gate, etching the upper portion of the gate oxide layer and the substrate to form a gate oxide pattern and a trench, and the trench Oxidize an inner surface of the trench to form a trench oxide film on the inner surface of the trench and to form a burj beak on top and bottom of the first fragment of the floating gate to form sidewalls of the first fragment of the floating gate during formation of the trench oxide film. A first conductive layer formed by planarizing the first conductive layer; A field oxide film formed in the trench while oxidizing an inner surface of the trench; And And a second piece of the floating gate formed to planarize the field oxide layer until the first piece is exposed to be in electrical contact with the first piece. Active area. 40. The self-aligned floating gate and associated active region of claim 39, wherein said first fragment of said floating gate is comprised of polysilicon or amorphous silicon. 40. The self-aligned floating gate and associated active region of claim 39, wherein the buffer film is an oxide film formed by thermal oxidation. 40. The self-aligned floating gate and associated active region of claim 39, wherein the buffer film is formed by plasma-enhanced chemical vapor deposition. 40. The self-aligned floating gate as claimed in claim 39, wherein the buffer film is formed by plasma treating an oxidizing gas to oxidize a surface of the first piece of the floating gate. 44. The self-aligned floating gate and associated active region of claim 43, wherein said oxidizing gas uses oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas. 40. The self-aligned floating gate and associated active region of claim 39, wherein the buffer film is formed to a thickness of 10 to 500 microns.