KR100364783B1 - digital television receiver and method for controlling to antenna in digital television receiver - Google Patents

Abstract

The present invention is to provide an antenna for a digital television receiver and a control device and method thereof capable of increasing the integration of the digital television receiver by configuring a single chip, and receiving digital television broadcast channel signals and subordinate to the control signal. An directional antenna; A signal processor for tuning a desired channel signal from the channel signals and processing the tuned channel signal in a desired form; A detector detecting state signals of the channel signal output from the signal processor; A memory for sorting and storing the detected new state signal with previously detected state signals each time a new state signal is detected; A controller configured to compare the new state signal with the previous state signals and generate the control signal corresponding to the optimum direction of the antenna; And an interface unit for providing the control signal to the antenna.

Description

Digital television receiver and method for controlling the antenna of the digital television receiver

The present invention relates to an apparatus and method for controlling an antenna of a digital television receiver.

(VSB) has been selected as a standard for transmitting terrestrial channels of digital television broadcasting. However, concepts and ideas have recently been proposed as the still early state of antennas used in the VSB receiver. In addition, (ATSC) is also preparing a standardization work for the VSB antenna. At this time, however, no examples of antennas applied to digital television receivers have been disclosed, nor have they been commercialized.

Conventional antennas that can be used as digital television receivers may be classified into two types.

As a first kind, a normal outdoor antenna can be considered. This outdoor antenna has the advantage of having a high reception performance, while the size is large and the installation is inconvenient.

As a second kind, a normal indoor antenna can be considered. This indoor antenna has the advantage of being small in size and easy to install, but it is inconvenient to manually adjust the antenna's directivity while the viewer monitors the screen when the reception sensitivity decreases while watching TV broadcast.

On the other hand, in the terrestrial channel of digital television broadcasting, there may be many multipaths and radio obstacles. Therefore, the reception characteristics of the antenna of the digital television receiver can greatly affect the overall characteristics of the digital television receiver. In the following, with reference to Figs. 1 to 3, problems of those antennas according to different antenna types and channel environments will be listed.

1 is a diagram showing an omnidirectional antenna, FIG. 2 is a diagram showing a directional antenna, and FIG. 3 is a diagram showing a smart antenna.

First, the digital television receiver using the omni-directional antenna of Fig. 1 can receive the main signal in all directions only on channels where the strength of the main signal is strong and the strength of the signals in the multipath is weak. On the other hand, in the channels where the main signal is weak and the multipath signals are strong, such as an urban building area or an indoor antenna, reception of a desired channel is not easy, thereby degrading the performance of the digital television receiver.

Second, in order to solve the shortcomings of the omnidirectional antenna, the use of the directional antenna of FIG. 2 may be considered. However, the main signal may be interrupted by moving jammers in an environment where the change of channel condition is continuously severe. In this case, too, it is not easy to receive the main signal from other directions, which degrades the performance of the digital television receiver. As described above, the omni directional antenna and the directional antenna have a trade off relationship with each other.

Third, in order to solve the shortcomings of the omnidirectional antenna and the directional antenna, the use of the smart antenna of FIG. 3 may be considered. When applying the smart antenna, while the above disadvantages can be solved, the existence of a control system that can effectively control the pattern and directivity of the smart antenna should be premised.

An object of the present invention is to provide an antenna for a digital television receiver and a control apparatus and method thereof, which can increase the integration degree of the digital television receiver by configuring a single chip.

It is another object of the present invention to provide an antenna for a digital television receiver and a control apparatus and method thereof for which the hardware is simple and thus can be configured at low cost.

It is still another object of the present invention to provide an antenna for a digital television receiver and a control apparatus and method thereof for quick judgment and high reliability.

It is still another object of the present invention to provide an antenna for a digital television receiver and a control apparatus and method thereof, which are compatible with other digital television receivers by operating independently of the digital television receiver.

In order to achieve the above objects, the control device of the antenna for a digital television receiver according to the present invention is configured to digitally configure all the control parts and to operate independently from the digital television receiver. The control device for an antenna for a digital television receiver according to the present invention also extracts channel information only from the receiving chip without using any separate hardware. In addition, the control device of the antenna for a digital television receiver according to the present invention is a step-by-step information from the automatic gain controller which is an introduction part of the demodulation part of the receiving chip, the data segment synchronizer which is the middle part, and the equalizer and the signal-to-noise ratio calculator which is the last part. Extract The antenna is controlled to maintain an optimal state using the extracted information. Thus, the apparatus and method of the present invention always optimize the antenna of the digital television receiver under varying terrestrial channel environments and further improve the performance of the digital television receiver.

1 is a diagram showing an omni directional antenna.

2 is a diagram showing a directional antenna.

3 is a diagram showing a smart antenna.

4 is a diagram showing the configuration of a digital television receiver having an antenna according to the present invention and a control device of the antenna.

5 is a block diagram showing a partial detailed configuration of FIG.

6 is a diagram illustrating an interface unit that serves to connect an antenna and an antenna control device.

FIG. 7 is a block diagram for explaining a method of controlling automatic gain using a delayed automatic gain control signal in a digital television receiver.

FIG. 8 is a diagram illustrating a method of automatically controlling gains of a high frequency signal and an intermediate frequency signal directly in a VSB receiving chip.

9 is a block diagram illustrating the role of the signal power detection controller.

10 is a block diagram showing a detailed configuration of a ghost signal power detector.

11 is a graph showing information of a ghost signal detected by a ghost power detector.

12 is a block diagram showing the configuration of the signal-to-noise ratio calculator.

Fig. 13 is a block diagram showing a partial detailed configuration of the antenna control apparatus.

14 is a diagram illustrating signals transmitted and received between components in the antenna control apparatus.

15 is an overall control flowchart of the antenna control apparatus according to the present invention.

16A is a detailed flowchart of the scanning process of FIG.

16B is a flowchart illustrating a process of searching for the maximum power value of the tuned channel signal during the scanning process of FIG. 16A.

FIG. 16C is a flowchart illustrating a counting process considering all antenna states in order to obtain a maximum signal power value during the scanning process of FIG. 16A.

Fig. 17 is a flowchart showing the alignment process of data stored in the memory in detail.

18 is a flowchart illustrating a tracking process of the antenna control apparatus according to the present invention. 19 is a flowchart showing a sub process of the signal power tracking process.

20 is a flowchart illustrating a subprocess of the maximum ghost power tracking process according to the present invention.

21 is a flowchart showing a sub-process of the signal-to-noise ratio tracking process according to the present invention.

* Description of the symbols for the main parts of the drawings *

108: channel signal processing department of digital TV receiver,

109: antenna control device 100: antenna

101: tuner 102: intermediate frequency automatic gain control unit

103: VSB receiving chip 104: detector

105: memory 106: direction controller

107: interface unit

A digital television receiver according to the present invention comprises an antenna for receiving digital television broadcast channel signals and having a direction dependent on the control signal;

A signal processor for tuning a desired channel signal from the channel signals and processing the tuned channel signal in a desired form;

A detector detecting state signals of the channel signal output from the signal processor;

A memory for sorting and storing the detected new state signal with previously detected state signals each time a new state signal is detected;

A controller for comparing the new state signal with the previous state signals to generate the control signal corresponding to the optimum direction of the antenna; and

And an interface unit for providing the control signal to the antenna.

4 is a diagram showing the configuration of a digital television receiver having an antenna according to the present invention and a control device of the antenna. 4 is largely composed of a channel signal processing section 108 and an antenna control device 109 of a digital television receiver.

First, the channel signal processing unit 108 of the digital television receiver is a channel signal received from the antenna 100 of the digital television receiver (in this embodiment, a smart antenna is used. However, other types of antennas may be used.) Among them, a tuner 101 for tuning a desired channel signal, an intermediate frequency automatic gain control unit 102 for automatically adjusting an intermediate frequency (IF) gain of the channel signal tuned from the tuner 101, and the intermediate frequency automatic gain control unit ( And a VSB receiving chip 103 which takes a VSB (Vestigial Side Band) signal from the channel signal from 102.

On the other hand, the antenna controller 109 is used to obtain status signals such as power of a channel signal, power of a ghost signal, and a signal-to-noise ratio from the channel signal taken by the VSB receiving chip 103 of the channel signal processor 108. A detector 104 to obtain, a memory 105 for storing the state signals and updating stored values with newly detected state signals, a state signal from the detector 104 and a previous state stored in the memory 105 A direction controller 106 for obtaining a control signal for controlling the direction of the antenna 100 by comparing the signals, connected between the antenna 100 and the tuner 101 and in accordance with the control signal to the antenna 100. It consists of an interface unit 107 for controlling the direction of.

5 is a block diagram showing a partial detailed configuration of FIG.

In FIG. 5, the VSB receiving chip 103 of FIG. 4 is an automatic gain control unit 103-1 for automatically controlling the gain of the output signal of the intermediate frequency automatic gain control unit 102 again, and the automatic gain control unit 103-. A timing and carrier recovery section 103-2 for recovering timing and carrier loss on the output of 1), an equalizer 103-3 for equalizing the output of the timing and carrier recovery section 103-2, and the equalizer A phase tracker 103-4 for tracking the phase of the output signal of 103-3, correcting forward errors on the output signal of the phase tracker 103-4, and outputting a final VSB signal. Forward error corrector 103-5.

Meanwhile, the detector 104 detects the power of the tuned channel signal using the automatic gain control signal from the automatic gain controller 103-1 of the VSB receiving chip 103. ), Ghost power for detecting power of a ghost signal by using the timing signal of the VSB receiving chip 103 and an output signal of the carrier recovery unit 103-2 and / or a signal from the equalizer 103-3. Detector 104-2 and a signal-to-noise ratio (SNR) calculator 104-3 which calculates a signal-to-noise ratio using the output signal of the phase tracker 103-4 of the VSB receiving chip 103.

On the other hand, the direction controller 106 of FIG. 4 is a signal power tracker 106-1 and the ghost power detector for tracking the power of the tuned channel signal using the output signal of the signal power detector 104-1. The signal-to-noise ratio is measured using a ghost power tracker 106-2 for tracking the power of the ghost signal using the output signal of 104-2, and an output signal of the signal-to-noise ratio calculator 104-43 of the detector 104. A signal-to-noise ratio (SNR) tracker 106-3 for tracking, using the output signals of the trackers 106-1, 106-2, 106-3 in the currently selected antenna pattern to track and track the state signals of the tuned channel signal. If the status signals do not maintain a valid magnitude value, the tracking signal 106-4 and the tracking signal 106-4 change the antenna pattern in the order of the antenna pattern stored in the memory 105. this A scan processor 106-5 and the stored antenna pattern to obtain an effective signal power and antenna pattern while changing the directivity of the antenna 100 and to store the obtained power and pattern values in the memory 105. And a sort processor 106-6 for sorting values in order of the signal power values, while the direction controller 106 is operated by the tracking processor 106-4 by the operation of the memory 105. If it is determined that there is no antenna pattern having a valid size, the scan processor 106-5 again performs a scan process.

Hereinafter, the operation of each major component of FIGS. 4 and 5 will be described in detail. First, the antenna 100 is configured to adjust its beam width, gain, frequency characteristics, etc. in response to a mechanical or electrical control signal from the outside, and further, to take an optimal pattern for reception of a desired channel signal.

As illustrated in FIG. 6, the interface unit 107 connects the antenna 100 and the antenna control device 109.

A process of detecting signal power of the tuned channel signal will be described. First, FIG. 7 is a block diagram illustrating a method of controlling automatic gain using a delayed automatic gain control signal in a digital television receiver, and FIG. 8 illustrates a gain of a high frequency signal and an intermediate frequency signal in the VSB receiving chip 103. This is a block diagram that describes how to do this automatically. The automatic gain control (AGC) scheme according to FIG. 7 controls an intermediate frequency (IF) signal from the VSB receiving chip 103 via a charge pump and a lag filter 110, and the gain of the high frequency signal is the intermediate frequency. Automatic control is performed using the delayed automatic gain control signal from the automatic gain control unit 102. According to the automatic gain control method of FIG. 8, both the gains of the intermediate frequency signal and the high frequency signal are automatically controlled in the VSB receiving chip 103. Meanwhile, the automatic gain control unit 103-1 of FIG. 5 constitutes a loop for controlling one automatic gain control amplifier, and the signal power detector 104-1 of FIG. 5 stores a gain error included in the loop. The signal power of the tuned channel signal is detected from (e.g., an integrator). The signal power detection controller 111 (included in the signal power detector 104-1 of FIG. 5) of FIG. 9 detects the signal power ready signal and the signal power information from the automatic gain control information output from the VSB receiving chip 103. Output to the direction controller 106 of the antenna 100.

As shown in FIG. 10, the ghost signal power detector 104-2 of FIG. 5 receives the received I-channel signal from the VSB receiving chip 103 and a preset synchronization signal value (for reference, each data segment in the VSB transmission scheme). A data segment sync correlator 112 for calculating a correlation value with " 1001 ", and an output value of the data segment sync correlator 112 in 832 delayers. 113), a slicer 114 for providing an increased count value when the accumulated correlation value reaches a predetermined size, a reliability counter 115 for increasing the count number according to the increased count value, and the reliability counter 115 The maximum ghost that sends the ghost power ready signal and the maximum ghost power normalized to the power of the received signal when the value reaches the reference value, to the direction controller 106 of the antenna of FIG. Power detection controller 116.

11 is a graph showing information of a ghost signal detected by the ghost power detector 104-2. That is, FIG. 11 shows a correlation value accumulated in the segment integrator 113 of FIG. 10. A tap having a maximum correlation value is a value accumulated by a main signal, and a correlation value corresponding to a next magnitude is multipath. Accumulated by the ghost signal generated by.

Hereinafter, the signal-to-noise ratio calculator 104-3 will be described in detail.

12 is a diagram showing one configuration of the signal-to-noise ratio calculator 104-3, which calculates a signal-to-noise ratio (SN) using Means Square Error (MSE). The signal-to-noise ratio calculator 104-3 of Fig. 12 subtracts the demodulated signal constellation (received field sync signal or I-channel data) from the decision signal constellation (Deec), decoded signal constellation (train sequencer or decision signal arrangement). 117, a squarer 118 that squares the output of the subtractor 117, an accumulator 119 that accumulates output signals of the squarer 118, and a latch that delays the output of the accumulator 119. And a divider 121 dividing the output of the latch 120 by the window size m of the segment integrator 113 of the power detector 104-2 of the ghost signal. An algorithm of signal-to-noise ratio according to the configuration of Fig. 12 is summarized below. First, the signal-to-noise ratio (SNR) can be represented by Equation (1) below.

SNR = 10 log (Ps / Pn) (1)

In Equation (1), Ps is signal power (= 1), and Pn indicates noise power Pn | mse.

Here, the algorithm for calculating the signal-to-noise ratio due to the mean squared error can be expressed by Equation (2) below.

Pn | mse = sigma (k is from 1 to n) (mse / m) (2)

In formula (2), mse can be represented by the following formula (3).

mse = square of (D_l-R_l) (3)

In Equations 1-3, R_1 is a demodulated constellation, D_1 is a determined constellation, and m indicates a window size of the integrator 113 as described above.

Next, the direction controller 106 and the memory 105 of the antenna of FIGS. 4 and 5 will be described.

13 is a block diagram showing a partial configuration of the antenna control apparatus 109. According to Fig. 13, it can be seen that the direction controller 106 in the antenna control device 109 is composed of the tracking processor, the scan processor and the sort processor 106-4, 106-5, 106-6 and general purpose registers as described above. Here, the general purpose registers shown in FIG. 13 are a pointer register indicating an address of a memory, a direction register (Dir_reg.) That always stores a current antenna state value, and an angle that temporarily stores a state value of an antenna. And a power register for temporarily storing the power value of the received signal. As best shown in Fig. 13, the memory 105 stores the state value (or pattern value) of the antenna 100 and the corresponding power value of the received signal, and stores the stored power values in their magnitude order. It sorts (or sorts) and stores it back in.

14 is a diagram illustrating signals transmitted and received between components in the antenna control apparatus.

15 is an overall control flowchart of the antenna control apparatus according to the present invention. The flowchart of FIG. 15 is largely divided into a scanning process for sensing a channel signal and storing power of the channel signal, an alignment process, and a tracking process (TRACK).

First, according to a scanning process, the antenna controller detects whether a channel signal exists in an initialized state. Subsequently, when the channel signal is detected, the effective power of the detected channel signal is stored in the memory 105 by rotating the directivity of the antenna 9100 by 360 degrees, and the antenna pattern when the maximum signal power is detected is selected. do.

Subsequently, according to the sorting process, the antenna control apparatus arranges the stored antenna patterns in the order of the stored signal powers.

Subsequently, according to the tracking process, first, the antenna control apparatus detects states of the tuned channel signal in the currently selected antenna pattern, that is, power, maximum ghost power, and signal-to-noise ratio of the channel signal, and the detected values Determine whether to maintain a valid size. When the antenna pattern needs to be changed as a result of the determination, the antenna pattern is changed in the order of the antenna patterns arranged and stored. If none of the antenna patterns stored in the memory is valid, the antenna controller performs the above scan process again to obtain a valid signal power and antenna pattern. All of the processes described above monitor the digital television receiver in real time against all moving propagation obstacles, such as humans, keep the antenna in optimum condition according to the monitoring results and further optimize the performance of the digital television receiver. .

FIG. 16A shows a detailed flowchart of the scanning process of FIG. According to Fig. 16A, first, after the antenna controller is initialized, it checks whether detection of power of the received channel signal is ready. When ready (signal PW ready = '1'), the power value of the detected channel signal is taken (Latch power_d). Subsequently, it is checked whether a power value of the detected channel signal is a valid magnitude (check PW_thd). Subsequently, if the power value is found to be valid (PW_thd <PW_reg), the antenna control apparatus starts a maximum value search process for finding the maximum power value of the channel signal and the corresponding antenna pattern (Max_en). Then, a memory address to which the pointer register of the memory 105 specifies the power value of the channel signal temporarily stored in the angle register and the power register of the direction controller 106 and the state of the corresponding antenna. Save to (memo_r_w) and increment the pointer register value by 1 (Pointer ++). In the meantime, the antenna controller performs a maximum value search process and a count process (proc.:MAX._SEAR.COUNT). During the above-described search process and count process, the antenna controller checks whether all patterns of possible antennas have been tried. If all patterns (or states) of possible antennas have not been attempted, each register and direction register value of the direction controller 106 is increased by '1', respectively (Ang._reg ++; Dir._reg ++). If all have been attempted, the pattern value (or state value) of the antenna for which the maximum signal power is detected is set in the direction register in the memory 105. Subsequently, the sort processing process (or sort processing process) is performed through the sort processor 106-6 (Sort_strob = 1, Proc.:SORT), and it is checked whether the sort processing process is completed (check sort_ack = 1). ). Subsequently, when the sort processing is completed (Sort_ack = 1), the tracking processing is performed through the tracking processor 106-4 (track_strob = 1, Proc.:TRACK), and the tracking processing is completed. Check track_ack. On the other hand, if the tracking process is completed (track_ack = 1), the process returns to the initialization process.

16B is a diagram illustrating a process of searching for the maximum power value of the tuned channel signal during the scanning process of FIG. 16A. First, the antenna controller sets the maximum power value of the channel signal to zero (PW_MAX = 0), and checks whether the maximum value enable signal is '1' (MAX_EN = 1). If the maximum enable signal is '1' (MAX_EN = 1), if the current maximum signal power value is less than the value stored in the power register of the direction controller 106, the value stored in each of the registers and the power register is maximum. It takes the signal power value and proceeds to confirm the next maximum enable signal.

FIG. 16C is a flowchart illustrating a counting process considering all antenna states in order to obtain a maximum signal power value during the scanning process of FIG. 16A. According to Fig. 16C, the count value is first set to zero (count = 0). Subsequently, it is checked whether the counter reset signal is set to '1'. If the counter reset signal is not '1' and the pointer value is not '0', the counter value is increased by '1' and then the counter reset signal. Return to the process of checking that is '1'. On the other hand, if the counter reset signal value is '1', the signal power ready signal value is not '1', or the pointer value is '0', the control device sets the counter value to '0'. Return to the setting process.

17 is a flowchart showing in detail a process of sorting (or sorting) data stored in the memory.

First, the antenna control apparatus 109 inputs the number of data stored in the memory 105 to the Sr_lim variable (Sr_lim <= pointer-1). Then, the scan process of FIGS. 16A to C is checked (check sort_strob) and when the scan process is completed (Sort_strob = '1'), the data of the memory is read into the angle register and the power register of the direction controller 106. (Ang_reg, PW_reg <= memo_in). Subsequently, Sr_cnt_k values are input to Sr_cnt and Sr_max variables, respectively (Sr_cnt, Sr_max <= Sr_cnt_k), and Sr_max_reg for storing the maximum value among the stored data. Enter the angle and power register values in the variable (Sr_max_reg. <= Ang._reg., PW_reg.). Subsequently, a value of Sr_cnt_l is input to an Addr variable for generating an address of the memory (Addr <= Sr_cnt_1), and Sr_max_reg for storing the maximum value of the stored data. Compare the variable value with the power register value (check Sr_max_reg. <PW_reg.). Next, Sr_cnt_l value is input to the Sr_max variable (Sr_max <= Sr_cnt_l), and Sr_max_reg for storing the maximum value among the stored data. Enter the angle and power register values in the variable (Sr_max_reg. <= Ang._reg., PW_reg.). Subsequently, the Sr_cnt_l value is increased by '1' (Sr_cnt_l ++), and memory data corresponding to the address address corresponding to the Sr_cnt_l value is read into the angle and power registers (Ang._reg., PW_reg. <= Memo_in (Sr_cnt_l)). Then, after comparing the Sr_cnt_l value and the Sr_lim value (Sr_cnt_l = Sr_lim), the data of the memory corresponding to the Sr_cnt_k value is read into the angle and power registers (Ang._reg, PW_reg. <= Memo_in (Sr_cnt_k)). . Subsequently, the antenna control apparatus 109 stores the Sr_max_reg. Value in the memory 105 corresponding to the address of the Sr_cnt_k value. After storing the value (memo_out (Sr_cnt_k)), the memory 105 is made available for storage (memo_r_w = 1). Subsequently, the Sr_cnt_k value is increased by '1' (Sr_cnt_k ++), and then the Sr_cnt_k value and the Sr_lim_1 value are compared to check whether the alignment is completed (check Sr_cnt_k = Sr_lim_1). Each of the power register values is stored in the memory of the address address corresponding to the Sr_max value (memo_out (sr_max) <= Ang._reg., PW_reg.) To enable the storage of the memory 105 (memo_r_w = 1). The completion of the sorting process is notified to the scan processor 106-5 (sort_ack = 1).

18 is a flowchart illustrating a tracking process of the antenna control apparatus according to the present invention. First, the antenna controller 109 sets '1' to the tr_cnt variable through the tracking processor 106-4 (tr_cnt <= '0001') and then checks whether the sorting process is completed (check track_strob = 1 ). Then, the execution of the subprocess included in the tracking process is allowed (Enable = 1). Subsequently, it is checked whether the calculated signal-to-noise ratio is valid (SNR condition) and sequentially, the detected maximum ghost value and the detected signal power value are valid (GHOST power condition, Signal power condition). Subsequently, the tracking processing unit 106-4 of the antenna processing unit 109 checks whether all the data stored in the memory 105 has been used (tr_cnt = pointer) and then increases the tr_cnt value by '1' (tr_cnt ++). . Subsequently, a value of a memory address corresponding to the tr_cnt is input to the direction register of the direction controller 106 (dir_reg. <= Memo_in (tr_cnt)), and the end of the tracking process is terminated. 5) (track_ack = 1).

19 is a flowchart showing a sub process of the signal power tracking process.

First, the reliability counter is set to a value of '0' (confidence = 0), and then a signal power condition value indicating whether the detected signal power is valid is set to '1' (signal PW condition = 1). Subsequently, it is checked whether the subprocess of the signal power tracking process is allowed to be performed (enable = 1), and whether the signal power tracker 106-1 of FIG. 5 is ready to detect signal power (see FIG. 5). signal PW ready = 1). Then, the reliability value is checked by comparing the reliability value and the unlocking threshold value (Unlock_thd) (confidence = unlock_thd?). In addition, the reliability value is compared with the locking threshold value Lock_thd to confirm the reliability (confidence = lock_thd.?), And confirm whether the detected signal power is valid (signal PW <TOV). Subsequently, depending on whether the signal power is valid, the reliability value is decreased by '1' (confidence--) or the reliability value is increased by '1' (confidence ++). Finally, if the confidence value is equal to the unlocking threshold (confidence = unlock_thd), the signal power state value indicating whether the detected signal power value is valid is set to '0' (signal PW condition = 0).

20 is a flowchart illustrating a subprocess of the maximum ghost power tracking process according to the present invention.

First, the ghost power tracker 106-2 sets the timer counter to a value of '0' (count = 0), and then sets a ghost state value indicating whether the detected ghost power is valid to '1' (ghost PW condition = One). Then, it is checked whether the subprocess is allowed to be performed (enable = 1), and it is checked whether the timer counter reaches the try limit (try_lim) value (counter = try_lim). Then, after confirming that the maximum ghost power detector 116 of FIG. 10 is ready to detect the ghost power (ghost PW ready = 1), whether the maximum ghost power is maintained by a certain magnitude with respect to the main signal, that is, (Main signal <max ghost * 2). For example, in the present embodiment, the maximum ghost power is -3 dB with respect to the main signal. If it is not ready to detect the ghost power, increase the counter value by '1' (counter ++), and if the maximum ghost power is maintained by a predetermined magnitude with respect to a main signal, the ghost indicating whether the detected ghost power is valid Set the status to '0' (ghost PW condition = 0).

21 is a flowchart showing a sub process of the signal-to-noise ratio tracking process.

First, the reliability counter value is set to '0' (counter = 0) and the signal to noise ratio state value indicating whether the calculated signal to noise ratio is valid is set to '1' (signal PW condition = 1). Then, it is checked whether the sub-process is allowed (enable = 1), and whether the SNR calculator 104-3 is ready to detect the SNR (SNR ready = 1). In addition, it is checked whether the detected SNR is valid (SNR> = THD), and the reliability is checked by comparing the counter value with the unlocking threshold value (counter = unlock_thd). If there is no reliability, return to the initial process, and if the counter value is not equal to the try limit value try_lim, increase the counter value by '1' (counter ++) and then return to the step of confirming the permission of the subprocess. Goes. On the other hand, when the counter value is equal to the attempt limit value, the ghost state value indicating whether the detected SNR is valid is set to '0' (SNR condition = 0) and then the process returns to the initial stage of the subprocess. On the other hand, if it is not ready to detect the SNR, the process returns to checking whether the sub-process is allowed again.

Although the embodiment of the present invention uses a VSB receiver as an example, it can be applied to other wireless communication fields such as an OFDM receiver without departing from the scope of the present invention.

As described above, the antenna control apparatus according to the present invention has the following effects.

First, because channel information is obtained only from the receiving chip without using additional hardware to monitor the channel, the hardware is simplified and the manufacturing cost can be reduced.

Second, digital TV receivers have fast judgment and high reliability because they obtain channel information for the antenna control step by step from the automatic gain controller, the middle data segment synchronizer, and the equalizer and SNR calculator. The antenna of the receiver can be controlled.

Third, since it can operate independently of the digital television receiver, it can be compatible with other digital television receivers.

Fourth, since all control sections are digitally configured, they can be configured as a single chip, further increasing device integration.

Claims (22)

delete delete delete delete An antenna for receiving digital television broadcast channel signals and having a direction dependent upon the control signal; A tuner for tuning a desired channel signal among channel signals received through the antenna; An automatic gain controller for an intermediate frequency for automatically adjusting an intermediate frequency gain of the channel signal tuned from the tuner; A VSB receiving chip which takes a VSB signal from an output signal of the automatic gain control unit for the intermediate frequency and outputs the VSB signal; A detector for obtaining, from the VSB receiving chip, status signals including the power of the channel signal, the power of a ghost signal, and a signal-to-noise ratio as the status signal of this output signal; A memory for updating and storing the new state signal and the previously detected state signals; A direction controller obtaining a control signal for controlling the direction of the antenna by comparing new state signals from the detection unit with previous state signals stored in the memory; And And an interface unit connected between the antenna and the direction controller and providing the control signal to the antenna such that the direction of the antenna is controlled in accordance with the control signal. delete delete 6. The apparatus of claim 5, wherein the VSB receiving chip comprises: an automatic gain control unit for automatically controlling a gain of an output signal of the intermediate frequency automatic gain control unit again; A timing and carrier recovery unit for recovering timing and carrier loss on the output signal of the automatic gain control unit; An equalizer for equalizing the timing and output signals of the carrier recovery unit; A phase tracker for tracking the phase of the output signal of the equalizer; And And a forward error corrector for correcting the forward error on the output signal of the phase tracker and outputting the VSB signal. 9. The apparatus of claim 8, wherein the detection unit comprises: a signal power detector for detecting power of the tuned channel signal using an automatic gain control signal from the automatic gain control unit of the VSB receiving chip; A ghost power detector for detecting power of a ghost signal using the timing signal of the VSB receiving chip and an output signal of a carrier recovery unit or an output signal of the equalizer; And And a signal-to-noise ratio (SNR) calculator for calculating a signal-to-noise ratio using the output signal of the phase tracker of the VSB receiving chip. 10. The apparatus of claim 9, wherein the ghost power detector includes a received I-channel signal from the VSB receiving chip and a preset synchronization signal value (for reference, a synchronization signal value of "1001" is inserted into each data segment in the VSB transmission method). A data segment synchronous correlator for computing a correlation value with. A segment integrator that accumulates the output value of the data segment sync correlator in 832 delayers; A slicer providing an increased count value when the accumulated correlation value reaches a predetermined size; A reliability counter for increasing a count number according to the increased count value; And And a maximum ghost power detection controller that sends a normalized value of the ghost power ready signal and the maximum ghost power to the power of the received channel signal to the direction controller when the value of the reliability counter reaches a reference value. receiving set. 11. The digital television receiver as claimed in claim 10, wherein in the VSB transmission scheme, a synchronization signal inserted in each data segment is " 1001 ". 10. The apparatus of claim 9, wherein the signal-to-noise ratio calculator comprises: a subtractor for subtracting the demodulated signal constellation from the decision signal constellation; A squarer that squares the output of the subtractor; An accumulator for accumulating output signals of the squarer; A latch for delaying the output of the accumulator; And And a divider for dividing the output of the latch by the window size of the segment integrator of the ghost signal power detector to output the signal-to-noise ratio. 13. The method of claim 12, wherein the signal to noise ratio is determined by the following algorithms, Signal-to-noise ratio (SNR) = 10 log (Ps / Pn), Pn | mse = sigma (k is from 1 to n) (mse / m), mse = (D_l-R_l) squared, where Ps is Digital signal receiver (1), Pn is noise power, R_1 is demodulated signal constellation, D_1 is determined signal constellation, and m indicates window size of integrator. The method of claim 8, wherein the automatic gain control (AGC) scheme of the tuned channel signal controls the gain of the intermediate frequency signal through the charge pump and the lag filter in the VSB receiving chip, and the gain of the high frequency signal is the intermediate frequency automatic. And controlled using a delayed automatic gain control signal from a gain control section. The digital television receiver as claimed in claim 8, wherein the gain of the intermediate frequency signal and the high frequency signal are automatically controlled by the VSB receiving chip according to the automatic gain control method of the tuned channel signal. 6. The apparatus of claim 5, wherein the direction controller comprises: a signal power tracker for tracking the power of the tuned channel signal using the power of the channel signal from the detector; A ghost power tracker for tracking the power of the ghost signal using the power of the ghost signal; And A signal-to-noise ratio (SNR) tracker for tracking the signal-to-noise ratio using the signal-to-noise ratio; Track the states of the tuned channel signal using the output signals of the trackers in the currently selected antenna pattern, and if the tracked states do not maintain a value of valid magnitude, the antenna pattern in order of the antenna pattern previously stored in the memory. A tracking processor to change the number of times; A scan processor for changing the directionality of the antenna using the output signal of the tracking processor to obtain an effective signal power and antenna pattern and to store the obtained power and pattern values in the memory; And And a sort processor for aligning the stored antenna pattern values in the order of the signal power values. 17. The digital television receiver as claimed in claim 16, wherein the direction controller causes the scan processor to perform the scanning process again when it is determined by the operation of the tracking processor that there is no antenna pattern having a valid size in the memory. . 17. The apparatus of claim 16, wherein the direction controller is a general purpose register, a pointer register indicating an address of the memory, a direction register (Dir_reg.) Which always stores a current antenna state value, and temporarily storing a state value of the antenna. An angle register, and a power register for temporarily storing a power value of the received channel signal. A digital television receiver having a directional antenna, an antenna controller and a memory, (a) rotating the antenna, storing the active power of the channel signal received through the antenna along with their antenna pattern in the memory and taking the antenna pattern when the maximum signal power is detected; (b) aligning the stored antenna patterns in order of magnitude of the signal powers; (c) detecting states of the tuned channel signal, power of the channel signal, maximum ghost power, and signal to noise ratio in a currently selected antenna pattern; (d) determining whether the detected values maintain a valid magnitude; And and (e) changing the antenna pattern in the order of the aligned and stored antenna patterns when a change of the current antenna pattern is required as a result of the determination. 20. The method of claim 19, wherein step (a) comprises: initializing the antenna control device and detecting whether a channel signal exists through the antenna; If the channel signal is detected, rotating the directivity of the antenna to a predetermined angle and storing active power of the detected channel signal in the memory along with the antenna pattern at that time; And And selecting the antenna pattern as the best pattern when the maximum signal power is detected. 21. The antenna control method according to claim 20, wherein the predetermined angle is 360 degrees. 20. The method of claim 19, wherein step (e) If none of all antenna patterns stored in the memory is valid, the method of controlling the antenna of the digital television receiver further comprises the step of performing step (a) again using the antenna control apparatus to obtain a valid antenna pattern. .