KR100350378B1 - Apparatus and method for interface between BMPA and HLDA of micro base station transciever of mobile communication system - Google Patents

Abstract

The present invention creates a communication path between the processor of the BMPA and the processor of the HLDA-B1, so that the processor of the BMPA can monitor the status of the processor performing the software arbitration function in the HLDA, so that the BMPA may fail when the processor of the HLDA is in operation. The present invention relates to an interface device between BMP and HDL in a micro base station of a mobile communication system capable of recovering a fault state, and a control method thereof. A first third state buffer for outputting a BMPA_DA signal by a BMPA_BUF_CON signal and the BMPA_BUF_CON. It is connected to the second third state buffer for outputting the HLDA_DA signal input by the signal, and the output terminal of the first third state buffer and the second third state buffer, and the output signal is input signal D, and the reset signal is reset. The clear (CL) signal is used, the WR_EN signal is the clock (CLK) signal, and Vcc is the driving power supply (PR) signal. A third flip-flop for outputting the input signal D as a Q signal or a Q 'signal, and a third third buffer for outputting the Q signal input by the BMPA_BUF_CON' signal and a Q signal input by the BMPA_BUF_CON signal; 4 consists of a register consisting of a 3-state buffer.

Description

Apparatus and method for interface between BMPA and HLDA of micro base station transciever of mobile communication system in micro base station of mobile communication system

The present invention relates to a micro base station of a mobile communication system, and more particularly, to a BMPA using an interface bus between a BMPA, a main control board of a micro base station (BTS), and an HLDA-B1 performing an E1 / T1 / V35 matching function. By creating a communication path between the processor and the HLDA-B1's processor, the BMPA's processor can monitor the status of a processor that performs software arbitration within the HLDA-B1. The present invention relates to an interface device between BMP and HDL in a micro base station of a mobile communication system capable of recovery.

In general, a base station of a mobile communication system is composed of a switching system and a cell (CELL) equipment. This includes many of the unit functional units that make up the system, and these units are implemented with various types of equipment.

The core of such a mobile communication base station is a digital shelf carrying a channel card, a sector interface card, an analog common card, and a Jordan card. The transceiver itself converts an intermediate frequency signal (hereinafter referred to as IF) output from the digital self into UHF and down-converts the received UHF into IF.

In addition, the transceiver itself includes a sector access card which combines baseband forward signals received from the channel card and converts them up to IF signals. Such a sector access card receives a combined baseband transmission signal from an analog common card, combines and amplifies them. The combined signal is passed through the low pass filter (LPF) and combined with the IF signal, i.e., the 0 ° and 90 ° delay signals of 4.95 MHz, into the RF rack as an IF signal of 4.95 MHz through the band pass filter (BPF). Send. Therefore, the RF rack is to be converted to the 4.95MHz IF signal received for signal transmission through the antenna.

1 is a configuration diagram of a base station of a general mobile communication system. As shown therein, a Radio Frequency Unit (RFU) is a part of a base station, and a CDMA Modulator and Demodulator Block (CMDB). A wireless connection is performed between the 130 and the mobile station in the forward and reverse links, and is performed in conjunction with a BTS control processor (BCP). : HPAB (hereinafter referred to as HPAB) 20, an antenna front end block (AFEB, AFEB) 10, and a BS Test Unit Block (BTUB, hereinafter BTUB), and the XCVB ( 30 is composed of a transceiver unit (XCUV, hereinafter referred to as XCVU) 32 and a transceiver master control unit (XMCU, hereinafter referred to as XMCU) 34, and the CMDB 100 is a sector access card (Sector). interface Card Assembly (SICA) Clock and automatic gain control bank (CABA) (110), CDMA Channel Element board Assembly (CCEA, CCEA) (130) and control and transmission board (Control) And Transmit board Assembly: CATA (hereinafter referred to as CATA) 140.

In addition, the micro base station is composed of a main controller board BMPA (not shown) and HLDA (not shown) to perform the E1 / T1 / V35 matching function.

2 is a block diagram illustrating an interface device between BMPA and HLDA in a micro base station of a mobile communication system according to the related art.

As shown in FIG. 2, the HLDA processor is connected to the HLDA processor 200 and the I / O pins of the HLDA processor 200 to output address, data, and read / write control signals. Programmable Logic Device (PLD) 300 that receives and outputs the address, data, and read / write control signals output from 200 and receives the address, data, and read / write control signals output from the PLD 300. A HLDA 500 comprising an E1 / T1 matching device 400 and a BMPA connected to an I / O pin of the PLD 300 and outputting address, data and read / write control signals to the PLD 300. It consists of a BMPA 700 which consists of an interrupt bus 600.

As shown in the configuration, the BMPA 700 passes through the PLD 300 to access the E1 / T1 matching device 400 in the HLDA-B1 board 500 and the registers configured inside the PLD 300.

Here, the data interface between the BMPA 700 and the HLDA 500 has a signal flow shown in FIG. 3.

In addition, since 1-byte data transmission and reception between the HLDA 500 and the BMPA 700 is possible, and 8 bits generate 2 ⁸ (256), the BMPA 700 is related to 256 states of the HLDA 500 processor. Information may be requested, and HLDA 500 may likewise report 256 related information to BMPA 700.

However, since the BMPA and the HLDA processor are connected to only the I / O pins, there is a problem in that no path is formed between the HLDA and the BMPA processors.

In other words, the BMPA provides direct access to devices in the HLDA-B1 via the interface bus between the BMPA and HLDA, providing software arbitration to provide daisy chain mode within the HLDA. There was a problem that the BMPA cannot monitor the state of the HLDA processor because it cannot communicate with the processor.

Therefore, there is a problem that can not be recovered at the system level when a failure of the HLDA processor in operation.

Accordingly, an object of the present invention is to connect an 8-bit register to an interface bus between BMPA and HLDA and a processor bus within HLDA. It is designed to be accessible in both directions, uses I / O pins between the processor in the BMPA and the HLDA processor, and detects by polling the signal input to each pin and uses the defined algorithm. Interface device between BMP and HDL in micro base station of mobile communication system that each processor can read and write information recorded in register so that each processor can use this data if necessary to communicate In providing.

A feature of an interface device between BMP and HDL in a micro base station of a mobile communication system according to the present invention for achieving the above object is a first third state buffer for outputting a BMPA_DA signal by a BMPA_BUF_CON signal and the BMPA_BUF_CON signal. Connected to an output terminal of the second third state buffer and the first third state buffer and the second third state buffer which output the HLDA_DA signal inputted by the second signal; the output signal is the input signal D, and the reset signal is cleared. (CL) signal, the WR_EN signal as the clock (CLK) signal, and Vcc as the driving power supply (PR) signal to the D flip-flop and the BMPA_BUF_CON 'signal, which outputs the input signal D as a Q signal or a Q' signal. And a register comprising a third third state buffer for outputting the Q signal input by the fourth third state buffer for outputting the Q signal input by the BMPA_BUF_CON signal. .

In addition, in the micro base station of the mobile communication system according to the present invention for achieving the above object, a feature of the interface control method between the BMP and HDL is, in the interface control method between the processor of the BMPA and the processor of the HLDA, BMPA sends a signal to the HLDA processor for data transmission, writes data to be sent to a register, BMPA sends a signal to the HLDA processor to notify the end of data transmission, and HLDA sends data. Waiting until the end signal is acknowledged and when the end signal is recognized, the BMPA determines that the data has been written, reads the register, receives the data sent by the BMPA, and informs the BMPA that the data has been successfully received. Waiting for a certain time until a signal is inputted; BMPA determines whether or not a normal transmission signal has been transmitted. If the normal transmission signal is transmitted, the BMPA recognizes that the normal transmission has been completed and ends the data transmission operation. If the normal transmission signal has not been transmitted, the BMPA receives a message from the HLDA. If there is no response from HLDA during this time, it repeats the data transmission operation up to 3 times, and if there is no response, the HLDA board initialization operation is performed considering that the HLDA processor has an error. It is done by

1 is a configuration diagram of a base station of a general mobile communication system;

2 is a block diagram showing an interface device between BMPA and HLDA in a micro base station of a mobile communication system according to the prior art;

3 is a flowchart between I / O pins at an interface between BMPA and HLDA in a micro base station of a mobile communication system according to the prior art;

4 is a detailed circuit diagram illustrating an interface device between BMPA and HLDA in a micro base station of a mobile communication system according to the present invention;

5 is a flowchart of a first embodiment in which data between BMPA and HLDA is interfaced in a micro base station of a mobile communication system according to the present invention;

6 is a flowchart of a second embodiment in which data between a BMPA and an HLDA is interfaced in a micro base station of a mobile communication system according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200: HLDA processor, 300: PLD,

400: E1 / T1 matching device, 500: HLDA,

600: BMPA interface bus, 700: BMPA.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the interface device between the BMP and HDL in the micro base station of the mobile communication system according to the present invention and a control method thereof are as follows.

4 is a detailed circuit diagram illustrating an interface device between BMPA and HLDA in a micro base station of a mobile communication system according to the present invention.

As shown in FIG. 4, the internal circuit of the PLD for the interface between the processor of the BMPA and the processor of the HLDA includes a first third state buffer 800 which outputs a BMPA_DA0 signal by the BMPA_BUF_CON signal and an HLDA_DA0 input by the BMPA_BUF_CON signal. It is connected to an output terminal of the second third state buffer 802 and the first third state buffer 800 and the second third state buffer 802 for outputting a signal, and the output signal is set as an input signal D and reset. ) First D flip that outputs the input signal D as a Q signal or a Q 'signal with the clear signal as the CL signal, the WR_EN signal as the clock CLK signal, and Vcc as the driving power source PR signal. A third third state buffer 806 for outputting a Q signal input by the flop 804 and the BMPA_BUF_CON 'signal and a fourth third state buffer 808 for outputting the Q signal input by the BMPA_BUF_CON signal 1 register 810 and the BMPA_BUF_CON signal. The fifth third state buffer 812 that outputs the BMPA_DA1 signal, the sixth third state buffer 814 that outputs the HLDA_DA1 signal input by the BMPA_BUF_CON signal, and the fifth third state buffer 812 and the sixth third state. It is connected to the output terminal of the buffer 814, and its output signal is the input signal D, the RESET signal is the clear signal, the WR_EN signal is the clock signal CLK, and Vcc is the driving power supply PR. A second D flip-flop 816 for outputting the input signal D as a Q signal or a Q 'signal and a seventh third state buffer 818 for outputting a Q signal input by the BMPA_BUF_CON' signal as a signal; A second register 822 comprising an eighth third state buffer 820 that outputs a Q signal input by the BMPA_BUF_CON signal, a ninth third state buffer 824 that outputs a BMPA_DA2 signal by the BMPA_BUF_CON signal, and the BMPA_BUF_CON A thirteenth outputting the HLDA_DA2 signal input by the signal It is connected to the output buffer of the data buffer 826, the ninth third state buffer 824 and the tenth third state buffer 826, and the output signal is input signal D, and the reset signal is cleared. The third D flip-flop 828 and the BMPA_BUF_CON 'outputting the input signal D as a Q signal or a Q' signal using the WR_EN signal as the clock CLK signal and Vcc as the drive power signal PR. A third register 834 comprising an eleventh third state buffer 830 for outputting a Q signal input by the signal and a twelfth third state buffer 832 for outputting a Q signal input by the BMPA_BUF_CON signal; A thirteenth state buffer 836 that outputs the BMPA_DA3 signal by the BMPA_BUF_CON signal, a thirteenth state buffer 838 that outputs the HLDA_DA3 signal input by the BMPA_BUF_CON signal, and the thirteenth state buffer 836 and the third 14 is connected to the output of the three-state buffer 826 and inputs the output signal. The input signal D is a Q signal or a Q signal by setting the signal D, the reset signal is a clear signal, the WR_EN signal is a clock CLK signal, and Vcc is a driving power source PR signal. A sixteenth state buffer 842 for outputting a Q signal input by the fourth D flip-flop 828 and a BMPA_BUF_CON signal output as a signal, and a third signal for outputting a Q signal input by the BMPA_BUF_CON signal Fourth register 846 comprising a state buffer 844, a seventeenth state buffer 848 for outputting the BMPA_DA4 signal by the BMPA_BUF_CON signal, and an eighteenth third state for outputting the HLDA_DA4 signal input by the BMPA_BUF_CON signal It is connected to an output terminal of the buffer 850 and the seventeenth state buffer 848 and the eighteenth state buffer 850, and the output signal thereof is an input signal D, and the reset signal is cleared. WR_EN signal to CLK signal and Vcc to drive power signal For example, a fifth D flip-flop 852 outputting the input signal D as a Q signal or a Q 'signal and a 19 th 3 state buffer 854 for outputting a Q signal input by the BMPA_BUF_CON' signal and the BMPA_BUF_CON signal To the fifth register 858 including the twentieth three-state buffer 856 for outputting the Q signal inputted by the second signal, and the twenty-third state buffer 860 for outputting the BMPA_DA5 signal by the BMPA_BUF_CON signal and the BMPA_BUF_CON signal It is connected to the output terminal of the 22nd 3rd state buffer 862 and the 21st 3rd state buffer 860 and the 22nd 3rd state buffer 862 to output the HLDA_DA5 signal inputted by the input signal (D). And the RESET signal as the clear signal, the WR_EN signal as the clock signal, and the Vcc as the driving power signal to output the input signal D as a Q signal or a Q 'signal. Q signal inputted by the sixth D flip-flop 864 and the BMPA_BUF_CON 'signal Outputs the BMPA_DA6 signal by the sixth register 870 including the twenty-third state buffer 866 to be output, the twenty-fourth state buffer 868 to output the Q signal input by the BMPA_BUF_CON signal, and the BMPA_BUF_CON signal Of the twenty-sixth state buffer 872 and the twenty-sixth state buffer 874 that outputs the HLDA_DA6 signal inputted by the BMPA_BUF_CON signal, and the twenty-sixth state buffer 872 and the 26th state buffer 874. The output signal is connected to the output terminal as the input signal (D), the reset signal as the clear signal (CL), the WR_EN signal as the clock (CLK) signal, and Vcc as the drive power (PR) signal. Input by the seventh D flip-flop 876 for outputting the signal D as the Q signal or the Q 'signal and the 27 th state buffer 878 for outputting the Q signal input by the BMPA_BUF_CON' signal and the BMPA_BUF_CON signal 28th state buffer 880 for outputting Q signal The seventh register 882 configured, the thirty-third state buffer 884 for outputting the BMPA_DA7 signal by the BMPA_BUF_CON signal, and the thirty third state buffer 886 for outputting the HLDA_DA7 signal input by the BMPA_BUF_CON signal; It is connected to the output terminal of the 29th 3rd state buffer 884 and the 30th 3rd state buffer 886, and its output signal is the input signal D, the RESET signal is the clear signal, and the WR_EN signal is clocked. Q signal inputted by the eighth D flip-flop 888 and the BMPA_BUF_CON 'signal outputting the input signal D as a Q signal or a Q' signal using the signal CLK and Vcc as the driving power supply PR signal. The eighth register 894 includes a thirty-three third state buffer 890 for outputting a second signal and a thirty-second third state buffer 892 for outputting a Q signal inputted by the BMPA_BUF_CON signal.

In the micro base station of the mobile communication system according to the present invention configured as described above, the interface device between the BMPA and the HLDA is a register 810, 822, 834, 846 (846) when the BMPA 700 passes the data to the HLDA 500. Two buffers 800, 802, 812, 814, 824, 826, 836, 838, 848, 850, 860, 862, 872 connected to the inputs of 858, 870, 882, 894. 874, 884, 886 connected to the BMPA 700 is turned on, the buffer of the HLDA 500 is turned off, and the output is controlled by the buffer as opposed to the input.

On the contrary, when the HLDA 500 passes data to the BMPA 700, the buffers 800 and 802 of the inputs of the registers 810, 822, 834, 846, 858, 870, 882 and 894 ( 812, 814 (824, 826) (836, 838) (848, 850) (860, 862) (872, 874) (884, 886) turn on the HLDA 500, and the output buffer is BMPA (700). ) Buffer is turned on.

This buffer control operation is made of I / O port (BMPA_BUF_CON, High active signal) provided by the interface part of BMPA. As a result, the main control word of the register is performed by BMPA.

Therefore, two I / O ports and processing through polling for these ports are required for communication between the HLDA and the BMPA processors.

In other words, the BMPA is a signal input to the processor of the BMPA to transmit data to the HLDA.

5 is a flowchart of a first embodiment in which data between a BMPA and an HLDA is interfaced in a micro base station of a mobile communication system according to the present invention.

5 illustrates a case in which data is interfaced from BMPA to HLDA. First, the BMPA 700 sends a signal informing of data transmission to the processor of the HLDA 500 (S101) and writes data to be transmitted to a register (S101). S103).

Subsequently, the BMPA sends a signal indicating the end of data transmission back to the processor of the HLDA (S105).

The HLDA waits until it recognizes that the data transmission end signal is received, and when the data transmission end signal is recognized (S107) (S109), it is determined that BMPA has written data, reads a register, and transmits the BMPA. The data is received and waits for a predetermined time until a signal indicating that the data is normally received in the BMPA is input (S111) (S113) (S115).

Subsequently, the BMPA determines whether or not a normal transmission signal is transmitted (S117). If the normal transmission signal is transmitted, the BMPA recognizes that the normal transmission is completed and ends the data transmission operation.

If the normal transmission signal is not transmitted as a result of the determination of S117, the BMPA waits for a predetermined time from the signal from the HLDA. If there is no response from the HLDA during this time, the BMPA repeats the data transmission operation up to three times and responds as well. If not, it is assumed that an abnormality has occurred in the processor of the HLDA and the HLDA board initialization operation is performed (S119) (S121).

6 is a flowchart of a second embodiment in which data between BMPA and HLDA is interfaced in a mobile communication micro base station according to the present invention.

FIG. 6 illustrates a case where data is interfaced from HLDA-B1 to BMPA. First, HLDA generates a signal informing transmission of data to BMPA (S201).

Subsequently, upon recognizing the data transmission signal from the HLDA, the BMPA changes the control of the register buffer set in the direction in which the data is transmitted by itself, and controls the register buffer set in the direction in which the data is received (S203) (S205).

Then, a data transmission possible signal is sent to HLDA (S207).

Thereafter, the HLDA waits for a data transmission possible signal from the BMPA and writes data to the register when the signal is recognized (S209) (S211).

Subsequently, a signal informing that the data transmission is finished is again generated to the BMPA (S213) and waits until the data reception end signal is input from the BMPA (S215).

Recognizing that the data transmission is completed from the HLDA, the data is read from the register and a signal indicating the end of data reception is generated to the HLDA (S217) (S219).

Subsequently, the register buffer is controlled in a mode in which the register buffer is transmitted (S221).

Therefore, the data transmission operation is terminated after recognizing the data reception end signal from the BMPA.

As described above, in the present invention, the BMPA can cope with a failure in the event of a failure through the state monitor of the processor performing the software arbitration function in the HLDA-B1 performing the link matching function with the control station, thereby reducing the maintenance cost. There is.

In particular, when multiple processors are applied to the system, the main processor manages the state of the coprocessor, thereby enabling stable system operation.

Claims (3)

In the interface device between the processor of the BMPA and the processor of the HLDA, A first third state buffer 800 for outputting the BMPA_DA0 signal by the BMPA_BUF_CON signal, a second third state buffer 802 for outputting the HLDA_DA0 signal input by the BMPA_BUF_CON signal, and the first third state buffer 800 and the first It is connected to the output terminal of the 3 state buffer 802, and its output signal is the input signal (D), the RESET signal is the clear signal (CL), the WR_EN signal is the clock signal (CLK), and Vcc is the driving power supply. A first D flip-flop 804 for outputting the input signal D as a Q signal or a Q 'signal as a (PR) signal and a third third state buffer 806 for outputting a Q signal input by the BMPA_BUF_CON' signal. ) And a first register 810 including a fourth third state buffer 808 for outputting a Q signal input by the BMPA_BUF_CON signal, A fifth third state buffer 812 for outputting the BMPA_DA1 signal by the BMPA_BUF_CON signal, a sixth third state buffer 814 for outputting the HLDA_DA1 signal input by the BMPA_BUF_CON signal, and the fifth third state buffer 812 and the fifth 6 Connected to the output of the state buffer 814, the output signal is the input signal (D), the reset signal is the clear signal (CL), the WR_EN signal is the clock (CLK) signal, and Vcc is the driving power supply. A second D flip-flop 816 outputting the input signal D as a Q signal or a Q 'signal as a PR signal, and a seventh third state buffer 818 for outputting a Q signal input by the BMPA_BUF_CON' signal. ) And a second register 822 comprising an eighth third state buffer 820 for outputting a Q signal input by the BMPA_BUF_CON signal, A ninth third state buffer 824 for outputting the BMPA_DA2 signal by the BMPA_BUF_CON signal, a tenth third state buffer 826 for outputting the HLDA_DA2 signal input by the BMPA_BUF_CON signal, and the ninth third state buffer 824 and the ninth state buffer 824; It is connected to the output terminal of the three-state buffer 826, and its output signal is the input signal (D), the RESET signal is the clear signal (CL), the WR_EN signal is the clock (CLK) signal, and Vcc is the driving power supply. A third D flip-flop 828 outputting the input signal D as a Q signal or a Q 'signal as a PR signal, and an eleventh third state buffer 830 for outputting a Q signal input by the BMPA_BUF_CON' signal. ) And a third register 834 comprising a twelfth third state buffer 832 for outputting a Q signal input by the BMPA_BUF_CON signal, A thirteenth state buffer 836 that outputs the BMPA_DA3 signal by the BMPA_BUF_CON signal, a thirteenth state buffer 838 that outputs the HLDA_DA3 signal input by the BMPA_BUF_CON signal, and the thirteenth state buffer 836 and the third It is connected to the output terminal of the three-state buffer 826, and its output signal is the input signal D, the RESET signal is the clear signal, the WR_EN signal is the clock signal, and Vcc is the driving power supply. A fourth D flip-flop 828 outputting the input signal D as a Q signal or a Q 'signal and a 15 th third state buffer 842 for outputting a Q signal input by the BMPA_BUF_CON' signal as a (PR) signal ) And a fourth register 846 comprising a sixteenth third state buffer 844 for outputting a Q signal input by the BMPA_BUF_CON signal, A seventeenth state buffer 848 that outputs the BMPA_DA4 signal by the BMPA_BUF_CON signal, and an eighteenth state buffer 850 that outputs the HLDA_DA4 signal input by the BMPA_BUF_CON signal, and the seventeenth state buffer 848 and the seventh state buffer 848. It is connected to the output terminal of the three-state buffer 850, and its output signal is the input signal (D), the reset signal is the clear signal (CL), the WR_EN signal is the clock signal (CLK), and Vcc is the driving power supply. A fifth D flip-flop 852 for outputting the input signal D as a Q signal or a Q 'signal as a signal (PR) and a 19th third state buffer 854 for outputting a Q signal input by the BMPA_BUF_CON' signal ) And a fifth register 858 comprising a twentieth third state buffer 856 for outputting a Q signal input by the BMPA_BUF_CON signal, Twenty-first three-state buffer 860 for outputting BMPA_DA5 signal by BMPA_BUF_CON signal, twenty-second three-state buffer 862 for outputting HLDA_DA5 signal input by the BMPA_BUF_CON signal, and twenty-first three state buffer 860 It is connected to the output terminal of the 3-state buffer 862, and its output signal is the input signal (D), the RESET signal is the clear signal (CL), the WR_EN signal is the clock signal (CLK), and Vcc is the driving power supply. A sixth D flip-flop 864 for outputting the input signal D as a Q signal or a Q 'signal and a 23rd third state buffer 866 for outputting a Q signal input by the BMPA_BUF_CON' signal as a (PR) signal ) And a sixth register 870 comprising a twenty-fourth state buffer 868 for outputting a Q signal input by the BMPA_BUF_CON signal, A twenty-fifth state buffer 872 that outputs a BMPA_DA6 signal by a BMPA_BUF_CON signal, a twenty-sixth state buffer 874 that outputs a HLDA_DA6 signal input by the BMPA_BUF_CON signal, and a twenty-fifth state buffer 872 and a second It is connected to the output terminal of the three-state buffer 874, and its output signal is the input signal (D), the RESET signal is the clear (CL) signal, the WR_EN signal is the clock (CLK) signal, and Vcc is the driving power supply. A seventh D flip-flop 876 for outputting the input signal D as a Q signal or a Q 'signal and a Q27 third state buffer 878 for outputting a Q signal inputted by a BMPA_BUF_CON' signal as a (PR) signal ) And a seventh register 882 including a 28 th third state buffer 880 for outputting a Q signal input by the BMPA_BUF_CON signal, Thirty-third state buffer 884 for outputting BMPA_DA7 signal by BMPA_BUF_CON signal and thirty-third state buffer 886 for outputting HLDA_DA7 signal input by the BMPA_BUF_CON signal It is connected to the output terminal of the three-state buffer 886, and its output signal is the input signal (D), the RESET signal is the clear signal (CL), the WR_EN signal is the clock signal (CLK), and Vcc is driven. An eighth D flip-flop 888 which outputs the input signal D as a Q signal or a Q 'signal as a signal (PR) and a thirty-third state buffer 890 which outputs a Q signal inputted by a BMPA_BUF_CON' signal And an eighth register 894 including a thirty-second third state buffer 892 for outputting a Q signal input by the BMPA_BUF_CON signal. Eagan Interpe Scotland device. In the interface control method between the processor of the BMPA and the processor of the HLDA, Sending, by the BMPA, a signal for notifying data transmission to a processor of HLDA, writing data to be transmitted to a register; The BMPA sending a signal to the processor of HLDA again indicating the end of data transmission; Waiting until the HLDA recognizes whether the data transmission end signal is received, and when the data transmission end signal is recognized, it is determined that the BMPA has written the data, reads the register, receives the data transmitted by the BMPA, and normally receives the data from the BMPA. Waiting for a predetermined time until a signal indicating that data has been received; Determining whether a normal transmission signal has been transmitted by the BMPA and recognizing that the normal transmission has been completed, if the normal transmission signal has been transmitted; If the normal transmission signal is not transmitted, the BMPA waits for the signal from the HLDA for a certain time. If there is no response from the HLDA during this time, the data transmission operation is repeated up to three times. And performing an HLDA board initialization operation in response to the abnormality occurring in the micro base station of the mobile communication system. In the interface control method between the processor of the BMPA and the processor of the HLDA, The HLDA generating a signal informing transmission of data to a BMPA; If the BMPA recognizes the data transmission signal from the HLDA, changing the control of the register buffer set in the direction in which the BMPA transmits data, and controlling the register buffer set in the direction in which the data is received; When the BMPA sends a data transmission capable signal to the HLDA, waits for a data transmission possible signal from the BMPA, and writes data into a register when the signal is recognized; Generating a signal informing that the data transmission is finished to the BMPA and waiting until the data reception termination signal is input from the BMPA; Recognizing that data transmission is finished from the HLDA, reading data from a register and generating a signal to the HLDA indicating completion of data reception; And controlling the register buffer to a mode in which the register buffer is transmitted. The method of controlling the interface between the BMP and the HLA in the micro base station of the mobile communication system.