KR100307495B1 - Asynchronous transfer mode having no.7 signal mode - Google Patents

Abstract

The present invention relates to an ATM switch that accommodates NO.7 signaling, comprising: a CEIA for changing a NO.7 message to an asynchronous transmission mode adaptation layer type cell; FMDA for multiplexing the NO.7 messages received from the CEIA to the switches in the exchange and demultiplexing the NO.7 messages received from the switches; A STIA for converting the demultiplexed NO.7 message into a NO.7 level 2 protocol, writing to the first dual port RAM, and generating an interrupt signal indicating that the NO.7 message is stored in the first dual port RAM; An AMPA that detects an interrupt signal from the STIA, writes it to the second dual port RAM, and generates an interrupt signal indicating that the NO.7 message is stored; A CMDA is provided that connects NO.7 messages between AMPA and the switch. Therefore, the new NO.7 hardware device can be easily accommodated to provide the NO.7 signaling system, and the NO.7 hardware device can be easily implemented due to the small development cost.

Description

Asynchronous transfer mode exchanger accepting NO.7 signaling system {ASYNCHRONOUS TRANSFER MODE HAVING NO.7 SIGNAL MODE}

The present invention relates to an Asynchronous Transfer Mode (hereinafter, simply referred to as ATM) exchange, and more particularly to a NO.7 signaling scheme that accommodates the NO.7 signaling scheme in an ATM exchanger to provide various communication services. To an ATM exchange.

In general, the ATM switching system is a communication method supporting a broadband information communication network, and can communicate by integrating multimedia such as voice and video, and is a packet switching method for improving data efficiency and circuit switching method for transmitting data in real time. It is a system that has all the advantages of an exchange method, and transmits ATM information to another exchange system using a high speed interface.

Since the ATM transmission in the ATM switching system is one of the data transmission schemes, the starting point of each character or each block is arbitrary, but once the transmission is started, the generation point of each signal representing the transmission character or the bit in the block is fixed. Send ATM data in the same way as time frames.

In the ATM data transmission method, each character is framed and transmitted by a bit (or pulse). When the start bit triggers a timing mechanism of the receiving terminal, the bit received from the transmitting terminal is subsequently timed. When counting with the stop bit and receiving the stop bit, the timing mechanism of the receiving end is stopped.

As shown in FIG. 1, a conventional ATM switch includes a circuit emulator interface board assembly (hereinafter referred to as CEIA) (10-1, 10-2, 10-3), and frame multi / inverse. Frame Multiplex / Demultiplex Board Assembly (hereinafter referred to as FMDA) (13-1, 13-2, 13-3), ATM Switch 15, Cell Multiplex / Demultiplex Assembly Board (Cell Multiplex / A demultiplex board assembly (hereinafter abbreviated as CMDA) 17 and an asynchronous transmission mode main processor assembly board (hereinafter referred to as AMPA) 19 are provided.

CEIA (10-1, 10-2, 10-3) receives NO.7 messages transmitted through a number of E1 interfaces (currently 8 Port / Printed Circuit Board Assembly (PBA)). 10-1, 10-2, and 10-3) can handle each channel, thus changing the NO.7 message to ATM Adaptation Layer (hereinafter, abbreviated as AAL) type 1 cell. After attaching a tag to the changed ALL1 type NO.7 message header, the tag is transmitted to the FMDA 13-1, 13-2, 13-3. As a delimiter for distinguishing an E1 line, the delimiter information is provided from an application software block.

FMDA 13-1, 13-2, 13-3 multiplexes / demultiplexes NO1 message of type ALL1 received from CEIA 10-1, 10-2, 10-3 or ATM switch 15 As a block (multiplex / demultiplex), the FMDA 13-1 multiplexes the NO.7 message of the ALL1 type received from the CEIA 10-1 and sends it to the ATM switch 15. In addition, the FMDAs 13-2 and 13-3 demultiplex the multiplexed NO.7 messages received from the ATM switch 15 and transmit them to the CEIA 10-2 and 10-3. Here, the FMDA connects a plurality of CEIAs (currently eight), and the ATM switch 15 is connected to the 155M switch 1 port using an internal module interface (hereinafter referred to as IMI) (B).

The ATM switch 15 switches to transmit the NO.7 message received from the FMDA 13-1 to the FMDAs 13-2 and 13-3.

The CMDA 17 interfaces to match between the AMPA 19 and the ATM switch 15, and interfaces to transmit a ring signal provided from the AMPA 19, that is, a ring signal according to state management, to the ATM switch 15. As a block, it performs 1: 8 cell multiplexing / demultiplexing, extending the IMI (B) port for eight processors, and extends the 155Mbps IMI (B) port to eight 100Mbps TAXI ports. .

The AMPA 19 is a main processor that manages the state of the ATM switch 15. The AMPA 19 transmits a ring signal according to state management to the ATM switch 15 through the CMDA 17.

However, there was a path capable of transmitting the NO.7 message received from the E1 trunk to the AMPA 19. However, this path is a path that is only matched by hardware. There was a problem that the NO.7 messages could not be sent and received.

Accordingly, the present invention has been made to solve the above-described problems, the object of which is to provide a variety of other services, such as IMT-2000 and intelligent networks by accepting the NO.7 signaling method in the ATM switch, the basic structure of the hardware of the ATM switch Without modification, the present invention provides an ATM switch that accommodates the NO.7 signaling system, which accommodates a new NO.7 hardware device and then sends and receives NO.7 messages to AMPA.

In the present invention to achieve this object, the ATM switch that accommodates the NO.7 signaling scheme includes: CEIA for changing the NO.7 message into an asynchronous transmission mode adaptation layer type cell; FMDA for multiplexing the NO.7 messages received from the CEIA to the switches in the exchange and demultiplexing the NO.7 messages received from the switches; A STIA for converting the demultiplexed NO.7 message into a NO.7 level 2 protocol, writing to the first dual port RAM, and generating an interrupt signal indicating that the NO.7 message is stored in the first dual port RAM; An AMPA that detects an interrupt signal from the STIA, writes it to the second dual port RAM, and generates an interrupt signal indicating that the NO.7 message is stored; Contains CMDA that connects NO.7 messages between AMPA and switch.

Another feature of the present invention is an asynchronous transmission mode switch having a 1,2CEIA, a 1,2FMDA, a switch, a STIA, a 1,2AMPA, and a 1,2CMDA and accommodating NO.7 signaling. 10. A method of communication of a message of NO.7 in the method, the first CEIA receiving the message of NO.7 by making an asynchronous transmission mode adaptation layer type cell and transmitting it to the first FMDA; Receiving the NO.7 message from the first CEIA, the first FMDA multiplexes the NO.7 message to the switch, and the switch transmits the NO.7 message to the second FMDA; Receiving the NO.7 message from the switch, the second FMDA demultiplexes the multiplexed NO.7 message to the second CEIA, and the second CEIA transmits the demultiplexed NO.7 message to the STIA via the E1 interface; Receiving a demultiplexed NO.7 message from CEIA, the STIA extracts one of 32 channels received through the E1 interface, and then converts the NO.7 message for one channel into a NO.7 level 2 protocol; About the NO.7 message After converting the level 2 protocol to the level 3 protocol, the NO.7 message converted to the level 3 protocol is written to the first dual port RAM (hereinafter referred to as DPRAM), and Transmitting an interrupt signal to the 1AMPA indicating that the NO.7 message is stored in the 1DPRAM; After detecting the interrupt signal from the STIA, the first AAMP reads the ID for the NO.7 message stored in the first DPRAM, and then processes the NO.7 message into the Asynchronous Transfer Mode Adaptation Layer 5 type to store it in the second DPRAM in the first AAMP. step; And transmitting the NO.7 message stored in the second DPRAM to the second AAMP through the first and second CMDAs and the switch.

1 is a diagram showing the configuration of an asynchronous transmission mode switch,

2 is a block diagram of an asynchronous transfer mode exchanger accommodating NO.7 signaling according to the present invention;

3 is a diagram illustrating a hardware functional diagram of the NO.7 of the asynchronous transmission mode switch according to the present invention.

<Description of the symbols for the main parts of the drawings>

100-1, 100-2: CEIA 103-1, 103-2: FMDA

105: switch 107: STIA

107-1, 107-2, 107-3, 107-4: E1 data conversion inverse converter

109, 109-1, 109-2: AMPA 111-1, 111-2: CMDA

119: first control unit 129: SMIA

139: DPRAM 139-1, 139-2: E1 Multiplex / Demultiplex

139-3, 139-4: With MTP Level 2 Function

139-5, 139-6: L3 to L2 converter 139-7, 139-8: L3 ← L2 converter

149: second control unit 159-1: SROS

159-2: MTP level 3 section 159-3: Signal terminal status management section

169-1: L-BUS I / F 169-2: SMIA-FW

169-3: DPRAM 169-4: SARA

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.

2 is a block diagram illustrating an ATM switch that accommodates NO.7 signaling according to a preferred embodiment of the present invention, and includes CEIA 100-1 and 100-2 and FMDA 103-1 and 103-2. And a switch 105, a Signaling Terminal Interworking board Assembly (hereinafter, abbreviated as STIA) 107, AMPAs 109-1 and 109-2, and a CMDA 111-1. , 111-2).

CEIA (100-1, 100-2) is connected to the E1 interface of 8 ports to transmit / receive NO.7 messages. The CEIA (100-1, 100-2) transmits NO.7 messages received through the E1 interface. Abbreviated name) and then attach a tag to the 5-byte header of the NO.7 message so that it can be transmitted to FMDA 103-1, 103-2. , 103-2). Here, the E1 interface is an interface capable of handling for each channel.

The FMDAs 103-1 and 103-2 are boards that multiplex / demultiplex cells for NO.7 messages received from the CEIA 100-1 and 100-2. 103-1 multiplexes the NO.7 message received from the CEIA 100-1 to the switch 105. Meanwhile, the FMDA 103-2 demultiplexes the received NO.7 message multiplexed from the switch 105 and transmits the demultiplexed message to the CEIA 100-2.

The switch 105 receives the multiplexed NO.7 message from the FMDA 103-1 and transmits it to the FMDA 103-2, and the NO.7 message is transmitted / received between the CMDAs 111-1 and 111-2. Switch as much as possible.

The STIA 107 extracts one of 32 channels on the E1 interface, converts the extracted NO.7 message into a NO.7 level 2 protocol, and then stores the dual port RAM (received in the STIA 107). Dual Port RAM (hereinafter abbreviated as DPRAM) writes the corresponding NO.7 message, and signals the interrupt in AMPA 109-1 and 109-2 to indicate that the NO.7 message is stored in DPRAM. As a board for transmitting to an interworking assembly board (hereinafter referred to as SMIA) 129, the E1 data conversion inverse converters 107-1, 107-2, 107-3, and 107-4 are connected. Equipped.

When the E1 data conversion inverse converter 107-1 extracts one of the 32 channels, it receives a NO.7 message at a transfer rate of 64 Kbps, writes it to the internal DPRAM, and stores the NO.7 message in the DPRAM. The interrupt signal is sent to the SMIA 129. At this time, the E1 data conversion inverse transformers 107-2, 107-3, and 107-4 operate in the same manner as the E1 data conversion inverse transformer 107-1.

The AMPA 109-1 is a board including an SMIA 129 and a first control unit 119. After detecting an interrupt signal from the STIA 107, the AMPA 109-1 is an E1 data conversion inverter 107-1, 107-2. Reads the NO.7 message stored in the DPRAM in the DMA-3, 107-4 through the L-bus D, writes it to the DPRAM 139 in the AMPA 109-1, and writes it to the CMDA 111-. 1, 111-2 and switch 105 transmit a signal to AMPA 109-2 indicating that there is a NO.7 message to send to AMPA 109-2. At this time, all the scheduler and message processing of the AMPA 109-1 is a SUNSPARK processor operating system, which is an AMPA processor of the ATM shown in FIG. 3, and performs a real time task and job scheduling function (Sunspark). Real time Operation System: hereinafter referred to as SROS) 159-1. After detecting the corresponding interrupt signal, the SROS 159-1 transmits a NO.7 message to the signal terminal state management unit 159-3 of the AMPA 109-1 via the S-bus. In addition, in order to use the SROS 159-1 in the AMPA 109-1 without change, a specific ID value is set in the SROS 159-1 to determine whether it is an ATM cell message or a NO.7 message. Make a distinction.

The SMIA 129 is a board for interworking signal messages. The SMIA 129 includes a DPRAM 139 and a second controller 149. The DPRAM 139 controls write operations of the second controller 149. To store the NO.7 message received from the DPRAM in the E1 data conversion inverse converters 107-1, 107-2, 107-3, and 107-4. The second control unit 149 detects an interrupt signal from the E1 data conversion inverse converters 107-1, 107-2, 107-3, and 107-4, and then converts the E1 data conversion inverse converters 107-1 and 107-. If the ID for the message stored in DPRAM in 2, 107-3, 107-4 is read through the L-bus D and is a NO.7 message, the NO.7 message is read as AAL5 type among ATM cell types. Processing to transmit to the CMDA (111-1) through the TAXI bus (C).

The first controller 119 controls state management so that the SMIA 129 in the AMPA 109-1 operates normally.

The CMDAs 111-1 and 111-2 perform a 1: 8 cell multiplex / demultiplex function that extends the IMI (B) port for eight processors, and eight 100Mbps taxis with 155Mbps IMI ports. A board that extends to a (taxi) port, allowing messages to be sent / received between the AMPAs 109-1 and 109-2 and the switch 105.

Based on the above configuration, the NO.7 hardware functional diagram of the ATM switch according to the present invention will be described in more detail with reference to FIG.

The CEIA 100-1, which is transmitted from a signal terminal (not shown) and receives the NO.7 message through the E1 interface, converts the NO.7 message into an ATM ALL type cell and changes it into a 5-byte header. A tag is attached and transmitted to FMDA 103-1 through Utopia (Universal Test & Operations Physical Interface for Atm: hereinafter abbreviated as UTOPIA) (A).

The FMDAs 103-1 and 103-2 receiving the ATM ALL type NO.7 message from the CEIA 100-1 receive the NO.7 message as shown in 139-1 and 139-2 of FIG. After multiplexing, the multiplexed NO.7 message is sent to the switch 105. In addition, the switch 105 switches in the direction of the FMDA 103-2, and then transmits the NO.7 message received from the FMDA 103-1 to the FMDA 103-2.

Upon receiving the NO.7 message from the switch 105, the FMDA 103-2 demultiplexes the multiplexed NO.7 message as shown in 139-1 and 139-2 of FIG. To send). The CEIA 100-2 transmits the demultiplexed NO.7 message to the STIA 107 via the E1 interface.

After receiving the demultiplexed NO.7 message from the CEIA 100-2, the E1 data conversion inverse converter 107-1 in the STIA 107 extracts one of 32 channels received through the E1 interface, and then FIG. After converting the NO.7 message of one channel to the NO.7 level 2 protocol as shown in 139-3 and 139-4 of FIG. 3, the NO.7 message as shown in 139-7 and 139-8 of FIG. Convert the level 2 protocol to a level 3 protocol. On the other hand, when the STIA 107 transmits the NO.7 message in the direction of the signal terminal (not shown), as shown in 139-5 and 139-6 of FIG. 3, the level 3 protocol is applied to the NO.7 message. Transmit by converting to Level 2 protocol.

The E1 data conversion inverse converter 107-1 writes the NO.7 message converted by the level 3 protocol to the DPRAM (not shown) accommodated therein, and an interrupt signal indicating that the NO.7 message is stored in the DPRAM. Is transmitted to the second control unit 149 in the SMIA 129. At this time, the E1 data conversion inverse transformers 107-2, 107-3, and 107-4 operate in the same manner as the E1 data conversion inverse transformer 107-1.

The second controller 149, which detects the interrupt signal from the E1 data conversion inverse converters 107-1, 107-2, 107-3, and 107-4, performs the E1 data conversion inverse converters 107-1, 107-2, and 107. After reading through the L-bus (D) interface as shown in 169-1 of FIG. 3, the ID for the NO.7 message stored in the DPRAM in -3, 107-4) is set to NO. If it is a .7 message, the NO.7 message is processed into an AAL5 type among ATM cell types to fit the SMIA 107 formware (FW) as shown in 169-2 of FIG. 3, as shown in 169-3 of FIG. Control to store in the DPRAM 139.

At this time, all scheduler and NO.7 message processing of the AMPA 109 shown in FIG. 3 is managed by the SROS 159-1. After detecting the corresponding interrupt signal, the SROS 159-1 detects the NO.7 message. The message is transmitted to the signal terminal state manager 159-3.

In addition, the second controller 149 sets a specific ID value to the SROS 159-1 so as to use the SROS 159-1 without change. If it is determined that the message is a NO.7 message, the above-described NO.7 message is stored in the DPRAM 169-3. In addition, the second controller 149 processes the NO.7 message using a message transfer port (hereinafter referred to as MTP) Level 3 protocol function, and then the other control unit 149 and the other AMPA 109-2 in which the main application is accommodated. During communication, the corresponding NO.7 message is written to the DPRAM 139 in the SMIA 129 using the ID stored in the SROS 159-1.

As such, the second control unit 149 assembles and disassembles the NO.7 message stored in the DPRAM 139 (Segmentation And Reassembly Atm adpation layer, hereinafter abbreviated as SARA) 169-4 and CMDA. The NO.7 message is transmitted to the AMPA 109-2 together with a signal indicating that there is a NO.7 message to be transmitted to the AMPA 109-2 through the 111-1 and 111-2 and the switch 105. Here, the SARA 169-4 assembles, disassembles and transmits the packet-type asynchronous transmission mode cell.

On the other hand, when an ATM cell message is transmitted to a corresponding signal terminal (not shown) by a general user, the second controller 149 sets a specific ID value and processes the ATM cell message into an AAL1 type to process SMIA ( 129) writes to the DPRAM 139, analyzes a specific ID, writes to the DPRAM (not shown) in the STIA 107, and transmits an interrupt signal to the STIA 107 that there is a message sent to the STIA. .

After receiving the interrupt signal, the STIA 107 reads an ALL1 type ATM cell message from the DPRAM, converts it into a Level 2 protocol, and then converts the processed ATM cell message through the corresponding E1 interface channel to the CEIA 100-2. To send. At this time, the ATM cell message carried on the E1 interface channel is sent to the CEIA 100-2 through the E1 path connected between the CEIA 100-2 and the NO.7 block.

The CEIA 100-2 interworks with the counterpart station with the NO.7 signal by transmitting an ALL1 type ATM cell message through the E1 port that is substantially connected to the counterpart.

As described above, the present invention provides a variety of other services such as IMT-2000 and intelligent networks by adopting the NO.7 signaling scheme in an ATM switch, and provides a new NO.7 hardware device without changing the basic structure of the ATM switch. By easily accepting NO.7 signaling, it is possible to easily implement NO.7 hardware devices due to small development costs.

Claims (5)

In an asynchronous transfer mode exchange, which accepts the signaling scheme for the NO.7 message, A circuit-mimicking interface assembly board for changing the NO.7 message into an asynchronous transfer mode adaptation layer type cell; A frame multiple / demultiplex assembly board which multiplexes NO.7 messages received from the circuit-mimicking interface assembly board and transmits them to a switch in the exchange, and demultiplexes the NO.7 messages received from the switch; A signaling terminal inter which converts the demultiplexed NO.7 message into a NO.7 level 2 protocol, writes to the first dual port RAM, and generates an interrupt signal indicating that the NO.7 message is stored in the first dual port RAM. Working assembly board; An asynchronous transfer mode main processor assembly board that detects an interrupt signal from the signaling terminal interworking assembly board, writes it to a second dual port RAM, and generates an interrupt signal indicating that a NO.7 message is stored; And a cell multiple / demultiplex assembly board for connecting the asynchronous transmission mode main processor assembly board and the switch to transmit / receive NO.7 messages. The method of claim 1, And said signaling terminal interworking assembly board comprises a plurality of E1 data conversion inverse transformers. The method of claim 1, And the asynchronous transmission mode main processor assembly board includes a first control unit and a signaling message interworking assembly board. The method of claim 3, wherein And said signaling message interworking assembly board comprises a dual port RAM and a second control unit. First and second circuit mimic interface assembly board, first and second frame multi / demultiplex assembly board, switch, signaling terminal interworking assembly board, first and second asynchronous transmission mode main processor assembly board, first In the NO.7 message communication method in an asynchronous transmission mode switch having a 2-cell multi / demultiplex assembly board and accepting NO.7 signaling, Receiving, by the first circuit-mimicking interface assembly board, the NO.7 message into an asynchronous transmission mode adaptation layer type cell and transmitting the message to the first frame multiple / demultiplex assembly board; The first frame multiple / demultiplex assembly board receiving the NO.7 message from the first circuit-mimic interface assembly board multiplexes the NO.7 message to the switch, and the switch sends the NO.7 message to the second switch. Transmitting to the frame multiple / demultiplex assembly board; The second frame multiple / demultiplex assembly board receiving the NO.7 message from the switch demultiplexes the multiplexed NO.7 message to the second circuit-mimicking interface assembly board, and the second circuit-mimic interface assembly board Sending a demultiplexed NO.7 message to the signaling terminal interworking assembly board via an E1 interface; The signaling terminal interworking assembly board receiving the demultiplexed NO.7 message from the circuit-mimicking interface assembly board extracts one channel among the 32 channels received through the E1 interface, and then extracts the NO.7 message for the one channel. .7 converting to a Level 2 protocol; After converting the level 2 protocol to the level 3 protocol for the NO.7 message, the NO.7 message converted to the level 3 protocol is written to the first dual port ram, and the NO.7 message is written to the first dual port ram. Transmitting an interrupt signal to the first asynchronous transfer mode main processor assembly board informing that the signal has been stored; The first asynchronous transfer mode main processor assembly board detecting the interrupt signal from the signaling terminal interworking assembly board reads the ID for the NO.7 message stored in the first dual port RAM, and then asynchronously reads the NO.7 message. Processing into a transfer mode adaptation layer 5 type and storing in a second dual port RAM in the first asynchronous transfer mode main processor assembly board; And transmitting the NO.7 message stored in the second dual port RAM to the second asynchronous transmission mode main processor assembly board through the first and second cell multi / demultiplex assembly board and the switch. 7 NO.7 message communication method in asynchronous transfer mode exchange accepting signaling.