KR100281875B1 - Data shuffling and deshuffling apparatus - Google Patents

Abstract

The present invention is an apparatus for implementing shuffling and deshuffling data using a single memory, and in the present invention is an apparatus for shuffling data composed of a plurality of channels. A front end FIFO portion each buffered to fit; A frame memory for storing data output from the front end FIFO unit; An address generator for selectively generating an address for shuffling according to whether the frame memory is in a write and read state; And a rear end FIFO section for buffering data read from the frame memory to match an output timing, wherein the frame memory has a higher data rate than the sum of the data rate input from the front end FIFO section and the data rate output from the rear FIFO section. The data is written and read alternately using the operating frequency. According to the present invention, since the shuffling system can be configured using only one general-purpose memory, the circuit implementation for the system can be simplified and the cost can be reduced.

Description

Data shuffling and deshuffling apparatus

The present invention relates to data shuffling and deshuffling devices, and more particularly to an apparatus for implementing shuffling and deshuffling data using a single memory. The amount of day of video information is enormous. Such video information is often transmitted and recorded after high efficiency encoding which reduces the amount of data. Highly efficient video encoding compresses the amount of data by eliminating redundant portions of video information. Standard Definition (SD) Digital Video Cassette Recorder (DVCR) constitutes a macro block for data compression, and shuffles the macro block in a direction to disperse energy of video data.

1 is a first embodiment showing a conventional video data shuffling apparatus shown in US Patent 5,440,706. The frame memory 110 stores one frame video data. The video data is written to and read from the frame memory 110 by the addresses generated by the input address generator 120 and the output address generator 130, and the address memory 150 and the address converter 160 are input addresses. The generator 120 and the output address generator 130 generate an address. The shuffling apparatus of FIG. 1 performs a shuffling operation with one frame of frame memory 110 and writes data to a portion of the frame memory 110 to which data is read.

2A and 2B show a second embodiment of a conventional video data shuffling apparatus, FIG. 2A is a block diagram for processing video data, and FIG. 2B is a block diagram for generating an address. In FIG. 2A, the video data is written to the first frame memory 210 by the switching controller 230 operated by the field signal (contact point a of switch 1 is connected to contact point b), and the second frame memory. Leads from 220 (contact point a of switch 1 is connected to contact point b). The first frame memory 210 and the second frame memory 220 each store one frame of data. The first address generator 260 of FIG. 2B generates an address for inputting video data into the first frame memory 240 in the recording mode and outputting the video data in the playback mode, and the second address generator 270. Outputs video data from the second frame memory 250 in the recording mode and generates an address for inputting the video data in the reproduction mode. The first switch SW1 and the second switch SW2 are switched every frame by the switching controller 230 operated by the field signal. The first and second address generators 260 and 270 are fixed address generators that generate the same address at the same position. That is, in the write mode, when the first data memory 240 is written by the address generated by the first address generator 260, the second data memory 250 is generated by the second address generator 270. It is read by address. Next, the first data memory 240 is read by an address generated by the second address generator 270, and the second data memory 250 is written by an address generated by the first address generator 260. In contrast, in the reproduction mode, when the first data memory 240 is written by an address generated by the second address generator 270, the second data memory 250 may generate an address generated by the first address generator 260. Is lead by. Next, when the second data memory 250 is written by the address generated by the second address generator 270, the first data memory 240 is read by the address generated by the first address generator 260.

As described above, the conventional apparatus of FIG. 1 uses one frame video frame memory, thereby saving memory, but it is difficult to implement a circuit for generating a shuffling address, and the apparatus of FIG. There is a disadvantage.

The present invention provides a shuffling device that reads and writes data into a single frame memory using a frequency higher than the input data rate, separated into luminance (Y) and color difference (Cr, Cb) signals during recording. There is.

Another technical problem to be achieved by the present invention is a deshuffle that reads and writes data into a single frame memory using a frequency higher than a data rate divided into luminance (Y) and color difference (Cr, Cb) signals. To provide a ring device.

1 is a first embodiment showing a conventional video data shuffling apparatus.

2A and 2B are a second embodiment showing a conventional video data shuffling apparatus.

3 is a block diagram showing a data shuffling and deshuffling apparatus according to the present invention.

4A is an address generation block diagram for addressing the frame memory 360 of FIG. 3 in a write mode (shuffling mode).

4B is an address generation block diagram for addressing the frame memory 360 of FIG. 3 in a playback mode (deshuffling mode).

5A is a detailed view of the first address generator of FIGS. 4A and 4B.

5B is a detailed view of the second address generator of FIGS. 4A and 4B.

In order to solve the above technical problem, an apparatus for shuffling data consisting of a plurality of channels, comprising: a front end FIFO unit for buffering each of the data input to the plurality of channels in accordance with the timing; A frame memory for storing data output from the front end FIFO unit; An address generator for selectively generating an address for shuffling according to whether the frame memory is in a write and read state; And a rear end FIFO section for buffering data read from the frame memory to match an output timing, wherein the frame memory has a higher data rate than the sum of the data rate input from the front end FIFO section and the data rate output from the rear FIFO section. Data shuffling device characterized in that the data is written and read alternately using the operating frequency.

In order to solve the above other technical problem, an apparatus for deshuffling data composed of a plurality of channels, the apparatus comprising: a rear end FIFO unit for buffering the input data to match the timing; A frame memory for storing data output from the rear FIFO unit; An address generator for selectively generating an address for deshuffling according to whether the frame memory is in a write and read state; And a front end FIFO unit configured to buffer data of a plurality of channels, respectively, according to the timing of the data read from the frame memory, wherein the frame memory includes a data rate input from the rear end FIFO unit and a data rate output from the front end FIFO. A data deshuffling device characterized in that data is alternately written and read using an operating frequency higher than the data rate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a data shuffling and deshuffling apparatus according to the present invention. The first, second, and third FIFOs 310,320,330 by first, second, and third FIFOs 310,320,330 and first, second, and third FIFOs 310,320,330 that first-in, first select luminance, color difference (Cr, Cb) data. ), A first switch SW1 for selecting a second switch, a second switch SW2 for reading and writing data switched from the first switch SW1 with contacts a, b, and c, and the second switch SW2. Frame memory 360 in which data generated by switching of the data is stored and read, a fourth FIFO 370 that first-in first-out data read from the frame memory 360 by the second switch SW2, a clock, and The counter 340 is counted by the start signal, and the switching controller 350 controls the switching of the first switch SW1 and the second switch SW2 based on the count value of the counter 340.

As shown in FIG. 3, video data is composed of a plurality of macroblock units, and as input signals, luminance (Y) data, color difference (Cr) data, and color difference (Cb) data, which are its data components, are simultaneously input. The luminance (Y) data, the color difference (Cr) data, and the color difference (Cb) data are stored in the order of input to the first, second, and third FIFOs (310, 320, 330), respectively.

The luminance (Y) data, the color difference (Cr) data, and the color difference (Cb) data are selected by the first switch SW1, and the selected data is written to the frame memory 360 by switching of the second switch SW2. Leads. For example, when the contact b of the first switch SW1 is connected to the contact a and the contact b of the second switch SW2 is connected to the contact a, the luminance data stored in the first FIFO 310 is stored. Is written to the frame memory 360. In addition, when the contact point c of the first switch SW1 is connected to the contact point a and the contact point b of the second switch SW2 is connected to the contact point a, the color difference Cr stored in the second FIFO 320 is stored. When data is written to the frame memory 360, the contact d of the first switch SW1 is connected to the contact a, and the contact b of the second switch SW2 is connected to the contact a. Color difference (Cb) data stored in the 3FIFO 330 is written to the frame memory 360. Meanwhile, when the contact c of the second switch SW2 is connected to the contact a, the luminance and color difference data stored in the frame memory 360 are read to the fourth FIFO 370. The fourth FIFO 370 is a buffer for timing data rate of data signal processing after data read from the frame memory 360 is shuffled. The data rate required to read and write the frame memory 360 may include a data rate or a shuffling operation in front of the first, second, and third FIFOs 310, 320, and 330 where the video signal is input. The data should be higher than the sum of the data rates stored in the fourth FIFO 370.

For example, data is processed into 8 bits, the data rate of the front end of the first FIFO 310 is 13.5 MHz, the data rate of the front end of the second FIFO 320 is 3.375 MHz, and the data rate of the front end of the third FIFO 330 is 3.375 MHz. When the data rate of the fourth stage of the fourth FIFO 370 is 18 MHz, the operating frequency of the frame memory 360 performing the shuffling operation is 54 MHz, which is a multiplication.

In addition, if the data is processed as 16-bit data, the data rate at the front end of the first FIFO 310 is 13.5 MHz / 2, the data rate at the front end of the second FIFO 320 is 3.375 MHz / 2, and the data rate at the front end of the third FIFO 330. Is 3.375 MHz / 2, and the data rate at the rear end of the fourth FIFO 370 is 18 MHz / 2. Therefore, the operating frequency of the frame memory 360 that performs the shuffling operation uses 27 MHz. The embodiment of the present invention is an example of operating with 16-bit data.

The counter 340 starts with reference to the frame start signal of the video data and operates at a 27 MHz clock and applies the switching control unit 350 to control switching according to a predetermined time. The switching controller 350 generates a control signal for switching the first switch SW1 and the second switch SW2 according to the applied counter value. That is, when the video data is input, the first switch SW1 switches the contact a to the contacts b, c, and d by the switching controller 350 at a predetermined time at the 27 MHz clock from the start point of the video data frame. do. In the second switch SW2, the contact point a switches to the contacts b and c by the switching controller 350 at a predetermined time determined by the 27 MHz clock at the start point of the video data.

Next, the process in which the shuffled data during recording is deshuffled during reproduction is operated in reverse of shuffling. That is, the fourth FIFO unit 370 buffers the input data to match the timing. The frame memory 360 stores data output from the fourth FIFO unit 370 from the FIFO unit. The first, second, and third FIFOs 310, 320, and 330 buffer the plurality of data read from the frame memory 360 to match timing. The frame memory 360 alternates data using an operating frequency higher than the sum of the data rates input from the fourth FIFO unit 370 and the data rates output from the first, second, and third FIFOs 310, 320, and 330. Lite and lead.

FIG. 4A is an address generation block diagram for addressing the frame memory 360 of FIG. 3 in a recording mode (shuffling mode), a frame memory 410 in which data is stored in units of frames, and a first address for generating a write address. The first switching unit 420 and the second address generating unit 430 are switched to the generator 420, the second address generator 430 for generating the read address, and the contacts a, b, and c. It consists of three switches (SW3).

4B is an address generation block diagram for addressing the frame memory 360 of FIG. 3 in a reproducing mode (deshuffling mode), a frame memory 440 in which data is stored in units of frames, and a first address generating a write address. Switching the second address generator 450 and the first address generator 460 through the address generator 450, the second address generator 460 for generating the read address, and the contacts a, b, and c. It consists of a 4th switch SW4.

As shown in FIGS. 4A and 4B, the address generator includes a first address generator 420 and 450 and a second address generator 430 and 460 and selectively applies an address depending on whether the state of the frame memory is read or written. . The first address generator 420 and 450 and the second address generator 430 and 460 are configured in the form of a ROM table having the same value at a predetermined position at all times. In the case of an address signal generated by the first address generator 420 and 450, a write is performed. It is used as an address for the write operation of the frame memory in the mode and as an address for the read operation in the reproduction mode. The address signal generated by the second address generators 430 and 460 is used as an address for the read operation of the frame memory in the recording mode and as an address for the write operation in the reproduction mode.

When the contact a of the second switch SW2 of FIG. 3 is switched to the contact b, at the same time, the third switch SW3 is connected to the first address generator 420 so that data is stored in the frame memories 410 and 440. ) In the recording mode, and in the playback mode. When the contact a of the second switch SW2 of FIG. 3 is switched to the contact c, at the same time, the third switch SW3 is connected to the second address generator 460 so that the data is stored in the frame memory 410. In the recording mode, the display device 440 reads the light. Herein, the operating frequencies of the frame memories 410 and 440 are 27 MHz, and thus the outputs of the first, second, and third FIFOs 310, 320, and 330 of FIG. Input in mode and output in regeneration mode are 27MHz.

5A is a detailed view of the first address generating unit of FIGS. 4A and 4B, and includes a first counter 510 and a first address table 520.

5B is a detailed view of the second address generating unit of FIGS. 4A and 4B, and includes a second counter 530 and a second address table 540.

As shown in FIGS. 5A and 5B, the first counter 510 has a counter value of "0" due to a counter reset pulse generated at a predetermined position of an input video signal, and the reset pulse is non-active. In the) state, the count operation is incremented by one. In addition, the second counter 530 performs a counting operation in which the counter value becomes "0" at a predetermined position by a counter reset pulse generated in an 18 MHz system. Otherwise, the second counter 530 increases the value one by one. In the first and second address tables 520 and 540, an address value is input by a count value generated by the first counter 510 and the second counter 530 and corresponds to the address value, that is, the first address and the second address. Output the ROM table value. In another embodiment, the first and second address tables 520 and 540 may be configured with logic.

Here, the first counter 510 is a reference signal for reading data from the first address table 520 and uses a 13.5M counter value based on the operating frequency of the front end of the first, second, and third FIFOs 310, 320, 330. The second counter 530 uses an 18 M counter value based on the operating frequency of the fourth FIFO 370 as a reference signal for reading data from the second address table 540.

As described above, according to the present invention, since the shuffling system can be configured using only one general-purpose memory, the circuit implementation for the system can be simplified and the cost can be reduced.

Claims (10)

In the apparatus for shuffling data composed of a plurality of block units, A front end FIFO unit which buffers data input to a plurality of channels at timing; A frame memory for storing the data output from the front end FIFO unit in units of frames; A subsequent FIFO section buffering the data read from the frame memory to match an output timing; A switching control unit which alternately writes and reads the data to the frame memory at a multiplication frequency higher than a data rate obtained by adding the data rate input from the front end FIFO unit and the data rate output from the rear end FIFO unit from the start of the frame of the data; Data shuffling apparatus comprising a. The data shuffling apparatus of claim 1, wherein the front end FIFO unit comprises first, second, and third FIFOs respectively storing luminance (Y) and color difference (Cr, Cb) data of the video data. The data shuffling apparatus of claim 1, wherein the frame memory is a single memory that stores two frames of video data. The data shuffling apparatus of claim 1, wherein an operating frequency of the frame memory is higher than a data rate obtained by adding up the luminance and color difference data and a data rate output from the rear FIFO unit. The display apparatus of claim 1, wherein the switching controller comprises: a first address generator configured to generate a write address in the frame memory; And a second address generator which generates a read address in the frame memory. 6. The apparatus of claim 5, wherein the first address generator comprises: a counter for operating at an operating frequency of the front end FIFO unit by a start signal and counting a value thereof; And a first address storage unit generating a fixed address corresponding to a count value generated by the counter. 7. The data shuffling apparatus of claim 6, wherein an operating frequency of the counter is a multiplication frequency of an input video data rate. 6. The apparatus of claim 5, wherein the second address generator comprises: a counter for counting an operating frequency of the rear end FIFO unit according to a start signal; And an address generator for generating a fixed address corresponding to the count value generated by the counter. In the apparatus for deshuffling data consisting of a plurality of channels, A rear-end FIFO unit for buffering the plurality of channel data in time; A frame memory for storing data output from the rear FIFO unit; An address generator for selectively generating an address for deshuffling according to whether the frame memory is in a write and read state; And a front end FIFO unit configured to buffer the plurality of channel data, respectively, in accordance with the timing of the data read from the frame memory, wherein the frame memory includes a data rate input from the rear end FIFO unit and a data rate output from the front end FIFO. A data deshuffling device, characterized in that data is alternately written and read using an operating frequency higher than the data rate. The memory device of claim 9, wherein the address generator comprises: a first address generator configured to generate a read address in the frame memory; And a second address generator for generating a write address in the frame memory.

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