KR100280929B1 - Semiconductor devices - Google Patents

Abstract

In order to reduce the chip size of the semiconductor device as well as to isolate the noise between at least two types of pads with different functions, the output pins or I / O pins are placed between them. At least one Vcc and at least one Vss are installed on opposite edges of the package to be deployed.

Description

Semiconductor devices

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

2 is a wiring diagram showing a peripheral portion of an internal circuit of a semiconductor device according to the first embodiment of the present invention.

3 is a circuit diagram showing a connection state between individual pads provided on one side of the semiconductor device according to the first embodiment of the present invention.

4 is a circuit diagram showing a connection state between individual pads provided on the other side of the semiconductor device according to the first embodiment of the present invention.

5 is a plan view illustrating an internal circuit and a lead frame of the semiconductor device according to the first embodiment of the present invention.

6 is a wiring diagram showing a peripheral portion of an internal circuit of a semiconductor device according to a second embodiment of the present invention.

7 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

8 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention.

9 is a wiring arrangement diagram showing a peripheral portion of an internal circuit of a semiconductor device according to a modification of the present invention.

10 is a plan view showing a conventional semiconductor device.

11 is a wiring arrangement diagram showing a periphery of an internal circuit for a conventional semiconductor device.

12 is a plan view showing an internal circuit and a lead frame of a conventional semiconductor device.

* Explanation of symbols for main parts of the drawings

100: chip 101: package

102: X decoder 103: Y decoder

104: internal circuit 105: first pad portion

106: second pad portion 115, 116: pad power supply wiring

117, 118: pad ground wiring 123: lead frame

131, 132: power supply pad 133, 134: ground connection pad

The present invention relates to a semiconductor device such as a mask ROM for mass storage.

As shown in FIG. 10, the semiconductor device is provided with a plurality of external connection pins 1 to 32 protruding from both sides of the package 21 having a generally rectangular planar shape. In addition, in such a conventional semiconductor device, as shown in FIG. 10, the power supply pin Vcc 32 and the GND terminal Vss 16 are disposed at a position farthest from each other on the diagonal of the package 21. do. That is, the power supply pin Vcc 32 and the GND terminal Vcc 16 are disposed at the upper right and lower left portions of the package 21 shown in FIG. The address input terminals A ₁₁ (25) to A ₁₈ (31) are arranged at positions relatively close to the power supply pin Vcc (32), while the address input terminals A ₀ (12) to A ₁₆ (2) are the address inputs. The terminals A ₁₁ (25) to A ₁₈ (31) are disposed on the reverse side side edge portion. Furthermore, the data output terminals D ₀ (13) to D ₂ (15) are arranged at positions relatively close to the GND terminal Vss (16), while the data output terminals D ₃ (17) to D ₇ (21) are the data. The output terminals D ₀ (13) to D ₂ (15) and the GND terminal Vss 16 are disposed on the side edges. Referring to FIG. 10, reference numeral 1 denotes a redundant pin (NC), reference numerals 22 and 24 denote control terminals (/ CE and / OE) such as chip enable terminals, and reference numeral 23 denotes an additional input terminal. A ₁₀ is shown. 11 and 12, reference numeral 35 denotes a chip, reference numeral 35a denotes an internal circuit installed inside the chip 35, and reference numeral 35b denotes a die pad for die bonding the chip 35. Indicates.

When designing a memory having a large data width of 8 bits or 16 bits, in order to reduce the influence of data output noise on the chip, in general, the pad Vcc wiring 31 has a Vcc wiring (for the internal circuit 35a). The pad Vss wiring 32 is separated from the Vss wiring 34 for the internal circuit 35a while being separated from the 33. In the fin arrangement of such a conventional semiconductor device, the chip 35 shown in FIG. 11 is formed inside the package 21. That is, it is necessary to wire the Vcc wiring 31 and the Vss wiring 32 to the pads 36 and 37 provided on the upper and lower portions of the chip 35, respectively. In this case, the wiring passing through the left and right sides of the chip 35 ( 31, 32) increases the chip size. In order to reduce the effect of output noise on the input wiring, it is preferable to wire different Vcc / Vss wiring to the address input pad 41 and the data output pad 42, but it is arranged under the chip 35. If the address input pad 41 and the data output pad 42 are separated from each other, the size of the chip is further increased, so that it is difficult to actually manufacture such a product. Furthermore, as shown in FIG. 12, when the chip 35 is enclosed inside the package 21, the pins 45 corresponding to the central portion of the chip 35 are disposed adjacent to the side portions of the chip 35. Should be. Therefore, it is necessary to prevent the bonding wires 47 and 47a connecting the pin 45 and the other pin 45a to the pads 46 and 46a of the chip 35, respectively. Thus, as shown in FIG. 12, the pads 46 disposed adjacent to the pads 46a are disposed away from the remaining pads. In this case, however, most of the pads are aligned with each other, but only two pads 46 and 46a provided on the side of the chip 35 are arranged in two rows. That is, compared with the rest, an additional area is required for the sides of the chip 35. When the internal circuit 35 is formed by the memory cell array, the arrangement becomes incomplete if the memory cell is omitted from a portion of the edge portion. Therefore, it is necessary to reduce the number of columns or rows of X-direction or Y-direction memory cells provided in the memory cell array by several at each end. Thus, the number of memory cells is significantly reduced against the requirement for high integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing size, separating noise between at least two different types of pads, and easily performing wire bonding.

The problem solving means according to the first to sixth aspects of the present invention includes a chip and a package for accommodating the same, and has a plurality of external connection pins on two opposite sides of the package, so that the external connection pins are connected to the chip. A power pin formed on each of the two opposite sides of the package to supply power, a ground pin formed on each of the two opposite sides of the package to connect the chip to ground, and not connected to the outside And a surplus pin, the surplus pin being sandwiched between the power supply pin and the ground pin at each of the two opposite sides of the package.

The problem solving means according to claim 2 of the present invention comprises a package and a chip housed inside the package, the package being formed on two sides facing each other and comprising a plurality of external connections including a power pin and a ground pin. And a chip, wherein the chip has an internal circuit having at least one power supply terminal and a ground connection terminal at each of two opposite sides, a first pad part for connecting the internal circuit and the power pin, and the inside of the chip. A second pad portion for connecting a circuit and the ground pin, wherein the first pad portion includes at least one on two opposite sides of the chip to be wired between each power supply terminal of the internal circuit and the power pin; A power supply pad formed in pieces, and pad power supply wirings arranged in parallel near two opposite sides of the internal circuit and connected to the respective power supply pads, The second pad part includes at least one ground connection pad formed on two opposite sides of the chip so as to be wired between each ground connection terminal of the internal circuit and the ground pin, and the opposite side of the internal circuit. The pad ground wiring line which is peeled in parallel to two sides and connected to each said ground connection pad is provided.

The problem solving means according to claim 3 of the present invention is that one of the power supply pins of the external connection pin is disposed on one side of the package, another power pin is disposed on the reverse side of the package and the external Among the connecting pins, one ground pin is disposed on one side of the package, and the other ground pin is disposed on the reverse side of the package.

The problem solving means according to claim 4 of the present invention comprises a first pad used only for inputting a predetermined signal to the chip on at least one side of the chip, and a second pad used for outputting a signal from the chip at least. Is formed, and the power pad and the ground connection pad disposed on the at least one side on which the second pad and the first pad of the chip are formed are spaced apart from each other with a predetermined separation process, and the power pad and the ground connection are spaced apart from each other. One pad of the second pad and the first pad is disposed between the pad for the pad, and the other pad of the second pad and the first pad is the pad for the power supply or the pad for ground connection. It is placed at the raised end.

The problem solving means according to claim 5 of the present invention is disposed opposite to one of the power supply terminal formed on one side of the internal circuit and one of the ground connection terminals formed on the other side of the reverse side, The other power supply terminal formed on the other side and the other ground connection terminal formed on the one side are disposed to face each other.

The problem solving means according to the sixth aspect of the present invention, the external connection pin includes a surplus pin that is not connected to the outside, the surplus pin between the power pin and the ground pin on each of the one side and the reverse side It is placed sandwiched.

In the semiconductor device according to the first to sixth aspects of the present invention, since the excess pin is disposed at a position between the power pin and the ground pin of one side and the reverse side of the package, the chip is placed at a position corresponding to this position. Since there is no need to arrange chips and surplus pins, it is not necessary to form a plurality of pads in the corners of the chip to prevent shorting of the bonding wires as in the conventional example. As a result, a flawless quadrangular array or the like can be configured up to the end of the chip, and the area efficiency can be improved as compared with the conventional example.

In the semiconductor device according to claim 2 of the present invention, the pad power wiring and the pad ground wiring need to be wire-bonded to each lead frame at two opposite sides of the internal circuit, but the power supply terminal and the ground of the internal circuit are ground. Since the connection terminals are arranged on two opposite sides of the internal circuit, there is no need to wire the pad power supply wiring and the pad ground wiring between the two sides. That is, the external connection pins can be connected on two opposite sides of the internal circuit without surrounding the pad power wiring and the pad ground wiring on the entire peripheral surface of the internal circuit. Therefore, the chip size can be reduced by that amount.

In the semiconductor device according to claim 3 of the present invention, one power pin is disposed on one side of the package, the other power pin is disposed on the reverse side of the package, and one ground pin is placed on one side of the package. When the other ground pin is arranged on the reverse side of the package, both the power pin and the ground pin can be pulled out from both sides of the package. Wiring and the ground pad and the ground pin can be wired easily, thus increasing the freedom of wiring design.

In the semiconductor device according to claim 4 of the present invention, since one of the first pad and the second pad and the other pad are arranged with the power pad or the ground connection pad floating thereon, noise is mixed in one pad. Even the other pad can be separated into a pad for power supply or a pad for ground connection.

In the semiconductor device according to claim 5 of the present invention, two or more power supply terminals are arranged on the reverse side on the diagonal side of the internal circuit, and two or more ground connection terminals are arranged on the reverse side on the diagonal side different from the power supply terminal of the internal circuit. As a result, the degree of freedom in design is increased with respect to any wiring outside the internal circuit and the chip.

The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description set forth with reference to the accompanying drawings.

[First Embodiment]

<Structure>

1 shows a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the present embodiment is formed by sealing a 64 megabit mask ROM in a package having 28 pins, and a chip contained in the package 101 and the package 101. It is a semiconductor memory device for mass storage provided with (100).

The package 101 has an insulating substrate and a molding made of epoxy resin or the like for sealing the circuit and the like and is provided on the insulating substrate so that the internal circuit 104 is inserted therebetween. A plurality of 28 external connection pins 1P to 28P including power supply pins Vcc (5P, 19P) and ground pins (Vss) 10P, 24P are provided on the reverse side of the package 101 (FIG. 1). Is formed on the left and right sides), and as shown in FIG. 5, the plurality of lead frames 123 are connected to the external connection pins 1P to 28P in order to connect the external connection pins and the chip with each other by bonding wires. ) And the chip 100.

The external connection pins 1P to 28P are disposed on the sides 126 and 127 (the left side and the right side in FIG. 1) opposed to the periphery of the package 101. Of the external connection pins 1P to 28P, the power supply pins Vcc 5P and 19P and the ground pins Vss 10P and 24P are the sides 126 and 127 of the package 101 (left in FIG. 1). And the right side) in the nearly center portion. Among them, the first power supply pin (Vcc) 5P is disposed almost at the center of one side of the package 101, while the second power supply pin (Vcc) 19P is the other side of the package 101. It is located almost in the center. Moreover, the first ground pin (Vss) 10P is disposed almost at the center of one side of the package 101, while the second ground pin (Vss) 24P is positioned almost at the other side of the package 101. It is arranged in the center. Furthermore, among the external connection pins 1P to 28P, the I / O pins (second pins) (1P to 4P, 11P to 14P, 15P to 18P, and 25P to 28P) serving as address input pins and data output pins are The power supply pins Vss 5P and 19P and the ground pins Vss 10P and 24P of the left and right sides 126 and 127 of the package 101 are disposed up and down.

The external connection pins 1P to 28P are formed on the left and right sides 126 and 127 of the package 101, and redundant pins (NC) 7P, 8P, 21P, and 22P that are not connected to the outside, and chip enable. Pin (/ CE) 20P, read pin (/ RD) 23P, ALEL pin 6P, and ALEH pin 9P. The chip enable pin (/ CE) 20P, the read pin (/ RD) 23P, the ALEL pin 6P, and the ALEH pin 9P, which are used only for inputting a control signal, are collectively referred to as input pins (first). Pin). The redundant pins (NC) (7P, 8P), ALEL pin (6P) and ALEH pin (9P) is between the power supply pin (Vcc) (5P) and the ground pin (Vss) (10P) of the left side 126. Are arranged. Meanwhile, the redundant pins (NC) 21P and 22P, the chip enable pin (/ CE) 20P, and the read pin (/ RD) 23P are the power supply pins (Vcc) 19P of the right side 127. ) And ground pin (Vss) 24P.

As shown in FIG. 2, the chip 100 includes an internal circuit 104 which performs a function as a memory circuit, and an internal circuit 104 via external lead pins 123 to external connection pins 1P to 28P. ) And first and second pad portions 105, 106 for connecting (wire bonding), respectively.

The internal circuit 104 includes a memory cell array consisting of a plurality of memory cells arranged vertically and laterally, and peripheral circuits 102 and 103 for controlling them. Inside the memory cell array of the interior 104, each of the memory cells is regularly arranged in the horizontal axis symmetry. The X (word line selection) decoder 102 is disposed at the left end of the internal circuit 104 as a peripheral circuit for specifying a word line for a memory cell along the longitudinal direction (Y direction), while Y (bit line) The decoder 103 is disposed at the lower end of the internal circuit 104 as a peripheral circuit for specifying the bit line for the memory cell along the transverse direction (X direction).

The first pad portion 105 includes a pair of power supply (Vcc) pads 131 and 132 connected (wire bonded) to the lead frame 123 connected to the power supply pins (Vcc) 5P and 19P. Between the power supply pads 131 and 132 and the internal circuit 104 so as to be arranged in parallel with each other near the two reverse sides of the internal circuit 104 shown in FIG. The pad power supply wirings 115 and 116 connected are provided.

Among them, the first power supply pad 131 and the pad power supply wiring 115 corresponding thereto are disposed on one side of the chip 100 near the upper side of FIG. 2, while the second power supply pad 132 and The pad power supply wiring 116 corresponding thereto is disposed on the other side of the chip 100 near the lower side of FIG. Furthermore, the first power supply pad 131 is disposed at a position slightly to the right from the left end of the lower side of the chip 100 in FIG. 2, while the second power supply pad 132 is the chip in FIG. 2. It is arrange | positioned in the position slightly to the left from the right end of the lower side of 100. Therefore, it is possible to arrange the power supply pads 131 and 132 in a rotationally symmetrical manner with respect to the center of the internal circuit 104.

The pad power supply wirings 115 and 116 are disposed under and past the passivation layer forming the uppermost surface of the chip 100, and the X decoder 102 is provided through the power supply terminals 111 and 112 of the internal circuit 104. And a P-channel MOS transistor Qp (see FIGS. 3 and 4) corresponding to each of the power supply pads 131 and 132 as well as connected to the Y decoder 103, as described later. It is a nearly straight metal wire having a material such as aluminum.

The second pad part 106 includes a pair of ground (Vss) connection pads 133 and 134 connected (wire bonded) to the lead frame 123 connected to the ground pins (Vss) 10P and 24P. Two parallel sides between the ground connection pads 133 and 134 and the internal circuit 104 are disposed in parallel with each other on the two opposite sides of the internal circuit 104, that is, the upper and lower sides in FIG. Pad ground wirings 117 and 118 are provided.

Among them, the first ground connection pad 133 and the pad ground wiring 117 corresponding thereto are arranged on one side of the chip 100 near the upper side in FIG. 2, while the first ground connection pad 134 is connected to the second ground connection pad 134. The pad ground wiring 118 corresponding thereto is disposed on the other side of the chip 100 near the lower side in FIG.

The first ground connection pad 133 is disposed slightly to the left from the right end of the upper side of the chip 100 in FIG. 2, while the second ground connection pad 134 is disposed in the chip 100 in FIG. 2. It is arrange | positioned in the position slightly right from the left end of a lower side. Therefore, it is possible to arrange the ground connection pads 133 and 134 in rotationally symmetry with respect to the center of the internal circuit 104.

The pad ground wirings 117 and 118 are disposed under the protective film forming the uppermost surface of the chip 100, and are disposed through the X decoder 102 and the ground connection terminals 113 and 114 of the internal circuit 104. Aluminum not only connected to the Y decoder 103 but also connected to the N-channel MOS transistor Qn (see FIGS. 3 and 4) corresponding to each of the ground connection pads 133 and 134 as described later. It is an almost straight metal wire having the same material.

In FIG. 2, the power supply pad 131 and the ground connection (Vss) pad 133 disposed on the first side of the internal circuit 104, that is, the upper side, are spaced apart from each other by a predetermined distance, thereby An output pad (second pad) 121 is formed between the power supply pad 131 and the ground connection (Vss) pad 133. Furthermore, in FIG. 2, the power supply pads 132 and the ground connection (Vss) pads 134 disposed on the second side and the lower side of the internal circuit 104 are spaced apart by a predetermined distance, thereby providing a plurality of output pads ( The second pad 122 is formed between the power supply pad 132 and the ground connection (Vss) pad 134. The output pads 121 and 122 that receive the head address at the first access to the memory cell array of the chip 100 are dual purpose pads (hereinafter referred to as I / I) that perform functions as both address input and data output pads. O pad). Each of the I / O pads 121 and 122 is connected to a contact between a source and a drain of a P-channel MOS transistor Qp or an N-channel MOS transistor Qn, as shown in FIGS. 3 and 4. do. Pad power supply wirings 115 and 116 are connected to P-channel MOS transistors Qp, respectively, while pad ground wirings 117 and 118 are connected to N-channel MOS transistors Qn, respectively. As shown in FIG. 5, the I / O pads 121 and 122 are wire-bonded to one corresponding lead frame 123 by the bonding wires 124 to form external connection pins (I / O pins) ( 1P to 4P, 11P to 14P, 15P to 18P, and 25P to 28P.

The power supply pad 131 formed on the first side (upper side in FIG. 2) of the internal circuit 104 and the ground connection (Vss) pads formed on the second side (lower side in FIG. 2) are the internal circuit 104. Reverse each other through On the other hand, the power supply pad 132 formed on the second side (lower side in FIG. 2) of the internal circuit 104 and the ground connection (Vss) pad 133 formed on the first side (upper side in FIG. 2) Are reversed from each other through the internal circuit (104). Therefore, the first and second pad portions 105 and 106 may be disposed and formed in a rotational symmetry with respect to the central portion of the internal circuit 104.

Referring to FIG. 2, reference numeral 135 denotes a chip enable pin (/ CE) 20P, a read pin (/ RD) 23P, an ALEL pin 6P, and an ALEH pin 9P in an internal circuit 104. ), An input pad (first pad) for inputting the / CE signal, the / RD signal, the ALEL signal, and the ALEH signal. The input pad 135 is separated from the I / O pads 121 and 122 to the power supply pads 131 and 132 and the ground connection (Vss) pads 133 and 134 and disposed at left and right ends thereof.

<How to use>

When using the semiconductor device having the above structure, X of the internal circuit 104 through the lead frame 123, the bonding wire 124, the power supply pads (131, 132) and the pad power supply wirings (115, 116). In order to supply power to the decoder 102 and the Y decoder 103 and to supply power to the P-channel MOS transistors Qp such as the I / O pads 121 and 122, an external power source is supplied with a power supply pin Vcc. ) 5P, 19P. In order to access the desired memory cell, the initial addressing is done through the I / O pins (1P-4P, 11P-14P, 15P-18P, 25P-28P), and then the data of the accessed memory cell is Output is via the / O pins (1P-4P, 11P-14P, 15P-18P, 25P-28P). In subsequent addressing, since address increment is performed inside the chip 100, address shifting is automatically performed. Current used in the N-channel MOS transistor Qn of the internal circuit 104, the ground connection pads 133 and 134, and the like, are the pad ground wirings 117 and 118, the ground connection (Vss) pads 133 and 134, and the bonding wires. Discharges to the outside from the ground pins (Vss) 10P and 24P through the 124 and the lead frame 123.

In this case, the pad power supply wirings 115 and 116 and the pad ground wirings 117 and 118 should be wire bonded to each of the lead frames 123 from the two reverse sides of the internal circuit 104, but the internal circuit 104 Since the power supply terminals 111 and 112 and ground connection terminals 113 and 114 of the &lt; RTI ID = 0.0 &gt;) are disposed on two reverse side (upper and lower side) of the internal circuit 104, &lt; / RTI &gt; It is not necessary to pass 118) through the two sides. That is, the pad power supply wirings 115 and 116 and the pad ground wirings 117 and 118 can be connected to the external connection pins without covering these wirings 115 to 118 over the entire peripheral portion of the internal circuit 104. Therefore, the chip size can be reduced. In particular, when increasing the widths of the pad power supply wirings 115 and 116 and the pad ground wirings 117 and 118 in order to keep the wiring resistance (impedance) at a low level, the second embodiment described later (see: Sixth) Considerable space is required in the side walls of the chip 100 as shown in FIG. However, in the structure according to the present embodiment shown in FIG. 5, the pad power supply wirings 115 and 116 and the pad ground wirings 117 and 118 and the chip (between the left and right sides of the internal circuit 104). Since the wirings of 100 can be omitted, a significant space can be reduced.

The first power supply pin (Vcc) 5P is disposed on either side of the package 101 and the second power supply pin (Vcc) 19P is disposed on the other side of the package 101, while the first ground Since the pin (Vss) 10P is disposed on one side of the package 101 and the second ground pin (Vss) 24P is disposed on the other side of the package 101, the package 101 can be freely drawn out. Since both the power supply pins Vcc and the ground pins Vss can be taken out from both sides of the lateral side, the degree of freedom in the wiring design can be improved.

When the I / O pads 121 and 122 are connected as shown in FIGS. 3 and 4, the current changes significantly during switching of the P-channel MOS transistor Qp and the N-channel MOS transistor Qn. This, on the one hand, generates response noise. If such noise is introduced into the input pad 135, the semiconductor memory device may malfunction. However, according to the present embodiment, the input pad 135 is separated from the I / O pads 121 and 122 through the power supply pads 131 and 132 and the ground connection (Vss) pads 133 and 134. Thus, even if noise occurs within the I / O pads 121 and 122, the input pad 135 is isolated from the noise by the power supply pads 131 and 132 or the ground connection (Vss) pads 133 and 134. As a result, not only a malfunction of the semiconductor memory device but also a bad effect caused by noise can be prevented.

Furthermore, the power supply terminals 111 and 112 and the ground connection terminals 113 and 114 are arranged rotationally symmetric about the center of the internal circuit 104, while the corresponding ones of these terminals 111 and 114 are mutually opposite. Since it is opposed, for example, to supply power to a peripheral circuit such as a sense circuit, power supply or ground connection can be performed from any terminal regardless of the arrangement of the peripheral circuit. Therefore, the degree of freedom in circuit design is remarkably improved, and the integration efficiency can be improved by reducing the wiring length or the like therebetween.

Furthermore, the surplus pins (NC) 7P, 8P, 21P, 22P are disposed at positions between the power supply pins Vcc and the ground pins Vss along the sides 126, 127 of the package 101, If the 100 is arranged to coincide with these positions, there is no need to wire the chip 100 and the surplus pins NC 7P, 8P, 21P, 22P. Therefore, unlike the prior art, it is not necessary to form a plurality of rows of pads on each side of the chip 100 to prevent the bonding wires from being shorted. Therefore, since the array and peripheral circuits (the X decoder 102 and the Y decoder 103) of a perfect square up to the end of the chip 100 can be formed, the integration efficiency can be improved as compared with the prior art.

Second Embodiment

<Structure>

6 shows a semiconductor device according to a second embodiment of the present invention. In the semiconductor device according to the present embodiment, a plurality of pads are arranged on four side surfaces of the internal circuit 104 compared to the area of the internal circuit 104. The remaining configuration is similar to that of the first embodiment, in particular, in that the I / O pads 121 and 122 and the input pad 135 are electrically isolated from each other through the power supply pads 131 and 132. Components having the same functions as those of the first embodiment are denoted by the same reference numerals. According to the present embodiment, the reduction in chip size is limited by the pad power supply wirings 115 and 116 and the pad ground wirings 117 and 118 disposed on the left and right sides of the internal circuit 104. Similar to the first embodiment, noise that may be introduced from the input pad 135 to the I / O pads 121 and 122 by the power supply pads 131 and 132 or the ground connection (Vss) pads 133 and 134. It is possible to separate. Therefore, the influence on the input pad 135 by the noise introduced into the I / O pads 121 and 122 can be reduced.

Third Embodiment

<Structure>

7 shows a semiconductor device according to a third embodiment of the present invention. The semiconductor device according to the present embodiment, which is a conventional 4-megabit mask ROM, does not have the I / O pin (which serves as the address input and data output pins) described with reference to the first embodiment or the like, The data output is generated from the output pins D0 to D7. Referring to FIG. 7, reference numeral Vcc denotes a power supply pin similar to that described with reference to the first and second embodiments, reference numeral Vss denotes a ground pin, reference numerals A0 to A16 denote address input pins, and NC denotes a surplus pin and the symbols / CE and / RD represent the control signal input pins. Of course, by using a similar internal structure, effects similar to those of the above embodiments can be obtained.

[Example 4]

<Structure>

8 shows a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device according to the present embodiment does not include the surplus pins NC that are not connected to the outside among the external connection pins 1P to 24P. Therefore, it is necessary to wire bond all external connection pins 1P to 24P, so that when the centers of both sides of the package 101 approach the side sides of the internal circuit 104, ALEH, ALEL, / CE and / RD The pads connected to the pins are arranged in two rows similarly to the second embodiment shown in FIG. 6, thereby lowering the integration efficiency in the array structure. However, except for this point, an effect similar to that of the first embodiment can be obtained.

[Modification]

(1) In the first embodiment, only one pad of the power supply pads 131 and 132 and one pad of the ground connection (Vss) pads 133 and 134 have two reverse sides ( Although arranged on the upper and lower sides in FIG. 2, a plurality of pads may be selectively installed on each side.

(2) For the first embodiment, the structure shown in FIG. 1 can be replaced with the structure shown in FIG.

Although the present invention has been described and illustrated in detail, the foregoing description is for illustrative purposes only and is not intended to be limiting. Thus, it is apparent that various modifications and changes can be made without departing from the scope of the present invention.

According to claims 1 to 6 of the present invention, since the surplus pin is disposed at a position between the power pin and the ground pin of one side and the reverse side of the package, when the chip is placed at a position corresponding to the position, Since there is no need to arrange the surplus pins, it is not necessary to form a plurality of rows of pads in the corners of the chip to prevent bonding and shorting of the wires as in the conventional example. As a result, a flawless quadrangular array or the like can be configured up to the end of the chip, thereby improving the area efficiency compared to the conventional example.

According to claim 2 of the present invention, since the power supply terminal and the ground connection terminal of the internal circuit are arranged on two opposite sides of the internal circuit, the wiring for the pad power wiring and the pad ground wiring are connected between the two sides. There is no need to do it. That is, the external connection pins can be connected on two opposite sides of the internal circuit without surrounding the pad power wiring and the pad ground wiring on the entire peripheral surface of the internal circuit. Therefore, the chip size can be reduced by that amount.

According to claim 3 of the present invention, one power pin is disposed on one side of the package, the other power pin is disposed on the reverse side of the package, and one ground pin is placed on one side of the package, Since the other ground pin is arranged on the reverse side of the package, both of the power pin and the ground pin can be pulled out from both sides of the package. In the case of claim 2, the wiring between the power pad and the power pin and The wiring between the ground pad and the ground pin can be easily performed, which increases the degree of freedom in wiring design.

According to claim 4 of the present invention, since one of the first pad and the second pad and the other pad are arranged with the power supply pad or the ground connection pad floating thereon, even if noise is mixed in one pad, The pad on the side can be separated into a pad for power supply or a pad for ground connection.

According to claim 5 of the present invention, since two or more power supply terminals are arranged on the reverse side of the internal circuit diagonally, and two or more ground connection terminals are arranged on the reverse side of the diagonal different from the power supply terminal of the internal circuit. There is an effect that the degree of freedom in design is increased for any wiring outside the wiring and the chip in the internal circuit.

Claims (6)

A chip and a package for accommodating the chip, and having a plurality of external connection pins provided on two opposite sides of the package, the external connection pins being opposed to each other in the package to supply power to the chip. A power pin formed on each of the two sides, a ground pin formed on each of the two opposite sides of the package for connecting the chip to the ground, and an excess pin not connected to the outside; A semiconductor device interposed between the power supply pin and the ground pin at each of the two opposite sides of the semiconductor device. A package, and a chip housed inside the package, wherein the package has a plurality of external connection pins formed of two sides facing each other, including a power pin and a ground pin, and the chips having two opposite sides. An internal circuit having at least one power supply terminal and a ground connection terminal at each side, a first pad portion for engaging the internal circuit and the power pin, and a second pad for engaging the ground pin with the internal circuit And a first pad part comprising: at least one power pad formed on two opposite sides of the chip so as to be wired between the power supply terminal and the power pin of the internal circuit; A pad power wiring arranged in parallel to the side and connected to the respective power pads, wherein the second pad portion is formed of the internal circuit. At least one ground connection pad formed on two opposite sides of the chip so as to be wired between the ground connection terminal and the ground pin, and disposed in parallel in the vicinity of two opposite sides of the internal circuit, the respective ground connections And a pad ground wire connected to the pad for the pad. According to claim 2, Of the external connection pin, one power pin is disposed on any one side of the package, and the other power pin is disposed on the reverse side of the package, One of the external connection pins, The ground pin of the semiconductor device is disposed on one side of the package, and the other ground pin is disposed on the reverse side of the package. The chip according to claim 2 or 3, wherein at least one side of the chip is provided with a first pad used only for inputting a predetermined signal to the chip, and at least a second pad used for outputting a signal from the chip. And the power pad and the ground connection pad disposed on the at least one side where the second and first pads of the chip are spaced apart from each other by a predetermined distance, and the second and second pads between the power pad and the ground connection pad. One pad of the first pads is disposed, and the other pad of the second and first pads is disposed at an end by lifting the power pad or the ground connection pad from the one pad. Semiconductor device. 4. The power supply terminal of claim 3, wherein the first power supply terminal formed on one side of the internal circuit and the ground connection terminal formed on the other side of the reverse side are disposed to face each other, and to the other side of the internal circuit. And the other power supply terminal formed and the other ground connection terminal formed on the one side are disposed to face each other. According to claim 2 or 3, wherein the external connection pin has a surplus pin that is not connected to the outside, the surplus pin is sandwiched between the power pin and the ground pin on each of the one side and the reverse side The semiconductor device characterized by the above-mentioned.