GB2170657A

GB2170657A - Semiconductor memory device

Info

Publication number: GB2170657A
Application number: GB8502915A
Authority: GB
Inventors: Robert William Hunt
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1985-02-05
Filing date: 1985-02-05
Publication date: 1986-08-06
Also published as: GB2170657B; GB8502915D0

Abstract

A memory device comprises a plurality of functional or part functional memory chips mounted on a common carrier. The carrier has redundant wiring for coupling to the functional cells of the memory chips. By utilising part functional chips the effective yield of the chip fabrication process is increased.

Description

SPECIFICATION Semiconductor memory device This invention relates to semiconductor memories, and in particular to random access memories.

As the complexity of semiconductor memory circuits increases the yield of fully functional devices decreases rapidly. For example, the step from a 64K random access memory to a 256K memory requires a very high degree of expertise to overcome the yield problem. This problem of low yield is particularly acute where a new circuit is to be manufactured and the necessary processing experience has yet to be gained. Thus, the introduction of a new more complex circuit involves an induction or 'learning' period before the manufacturing process becomes profitable. During this period considerable losses may be incurred.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a memory device, including a plurality of semiconductor memory chips each having memory cells disposed in two or more arrays, and a support structure to which said chips are bonded, wherein said support has a conductor pattern whereby the functional cells of the memory chips may be accessed.

In a memory circuit the majority of the chip area is occupied by memory cells. Thus processing faults occur most commonly in the memory array rather than the control and accessing circuitry. By dividing the array into, typically four, sub-arrays and providing separate access pads to these sub-arrays, circuits that are only partly functional may be utilised.

An embodiment of the invention will now be described with reference to the accom -panying drawings in which: Figure 1 is a schematic diagram of a random access memory; Figure 2 is a plan view of a memory device incorporating a plurality of memories, of the type shown in Fig. 1, and Figure 3 is a sectional view of the memory device of Fig. 2.

Referring to Fig. 1, the memory circuit, e.g.

a 256K dynamic random access memory, has a plurality of memory cells disposed together with their associated sense amplifiers in four similar rectangular arrays 11 to 14. The memory also includes double-sided X-decoders 15, Y-decoders 16, double-sided Y-decoders 17, clocks 18 and common address latches 19.

The operation of these portions of a random access memory is well known in the art.

External connection to the memory arrays 11 to 14 is provided via contact pads 20, one pair from each array of memory cells.

Further contact pads (not shown) are provided for the common address latches 19. It will be clear that a single memory array fault will affect only one of the four arrays of cells. Thus, provided that the control circuitry of the device is functional, the remaining good arrays can still be used for storage. In this event connection is made only to the contact pads coupled to the remaining good arrays and of course, to the control circuitry.

Figs. 2 and 3 show a memory device formed from a plurality of fully functional or part functional memory chips. The device comprises a laminar support member 21 provided with a plurality of output terminals 22.

Memory chips 23 mounted on the support 21 are coupled to the terminals 22 via a conductor pattern (not shown) disposed on the support. The conductor pattern includes bonding pads 24 disposed around the mounting area of each chip and to which the chip contact pads, with the exception of those pads associated with defective memory arrays, are connected. Advantageously the assembly is encapsulated in an insulating plastics housing 25. Preferably the conductor pattern incorporates redundant wiring to facilitate connection to the functional memory arrays.

The assembly functions electrically as a single high capacity memory device. For example, a 576K dynamic RAM may be provided by the following combinations of three fully or part functional chips to provide a total of nine functional arrays: 4+4+1=9 4+3+2=9 3+3+3=9 It will be appreciated that as part functional chips can be utilised the effective yield of the manufacturing process is considerably increased. The technique is not of course limited to dynamic RAM's but can of course also be used with static RAM's where again the memory cells occupy the bulk of the chip area.

The most effective way of utilising the functional and part functional chips will depend on their relative numbers and can be determined by simple linear programming techniques.

Claims

1. A memory device, including a plurality of semiconductor memory chips each having memory cells disposed in two or more arrays, and a support structure to which said chips are bonded, wherein said support has a conductor pattern whereby the functional cells of the memory chips may be accessed.

2. A memory device as claimed in claim 1, wherein said chips comprise random access memories.

3. A memory device as claimed in claim 2, wherein the memory cells of each said chip are disposed in four similar arrays.

4. A memory device as claimed in claim 1, 2 or 3, wherein the support structure is provided with a conductor pattern including redundant wiring whereby connection to the functional memory arrays may be effected.

5. A memory device substantially as de scribed herein with reference to the accom panying drawings.