KR100272266B1 - Thin film transistor and method of manufacturing same - Google Patents

Abstract

PURPOSE: A TFT and a method for fabricating the same are provided to be capable of increasing on current by forming an active layer only on a gate electrode to form a current pass bypassing an amorphous silicon layer having a high specific resistance. CONSTITUTION: A first gate insulating layer(33-1) is formed on a substrate(31) including a gate electrode(32). A second gate insulating layer(33-2) is formed on the first gate insulating layer(33-1) on the gate electrode(32). An active layer(34) is formed on the second gate insulating layer(33-2) to be spaced apart from an edge of the gate electrode(32) by 0.1-1.5 micrometer. Source/drain electrode(37,38) are formed on the first gate insulating layer(33-1) to expose the active layer(34). An ohmic layer(36) is formed between the source/drain electrode(37,38) and the active layer(34) for ohmic contact therebetween. An etch stopper(35) is formed to be spaced apart from the edge of the gate electrode(32) by 1.0-2.0 micrometer.

Description

Thin film transistor and method of manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor-liquid crystal display (TFT-LCD), which is one of flat panel display devices, and more particularly to a thin film transistor capable of increasing on current and a method of manufacturing the same. It is about.

In general, a gate electrode and a source / drain electrode are separated between a thin film transistor used as a pixel electrode driving switching element of a liquid crystal display (LCD) or a semiconductor layer, which is an active layer used for a static random access memory (SRAM) element, interposed therebetween. They are broadly classified into staggered shapes and coplanar shapes in which gate electrodes and source / drain electrodes are formed on one surface of a semiconductor substrate.

In addition, staggered thin film transistors are classified into inverted staggered TFTs whose gate electrodes are located at active charges and normally staggered TFTs whose gate electrodes are located above the active layer. .

Such thin film transistors are classified into thin film transistors using amorphous silicon or polysilicon and thin film transistors using compound semiconductors, depending on the active material.

1 shows a cross-sectional structure of a thin film transistor used in a conventional liquid crystal display device.

Referring to FIG. 1, a gate electrode 12 is formed on a transparent insulating substrate 11 such as a glass substrate, and a gate insulating layer 13 is formed on an insulating substrate 11 on which the gate electrode 12 is formed. .

An active layer 14 of amorphous silicon is formed on the gate insulating layer 13 corresponding to the gate electrode 12, and an etch stopper 15 is formed on the active layer 14 corresponding to the gate electrode 12. Is formed.

Source / drain electrodes 17 and 18 are formed between the active layer 14 and the gate insulating layer 13 so that the top surface of the etch stopper 15 is exposed. The source / drain electrodes 17 and 18 and the active layer are formed. An ohmic layer 16 made of doped amorphous silicon or the like is formed between the fourteen and the passivation layer 19 as a protective film over the entire surface of the substrate.

In the conventional thin film transistor having the structure as described above, when a predetermined voltage is applied to the gate electrode 12, a channel layer is formed on the active layer 14 above the gate electrode 12 by a voltage applied to the gate electrode 12. Become organic.

At this time, the width of the gate electrode 12 is formed to be relatively smaller than the width of the active layer 14 thereon, so that the channel layer according to the voltage applied to the gate electrode 12 is formed under the source / drain electrodes 16 and 17. The active layer 14 is free from the channel layer.

Accordingly, according to the formation of the channel layer, a current path is formed in which a current flows from the source electrode 17 to the drain electrode 18 through the channel layer induced by the voltage of the gate electrode 12. As shown in FIG. 1, the source electrode 17 → the ohmic layer 16 → the active layer 14 under the source electrode 17 → the channel layer induced by the voltage applied to the gate electrode 12 is lower than the drain electrode. The current path is formed such that current flows from the active layer 14 to the ohmic layer 16 to the drain electrode 18.

Thus, when current flows through the thin film transistor, current flows through the active layer 14 below the source / drain electrodes 16 and 17 where the channel layer is not formed, wherein the active layer without the channel layer is amorphous. Since the silicon layer has a high specific resistance close to the insulator, it is a major factor in reducing the on-current flowing through the thin film transistor.

As the on-current of the thin film transistor decreases due to the above factors, sufficient charge cannot be supplied to the liquid crystal, thereby degrading the image quality of the liquid crystal display device.

In addition, as described above, since the width of the active layer 14 is larger than the width of the gate electrode 12, light from the backlight is incident on the active layer 14 without being completely blocked by the gate metal 12, and thus the active layer 14 is formed. Current flows through), which is a major factor in increasing the off current of the thin film transistor.

Therefore, since the off current flowing through the thin film transistor acts as a leakage current to drop the voltage applied to the liquid crystal, there is a problem that adversely affects the image quality.

The present invention is to solve the problems of the prior art as described above, the present invention forms an active layer only on the gate electrode to form a current path so that the current flows without passing through the amorphous silicon layer having a high specific resistance, the on-current It is an object of the present invention to provide a thin film transistor and a method of manufacturing the same that can raise the.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which can prevent an increase in off current caused by a backlight by completely blocking light from a backlight incident to the active layer by a gate electrode.

In addition, an object of the present invention is to provide a thin film transistor and a method for manufacturing the same that can improve the image quality by increasing the on / off current ratio.

1 is a cross-sectional structure diagram of a thin film transistor according to the prior art.

2 is a cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention.

3 (a) to 3 (d) are sectional views of the manufacturing process of the thin film transistor of FIG.

* Explanation of symbols for main parts of the drawings

31: insulated substrate 32: gate

33-1: first gate insulating film 33-2: second gate insulating film

34: active layer 35: etch stopper

36: ohmic layer 37: source electrode

38: drain electrode 39: passivation charge

The present invention for achieving the above object; A gate electrode formed on the substrate; A first gate insulating film formed on the substrate including the gate electrode; A second gate insulating film formed on the first gate insulating film over the gate electrode; An active layer formed on the gate insulating film 0.5-1.5 μm away from an edge of the gate electrode; A source / drain electrode formed on the first gate insulating layer to expose an upper surface of the active layer; An ohmic layer formed therebetween for ohmic contact between the source / drain electrode and the active layer; It provides a thin film transistor comprising an etch stopper formed between 1.0-2.0㎛ from the edge of the gate electrode between the active layer.

In an embodiment of the present invention, the first gate insulating film has a thickness of 3000 to 500 GPa with SiON or SiO _x , and the second gate insulating film has a thickness of 300 to 500 GPa with SiN _x .

The present invention includes forming a gate electrode on a substrate; Forming a first gate insulating film, a second gate insulating film, and an active layer on the substrate including the gate electrode; Forming a silicon nitride film on the active layer; Exposing the silicon nitride film to the back or front to form an etch stopper 1.0-2.0 μm away from an edge of the gate electrode; Etching the active layer and the second gate insulating layer by front exposure or back exposure to form an active layer and the second gate insulating layer 0.5-1.5 μm away from an edge of the gate electrode; Depositing an ohmic layer and a metal for source / drain electrodes on the entire surface of the substrate; Patterning the metal to form a source / drain electrode; And etching the ohmic layer so that the active layer between the source and drain electrodes is exposed.

EXAMPLE

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a cross-sectional structure of a thin film transistor according to an embodiment of the present invention. 2, the thin film transistor according to the embodiment of the present invention is a metal such as MoTa, MoW, or Cr on a transparent insulating substrate 31, such as a glass substrate, the gate electrode having a thickness of 2000 ~ 3000 전극 32 is formed.

A double-layered gate insulating film 33 is formed on the insulating substrate 31 including the gate electrode 12. The first gate insulating film 33 made of an insulating film, such as SiO _x or SiON, is formed in the gate insulating film 33. -1 is formed entirely on the insulating substrate 31 including the gate electrode 32, and the second gate insulating film 33-2 of the thin film made of an insulating film such as SiN _{x is} formed on the first gate insulating film 33 on the gate. It is formed only on -1). Here, the first gate insulating film 33-1 has a thickness of about 3000 to 5000 GPa, and the second gate insulating film 33-2 has a relatively thin thickness of about 300 to 500 GPa.

Further, in the embodiment of the present invention, an active layer 34 of a thin film of an amorphous silicon film having a thickness of 400-600 Å is formed only on the second gate insulating film 33-2, so that the gate electrode 32 The width of the active layer 34 is smaller than the width.

An etch stopper 35 is formed on the active layer 34, and source / drain electrodes 37 and 38 are formed on the gate insulating layer 33 so that the top surface of the etch stopper 35 is exposed. An ohmic layer 36 made of doped amorphous silicon or the like is formed between the drain electrodes 37 and 38 and the active layer 34, and a passivation layer 39 is formed as a protective film over the entire surface of the substrate.

In the thin film transistor of the present invention having the structure as described above, when a constant voltage is applied to the gate electrode 12, the channel layer is induced in the active layer 34 by the voltage applied to the gate electrode 12.

As the channel layer is formed, current is drained through an interface between the channel layer, that is, the second gate insulating layer 33-2 and the active layer 34, induced by the voltage applied from the source electrode 37 to the gate electrode 32. A current pass through the electrode 38 is formed.

That is, since the width of the active layer 34 is smaller than the width of the gate electrode 32 and the active layer 34 is formed only on the gate electrode 32, the current flowing from the source electrode 37 to the drain electrode 38 is The on-current is increased because the resistive component flows without passing through the high active layer.

The manufacturing method of the thin film transistor as described above will be described with reference to FIGS. 3A to 3D.

First, as shown in FIG. 3 (a), MoTa, MoW, Cr, etc. are deposited on the insulating substrate 31 such as a transparent glass substrate using a sputter at a thickness of 2000 to 3000 mm as a gate electrode metal. The gate electrode 32 is formed by patterning using a photolithography method using a conventional gate mask (first mask, not shown in the drawing).

Subsequently, as shown in FIG. 3 (b), SiO _x is used as the first gate insulating film 33-1, SiN _x is used as the second gate insulating film 33-2, and the active layer 34 using PECVD or APCVD. SiN _x is deposited to a thickness of 3000 to 5000 kPa, 300 to 500 kPa, 400 to 600 kPa, 3000 kPa with a-Si and etch stopper 35).

No. 3 (c) also, the etch stopper mask (the second mask, not shown formed on the figure) over the exposure or etch stopper 35 is subjected to back exposure to pattern the SiN _x for the etch stopper by using the steps shown in To form. At this time, the exposure conditions are adjusted so that the etch stopper 35 is formed 1.0 to 2.0 占 퐉 away from the edge of the gate electrode 32.

Subsequently, the active layer 34 is formed by etching the a-Si by performing front or rear exposure using an active mask (third mask, not shown in the drawing). At this time, the active layer 34 is formed only on the gate electrode 32 by patterning the active layer 34 away from the edge of the gate electrode 32 by adjusting the exposure conditions.

SiN _x , which is the second gate insulating film 33-2, is simultaneously etched when a-Si is etched for the active layer 34, and the thickness of SiN _x , which is the second gate insulating film 33-2, is only about 300 to 500 μm. In addition, since the thickness of SiO _x , which is the first gate insulating layer 33-1, is 300 to 5000 식, an etching selectivity sufficient to etch only the second insulating film 33-2 with respect to the first gate insulating layer 33-1. It can have Here, SiON may be formed instead of SiN _x as the second gate insulating layer 33-2.

Subsequently, although not shown in the drawing, a pixel electrode ITO film is deposited by a sputtering method, and a pixel electrode is formed by patterning an ITO phase film using a pixel electrode mask (fourth mask). Then, a PAD forming process for applying a signal from the outside is performed using a contact mask (a fifth mask, not shown in the figure).

An n ⁺ a-Si film 36 was deposited on the entire surface of the substrate, and the source / drain electrode metal was sputtered thereon, and a source / drain mask (sixth mask, not shown in the drawing) was used. The metal is patterned to form source / drain electrodes 37 and 38.

After forming the source / drain electrodes 37 and 38, the exposed n + a-Si film 36 is dry etched to electrically separate them, thereby exposing the top surface of the etch stopper 35.

Subsequently, a passivation layer 39 as a protective film is deposited by PECVO, and a passivation film is patterned using a passivation mask (seventh mask, not shown in the figure) to manufacture a thin film transistor according to an embodiment of the present invention.

According to the present invention as described above, since the active layer is formed only on the gate electrode, the current flows from the source electrode to the drain electrode only through the channel layer and not through the amorphous silicon layer having a high resistivity, thereby increasing the on-current.

In addition, generation of photocurrent in the active layer by the backlight can be suppressed to reduce the off current.

Therefore, the on / off current ratio is increased, so that sufficient charge can be supplied to the pixel electrode, thereby improving the image quality.

Claims (10)

Substrate; A gate electrode formed on the substrate; A first gate insulating film formed on the substrate including the gate electrode; A second gate insulating film formed on the first gate insulating film over the gate electrode; An active layer formed on the gate insulating film 0.5-1.5 μm away from an edge of the gate low electrode; A source / drain electrode formed on the first gate insulating layer to expose an upper surface of the active layer; An ohmic layer formed therebetween for ohmic contact between the source / drain electrode and the active layer; And an etch stopper formed between 1.0-2.0 μm from an edge of the gate electrode between the active layers. The thin film transistor of claim 1, wherein the first gate insulating layer is one of SiON or SiO _x . The method of claim 1, wherein the first gate insulating layer is 3000. A thin film transistor having a thickness of from about 5000 kPa. The foil of claim 1, wherein the second gate insulating layer is SiN _x . Membrane transistor. The thin film transistor according to any one of claims 1 to 4, wherein the second gate insulating film has a thickness of 300 to 500 kW. The thin film transistor of claim 1, wherein the substrate is a transparent glass substrate. The thin film transistor of claim 1, further comprising a passivation film formed on the front surface of the substrate as a passivation film. Forming a gate electrode on the substrate; Forming a first gate insulating film, a second gate insulating film, and an active layer on the substrate including the gate electrode; Forming a silicon nitride film on the active layer; Exposing the silicon nitride film to the back or front to form an etch stopper 1.0-2.0 μm away from an edge of the gate electrode; Etching the active layer and the second gate insulating layer by front exposure or back exposure to form an active layer and the second gate insulating layer 0.5-1.5 μm away from an edge of the gate electrode; Depositing an ohmic layer and a metal for source / drain electrodes on the entire surface of the substrate; Patterning the metal to form a source / drain electrode; Etching the ohmic layer to expose the active layer between the source and drain electrodes. 10. The method of claim 8, wherein one of SiON and SiO _x is formed to a thickness of 3000 to 5000 kW as the first gate insulating film. The method of claim 8 wherein the method of manufacturing a thin film transistor, characterized in that for forming the SiN _x as the second gate insulating film thickness of 300 to 500Å.

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