KR100271298B1 - A handling unit and a handling method of the l1, l2,l3 bits of lower-order path overhead in synchronous transfer mode communication - Google Patents

Abstract

PURPOSE: An L1, L2 and L3 bit processing unit and a processing method of a low-level path overhead in synchronous transfer mode communication are provided to improve interface between old and new devices by recognizing the "1" logic value signal as low-level path. CONSTITUTION: A low-level path overhead input unit(210) receives low-level overhead 8 bit logic values and transmits nos. 5, 6 and 7 bit used as signal of low-level connection. A "000" detector(220) judges whether the bit logic value of the nos. 5, 6 and 7 bit is "000". A "010" detector(230) judges whether the bit logic value of the nos. 5, 6 and 7 bit is "010". A "001" detector(240) judges whether the bit logic value of the nos. 5, 6 and 7 bit is "001". A first memory element(250) outputs the output value of the "000" detector(220). A second memory element(260) outputs the output value of the "010" detector(230). A third memory element(270) outputs the output value of the "001" detector(240). A "mismatch" detector(280) judges whether the output values of the memory elements(250,260,270) are identical or not.

Description

A handling unit and a handling method of the L1, L2, L3 bits of lower-order path overhead in synchronous transfer in communication by the synchronous transfer method. mode communication)

The present invention relates to a L1, L2 and L3 bit processing apparatus and processing method of the low path overhead in the communication by the synchronous transmission method, in particular a synchronous transmission method which is a transmission method based on the synchronous digital hierarchy (Synchronous Digital Hierarchy) The devices that are connected to each other by using a different path are different for the L1, L2, and L3 bits of the low path overhead, which is the path overhead of the Virtual Box (VC) -1 or VC-2. Even in the case of a structure, the present invention relates to L1, L2, and L3 bit processing apparatus and processing method of a low path overhead that enables an inter-device interface.

Conventionally, when the L1, L2, and L3 bits of the low path overhead have a logic value of "0", it is determined as the "Unequip" state meaning that there is no low path, and the L1, L2, and L3 bits are "10". If it has a logic value of "," it is determined to be a normal state, and if the bits L1, L2, and L3 have a logic value other than "10", the "mismatch" state means that the connection between paths does not match. Judging by However, if the L1, L2, and L3 bits are "1", it is not actually a "mismatch" state, but rather a device that can use only 0 or 1 and conveys 8 situations using the L1, L2, and L3 bit modes. It is a condition that occurs when connecting between new devices with a function. Therefore, even when the L1, L2, and L3 bits are "1", it is determined that the low path is connected, and the signal must be passed. Judging by the state there was a problem that the signal does not pass.

Accordingly, the present invention has been made to solve the above problems, and the logic values of L1, L2, and L3 bits of low path overhead are " 1 " The present invention provides an apparatus and method for recognizing that the low path is connected even when a signal is reached, that is, the L1, L2 and L3 bit processing devices and the processing method of the low path overhead in the communication by the synchronous transmission method. have.

In order to achieve the above object, the L1, L2, and L3 bit processing apparatus of the low path overhead in the communication by the synchronous transmission method according to the present invention inputs a logic value of 8 bits of the low path overhead, A low path overhead input unit for extracting and outputting bits 5, 6 and 7; The low path overhead input unit receives the 5th, 6th, and 7th bits of the low path overhead to determine whether the logical values of the bits are "0" in order, and "0" and "0" Otherwise, a "0" detector for outputting different logic values; The low path overhead input unit receives the 5th, 6th, and 7th bits of the low path overhead to determine whether the logical values of the bits are "10" in order, and "10" and "10" Otherwise, a "10" detector for outputting different logic values; The low path overhead input unit receives the 5th, 6th, and 7th bits of the low path overhead to determine whether the logical values of the bits are "1" in order, and "1" and "1" Otherwise, a " 1 " detector for outputting different logic values; A memory device for storing an output value of the "0" detector; A memory device for storing an output value of the "10" detector; A memory device for storing an output value of the "1" detector; And an "mismatch" determination unit for outputting different logic values when the output values of the memory devices are all the same and otherwise, and the L1, L2, and L3 bit processing of the low path overhead is performed. The method includes receiving a low path overhead signal (step S310); Determining whether logical values of bits 5, 6, and 7 of the low path overhead received from step S310 are "0" in order (S320); Judging that the logical values of bits 5, 6, and 7 of the low path overhead are "0" in order, as a result of the determination in step S320 (step S350); As a result of the determination in step S320, if the logical values of bits 5, 6, and 7 of the low path overhead are not "0" in order, 5, 6, and 7 of the low path overhead Determining whether the logical values of the bits are "10" in order (step S330); If the logical value of bits 5, 6, and 7 of the low path overhead is "10" in order, as a result of the determination in step S330, determining a normal state (step S360); As a result of the determination in step S330, if the logical values of bits 5, 6, and 7 of the low path overhead are not "10" in order, 5, 6, and 7 of the low path overhead Determining whether the logical values of the bits are "1" in order (step S340); As a result of the determination in step S340, if the logic values of bits 5, 6, and 7 of the low path overhead are "1" in order, passing the input signal as it is (step S370); And if the logical values of bits 5, 6, and 7 of the low path overhead are not "1" in order as a result of the determination in step S340 (step S380), Characterized in that it comprises a.

1 is a structural diagram of VC-11, VC-12, and VC-2 of a synchronous multiplexing structure;

2 is a block diagram of a L1, L2 and L3 bit processing apparatus of low path overhead according to the present invention;

3 is a flowchart illustrating a method for processing L1, L2, and L3 bits of low path overhead according to the present invention.

* Explanation of symbols for main parts of the drawings

125,126,127: L1, L2, and L3 bits of low path overhead

200: L1, L2, and L3 bit processing units with low path overhead

210: Low path overhead input unit 220: "0" detection unit

230: "10" detector 240: "1" detector

250, 260, 270: memory device 280: mismatch determination unit

1 is a structural diagram of VC-11, VC-12, and VC-2 in a synchronous multiplexing structure in communication using a synchronous transmission method. VC-11 is a virtual box when the signal mapped to the virtual box 100: VC is a DS1 signal, and VC-12 is a virtual box when the signal mapped to the virtual box 100 is a DS1 / E signal. In the case of VC-11, it has 26 bytes of data, in the case of VC-12, it has 35 bytes of data, and in the case of VC-2, it has 107 bytes of data.

Also, all of VC-11, VC-12, and VC-2 have one byte of path overhead, which is the low path overhead 110.

Bit 1 121 and Bit 2 122 of the low path overhead 110 are information on bit shift even check, Bit 3 123 is Far End Block Error information, 4 Bit 124 is path trace information, Bit 5 125, Bit 6 126, Bit 7 127 is information for signal labeling, Bit 8 is 128 Far End Receive Failure information.

2 is a block diagram of the L1, L2, and L3 bit processing apparatus 200 of the low path overhead according to the present invention. The low path overhead input unit 210 inputs a value of 8 bits of low path overhead. Bits 5, 6 and 7 are extracted and output to the "0" detector 220, the "10" detector 230, and the "1" detector 240.

The "0" detector 220 receives the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210 by using the clock signal from the bit clock unit 211. It is determined whether the logic values are "0" in order, and if it is "0", the logic value '1' is inputted into the memory device A 250. Otherwise, the logic value '0' is inputted to the memory device A 250. ). Then, by using the clock signal of the clock unit 212, a logic value possessed by the memory device A is output. When the output value is examined and the logic value is '1', it is determined as an "unequip" state.

The "10" detecting unit 230 receives the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210 using the clock signal from the bit clock unit 211 to determine the bits of the bit. It is determined whether the logic values are "10" in order, and if the result is "10", the logic value "1" is input to the memory element B 260, otherwise the logic value "0" is input to the memory element B (260). ). Then, by using the clock signal of the clock unit 212, a logic value possessed by the memory element B is output, and when the output value is examined and has a logic value of '1', it is determined as a normal state.

The detection unit 240 receives the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210 by using the clock signal from the bit clock unit 211. It is determined whether the logic values are "1" in order, and if the result is "1", the logic value "1" is input to the memory device C 270, otherwise, the logic value "0" is input to the memory device C (270). ). Then, by using the clock signal of the clock unit 212, a logic value possessed by the memory device C is output. When the output value is examined and the logic value is '1', it is determined that the input signal is passed as it is.

The NOR gate, which is the mismatch determination unit 280, has an output value '1' when the output values of the memory device A, the memory device B, and the memory device C are not all the logic values '1', and otherwise, the output value '0'. The mismatch determination unit 280 has an output value of "1", which is not an "unequip" state, a normal state, and a "mismatch" state, and is determined as a "mismatch" state.

That is, even when the logic values of the 5th, 6th, and 7th bits of the low path overhead are "1" in order, they are not determined as "mismatch" state, and the input signal is passed as it is.

3 is a flowchart illustrating a method for processing L1, L2, and L3 bits of the low path overhead in the synchronous transmission method according to the present invention, the step of receiving a low path overhead signal (step S310) and step S310; Determining whether the logic values of bits 5, 6, and 7 of the low path overhead inputted from step S0 are in sequence (S320), and as a result of the determination in step S320, step 5 of the low path overhead; If the logical values of bits 6, 7, and 7 are "0" in order, it is determined as "unequip" state (step S350). As a result of the determination in step S320, 5, 6, of the low path overhead, And if the logic value of bit 7 is not "0" in order, determining whether the logic values of bits 5, 6, and 7 of the low path overhead are "10" in order (step S330), As a result of the determination in step S330, the logical values of bits 5, 6, and 7 of the low path overhead are sequentially " 10 ", if the logical value of the 5th, 6th, and 7th bits of the low path overhead is not" 10 "in order, the result of the determination in the normal state (step S360) and step S330; Judging whether the logic values of bits 5, 6, and 7 of the path overhead are "1" in order (step S340); as a result of the determination in step S340, 5, 6 of the low path overhead , And if the logic value of bit 7 is " 1 " in order, then passing the input signal as it is (step S370), and as a result of the determination in step S340, 5, 6, and 7 of the low path overhead If the logical value of the bit is not " 1 " in order, it is judged as a " mismatch " state (step S380).

In the communication by the synchronous transmission method according to the present invention, using the L1, L2, and L3 bit processing apparatus and processing method of the low path overhead, the low path between the various devices connected to each other using the synchronous transmission method Even when a signal having a logic value of "1" of the L1, L2, and L3 bits of the overhead arrives, the low-level path is recognized and the input signal is passed, so that the interface between the old and new devices is smooth. It is effective.

Claims (2)

In communication by the synchronous transmission method, bits 5, 6, and 7 used as signal signs indicating the connection relationship among the low path overheads among the low path overheads are inputted with a logic value of 8 bits of low path overheads. A low path overhead input unit 210 for extracting and outputting the extracted path; By receiving the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210, it is determined whether the logical values of the bits are "000" in order, and "000" and " If it is not 000 "," 000 "detection unit 220 for outputting different logic values; By receiving the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210, it is determined whether the logical values of these bits are "010" in order, and "010" and " If it is not 010 "," 010 "detection unit 230 for outputting different logic values; By receiving the 5th, 6th, and 7th bits of the low path overhead from the low path overhead input unit 210, it is determined whether the logical values of the bits are "001" in order, and "001" and " If not, "001" detection unit 240 for outputting different logic values; A memory device 250 for storing the output value of the “000” detector 220; A memory device 260 for storing the output value of the "010" detector 230; A memory device 270 that stores the output value of the "001" detector 240; And L1 of the low path overhead, characterized in that it comprises a "mismatch" determination unit 280 for outputting a different logical value when the output values of the storage devices (250, 260, 270) are the same or not , L2 and L3 bit processing apparatus 200. In the communication by the synchronous transmission method, receiving a logic value of bits 5, 6, and 7 which are used as signal signs indicating the connection relationship among the low path among the 8 paths of low path overhead (step S310). ); Determining whether logical values of bits 5, 6, and 7 of the low path overhead received from step S310 are "000" in order (S320); If the logical value of the 5th, 6th, and 7th bits of the low path overhead is "000" in order, as a result of the determination in step S320, determining the "unequip" state (step S350); As a result of the determination in step S320, if the logic values of bits 5, 6, and 7 of the low path overhead are not "000" in order, 5, 6, and 7 of the low path overhead Determining whether the logical values of the bits are "010" in order (step S330); Judging that the logical values of bits 5, 6, and 7 of the low path overhead are "010" in order, as a result of the determination in step S330 (step S360); As a result of the determination in step S330, if the logic values of bits 5, 6, and 7 of the low path overhead are not "010" in order, 5, 6, and 7 of the low path overhead Determining whether the logical values of the bits are "001" in order (step S340); As a result of the determination in step S340, if the logic values of bits 5, 6, and 7 of the low path overhead are " 001 " in order, passing the input signal as it is (step S370); And If the logical value of the 5th, 6th, and 7th bits of the low path overhead is not "001" in order as a result of the determination in step S340, the method includes determining a "mismatch" state (step S380). L1, L2 and L3 bit processing method of the low path overhead, characterized in that configured to.

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