KR100262737B1 - Manufacturing method of tma - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film actuated mirror array is to recover the defected part of an active substrate by forming an actuator on the rear surface of the active substrate. CONSTITUTION: A field oxide layer(520) is formed to define an active region by oxidizing a predetermined part of an insulating substrate(510). A MOS transistor is formed on the active region defined by the field oxide layer. The MOS transistor includes a gate oxide layer(530a), a gate electrode(530b), an interlayer dielectric(530c), a source region(530d), and a drain region(530e). A metal layer(540) includes a source line(540a) electrically connected to the source region and a drain pad(540b) electrically connected to the drain region. An active substrate(560) is formed by depositing a passivation layer on the metal layer. After rotating the active substrate by 180 degrees in a clockwise direction, a sacrificial material layer is formed on the rear surface of the active substrate.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method of manufacturing a thin film type optical path control apparatus, and more particularly, to a method of manufacturing a thin film type optical path control apparatus that can be easily recovered when an actuator is formed on the rear surface of a driving substrate and a part of the driving substrate is damaged.

In general, a spatial light modulator, which is an apparatus for projecting optical energy onto a screen, may be variously applied to optical communication, image processing, and information display apparatus. Such devices are classified into a direct view type image display device and a projection type image display device according to a method of projecting a light beam incident from a light source onto a screen. CRT (Cathod Ray Tube) is a direct type image display device, and liquid crystal display (hereinafter referred to as LCD), DMD (Deformable Mirror Device), or AMA (Actuated) is a projection type image display device. Mirror Arrays).

The above-described CRT apparatus is an excellent display apparatus which is guaranteed an average brightness of 100 ft-L (white display) or more, a contrast ratio of 30: 1 or more, a lifetime of 10,000 hours or more. However, since the CRT has a large weight and volume and maintains high mechanical strength, it is difficult to make the screen completely flat, which causes distortion of the peripheral part. In addition, since CRTs excite phosphors with an electron beam to emit light, there is a problem that a high voltage is required to produce an image.

Therefore, LCDs have been developed to solve the above-mentioned problems of CRT. The advantages of such LCDs are explained in comparison with CRTs. LCDs operate at low voltages, consume less power, and provide images without distortion.

However, despite the advantages described above, the LCD has a low light efficiency of 1 to 2% due to the polarization of the light beam, and there is a problem that the response speed of the liquid crystal material therein is slow.

Accordingly, in order to solve the problems of the LCD as described above, a device such as a DMD or an AMA has been developed. Currently, AMA can achieve a light efficiency of 10% or more, while DMD has a light efficiency of about 5%. In addition, the AMA is not only affected by the polarity of the incident luminous flux but also does not affect the polarity of the luminous flux.

Typically, the respective actuators formed inside the AMA cause deformation depending on the electric field generated by the applied image signal and bias voltage. When this actuator causes deformation, each of the mirrors mounted on top of the actuator is inclined in proportion to the magnitude of the electric field.

Thus, these inclined mirrors can reflect light incident from the light source at a predetermined angle. Piezoelectric ceramics such as PZT (Pb (Zr, Ti) O ₃ ), or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as the constituent material of the actuator for driving the respective mirrors. As the constituent material of this actuator, electrodistorted ceramics such as PMN (Pb (Mg, Nb) O ₃ ) can be used.

The AMA is classified into a bulk type and a thin film type. Currently, AMA is the main trend of the thin-film optical path control device.

1 is a cross-sectional view of a conventional thin film type optical path control device.

Referring to FIG. 1, the thin film type optical path control apparatus includes a driving substrate 70 and an actuator 170 formed thereon.

The driving substrate 70 includes an insulating substrate 10, a field oxide layer 20 defining an active region of the insulating substrate 10, an MOS transistor 30 formed in an active region defined by the field oxide layer 20, and a MOS transistor ( The metal layer 40 is electrically connected to the substrate 30, the protective layer 50 formed on the metal layer 40, and the etch stop layer 60 formed on the protective layer 50.

The MOS transistor 30 includes a gate oxide layer 30a, a gate electrode 30b, an interlayer insulating layer 30c, a source region 30d, and a drain region 30e.

In addition, the metal layer 40 includes a source line 40a electrically connected to the source region 30d and a drain pad 40b electrically connected to the drain region 40b.

Actuator 170 is a membrane formed so that one side is in contact with the portion of the etch stop layer 60 in which the drain pad 40b is formed and the other side is parallel to the etch stop layer 60 via an air gap (90). (membrane: 100), the lower electrode 110 formed on the membrane 100, the strained layer 120 formed on the lower electrode 110, the upper electrode 130 formed on the strained layer 120, A strip pad 140 formed on a predetermined portion of the upper electrode 130 and a drain pad through the lower electrode 110, the membrane 100, the etch stop layer 60, and the protective layer 50 from the other side of the deformation layer 120. A distribution hole 150 vertically formed up to 40b and a power distribution 160 formed in the distribution hole 150 to electrically connect the lower electrode 110 and the drain pad 40b to each other.

In addition, a predetermined portion is removed from the upper electrode 130 to form a stripe 140. The stripe 140 prevents diffuse reflection of light reflected from the upper electrode 130 when the actuator 170 is deformed.

Hereinafter, the manufacturing method of the above-described thin film type optical path control apparatus will be described with reference to the drawings.

2A to 2D are manufacturing process diagrams of the apparatus shown in FIG. 1. 2A to 2D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 2A, a predetermined portion of the insulating substrate 10 is oxidized to form a field oxide layer 20. The field oxide layer 20 defines an active region of the insulating substrate 10, and the active region is formed with a MOS transistor 30 to be described later.

Next, an MOS transistor 30 including a gate oxide layer 30a, a gate electrode 30b, an interlayer insulating layer 30c, a source region 30d and a drain region 30e in an active region defined by the field oxide layer 20. ).

Next, the metal layer 40 is formed of an electrically conductive material on the source region 30d and the drain region 30e. The metal layer 40 includes a source line 40a and a drain pad 40b. At this time, the source line 40a and the drain pad 40b are formed not to be electrically connected.

Subsequently, the protective layer 50 is formed on the metal layer 40. The protective layer 50 is formed to have a thickness of about 1.0 to 2.0 μm using a chemical vapor deposition (CVD) method. The protective layer 50 protects the MOS transistor 30 during subsequent processing.

The etch stop layer 60 is formed of silicon nitride (Si ₃ N ₄ ) on the protective layer 50. The etch stop layer 60 is formed to a thickness of about 1000 to 2000 kPa by Low Pressure Chemical Vapor Deposition (LPCVD). The etch stop layer 60 prevents the protective layer 50 and its lower portion from being damaged during the subsequent etching process.

Accordingly, the driving substrate 70 including the insulating substrate 10, the field oxide layer 20, the MOS transistor 30, the metal layer 40, the protective layer 50, and the etch stop layer 60 is formed.

Referring to FIG. 2B, the sacrificial material layer 80 ′ is formed on the etch stop layer 60. The sacrificial material layer 80 ′ is formed of a silicate glass having a high concentration of phosphorus (P) to a thickness of about 1.0 μm to 2.0 μm by an Atmospheric Pressure CVD (APCVD) method. In this case, since the sacrificial material layer 80 ′ covers the upper portion of the driving substrate 70 in which the MOS transistor 30 is embedded, the surface flatness is very poor.

Therefore, the surface of the sacrificial material layer 80 ′ is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial material layer 80 ′ in which the drain pad 40b is formed is etched to expose a portion of the etch stop layer 60 to form the sacrificial layer 80.

The membrane material layer 100 ′ is stacked on top of the exposed etch stop layer 60 and on top of the sacrificial layer 80. The membrane material layer 100 ′ is formed to have a thickness of about 0.1 to 1.0 μm of silicon nitride by low pressure chemical vapor deposition.

The lower electrode material layer 110 ′ is formed of a material having excellent electrical conductivity such as platinum / tantalum (Pt / Ta) on the membrane material layer 100 ′. The lower electrode material layer 110 ′ is formed to a thickness of about 500 to 2000 micrometers by a sputtering method.

Next, the strained material layer 120 ′ is formed of PZT or PLZT, which is a piezoelectric material, on the lower electrode material layer 110 ′. The deformable material layer 120 ′ is formed to have a thickness of 0.1 μm to 1.0 μm by a sol-gel method. Subsequently, the deformable material layer 120 ′ is phase-shifted by a rapid thermal annealing (RTA) method.

The upper electrode material layer 130 ′ is formed on the strained material layer 120 ′. The upper electrode material layer 130 ′ is formed to have a thickness of about 500 to about 2000 μs by sputtering a metal having excellent electrical conductivity and reflectivity such as aluminum.

Referring to FIG. 2C, the upper electrode material layer 130 ′ is patterned for each pixel to form the upper electrode 130. At the same time, a stripe 140 is formed in the center of the upper electrode 130. The stripe 140 uniformly operates the upper electrode 130 to prevent the incident light beam from being diffusely reflected.

Subsequently, the strained material layer 120 ′, the lower electrode material layer 110 ′, and the membrane material layer 100 ′ are sequentially patterned for each pixel to form the strained layer 120, the lower electrode 110, and the membrane 100. To form. Next, the strained layer 120, the lower electrode 110, the membrane 100, the etch stop layer 60, and the protective layer 50 are sequentially formed from the other upper portion of the strained layer 120 to the upper portion of the drain pad 40b. By etching, the distribution hole 150 is vertically formed from the strained layer 120 to the drain pad 40b.

Subsequently, the inside of the power distribution hole 150 is filled with a metal such as tungsten, platinum, or titanium to form the power distribution 160. The distributor 160 is formed by a sputtering method and electrically connects the drain pad 40b and the lower electrode 110. Therefore, the distributor 160 is vertically formed from the lower electrode 110 to the top of the drain pad 40b in the distribution hole 150.

Referring to FIG. 2D, the sacrificial layer 80 is removed with hydrofluoric acid (HF) gas, followed by washing and rotation drying to form an air gap 90 to complete the thin film type optical path control apparatus.

As described above, the conventional thin film type optical path control device has a problem in that the actuator cannot be recovered when the actuator substrate under the actuator is damaged because the actuator is formed on the driver substrate.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to form an actuator on the back surface of the driving substrate, so that a part of the driving substrate can be easily recovered even if a part of the driving substrate is damaged. The purpose is to provide a manufacturing method.

In order to achieve the above object, the present invention includes the steps of oxidizing a predetermined portion of the insulating substrate to form a field oxide layer defining an active region; Forming a MOS transistor including a gate oxide layer, a gate electrode, an interlayer insulating layer, a source region and a drain region in an active region defined by the field oxide layer; Forming a metal layer comprising a source line electrically connected to the source region and a drain pad electrically connected to the drain region; Stacking a protective layer on top of the metal layer to form a driving substrate; Rotating the drive substrate clockwise by 180 ° and forming a sacrificial material layer on the back surface of the drive substrate; Forming a sacrificial layer exposing an insulating substrate by removing a portion of the sacrificial material layer in which a drain pad is formed; Sequentially forming a membrane material layer, a lower electrode material layer, a strain material layer and an upper electrode material layer on the insulating substrate and the sacrificial layer; Sequentially patterning the upper electrode material layer, the modifying material layer, the lower electrode material layer, and the membrane material layer for each pixel to sequentially form the upper electrode, the modifying layer, and the membrane; Forming a distribution hole by sequentially etching the strain layer, the lower electrode, the membrane, the insulating substrate, and the field oxide layer from an upper portion of the strain layer to an upper portion of the drain pad; And forming a distributor so that the lower electrode and the drain pad are electrically connected to the inside of the distribution hole.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

1 is a cross-sectional view of a conventional thin film type optical path control device,

2a to 2d is a manufacturing process diagram of the device shown in FIG.

3 is a cross-sectional view of a thin film type optical path control apparatus according to the present invention,

4A-4D are manufacturing process diagrams of the apparatus shown in FIG. 3.

<Explanation of symbols for main parts of drawing>

510: insulating substrate 520: field oxide layer

530: MOS transistor 530a: gate oxide layer

530b: gate electrode 530c: interlayer insulating layer

530d: source region 530e: drain region

540: metal layer 540a: source line

540b: drain pad 550: protective layer

560: driving substrate 570: sacrificial layer

580: air gap 590: membrane

600: lower electrode 610: strained layer

620: upper electrode 630: stripe

640: power distribution hall 650: power distribution

660: Actuator

Hereinafter, with reference to the accompanying drawings will be described in detail a thin film type optical path control apparatus according to the present invention.

3 is a cross-sectional view of a thin film type optical path control apparatus according to the present invention.

Referring to FIG. 3, the thin film type optical path control device includes a driving substrate 560 and an actuator 660 formed thereon.

The driving substrate 560 includes an insulating substrate 510, a field oxide layer 520 defining an active region of the insulating substrate 510, a MOS transistor 530 formed in an active region defined by the field oxide layer 520, and a MOS transistor ( A metal layer 540 electrically connected to the 530 and a protective layer 550 formed on the metal layer 540.

The MOS transistor 530 includes a gate oxide layer 530a, a gate electrode 530b, an interlayer insulating layer 530c, a source region 530d, and a drain region 530e.

In addition, the metal layer 540 includes a source line 540a electrically connected to the source region 530d and a drain pad 540b electrically connected to the drain region 530e.

The actuator 660 is formed such that one side of the insulating substrate 510 is in contact with a portion where the drain pad 540b is formed, and the other side thereof is parallel to the insulating substrate 510 via an air gap 580. (membrane: 590), the lower electrode 600 formed on the membrane 590, the strain layer 610 formed on the lower electrode 600, the upper electrode 620 formed on the strain layer 610, The drain pad 630 may be formed on the stripe 630 formed on a predetermined portion of the upper electrode 620 through the lower electrode 600, the membrane 590, the insulating substrate 510, and the field oxide layer 520 from the other side of the deformation layer 610. A distribution hole 640 vertically formed to 540b and a distribution 650 formed in the distribution hole 640 so that the lower electrode 600 and the drain pad 540b are electrically connected to each other.

In addition, a predetermined portion is removed from the upper electrode 620 to form a stripe 630. The stripe 630 prevents diffuse reflection of light reflected from the upper electrode 620 when the actuator 660 is deformed.

Hereinafter, the manufacturing method of the above-described thin film type optical path control apparatus will be described with reference to the drawings.

4A to 4D are manufacturing process diagrams of the apparatus shown in FIG. 3. 4A to 4D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 4A, a predetermined portion of the insulating substrate 510 is oxidized to form a field oxide layer 520. The field oxide layer 520 defines an active region of the insulating substrate 510, and the MOS transistor 530, which will be described later, is formed in the active region.

Next, an MOS transistor 530 including a gate oxide layer 530a, a gate electrode 530b, an interlayer insulating layer 530c, a source region 530d, and a drain region 530e in an active region defined by the field oxide layer 520. ).

Next, a metal layer 540 is formed of an electrically conductive material on the source region 530d and the drain region 530e. The metal layer 540 includes a source line 540a and a drain pad 540b. At this time, the source line 540a and the drain pad 540b are formed so as not to be electrically connected.

Subsequently, the protective layer 550 is formed on the metal layer 540. The protective layer 550 is formed to have a thickness of about 1.0 to 2.0 μm using a chemical vapor deposition (CVD) method. Protective layer 550 protects MOS transistor 530 during subsequent processing.

Accordingly, the driving substrate 560 including the insulating substrate 510, the field oxide layer 520, the MOS transistor 530, the metal layer 540, and the protective layer 550 is completed.

Next, after the driving substrate 560 is rotated 180 ° clockwise, a sacrificial material layer 570 ′ is formed on the rear surface of the driving substrate 560. The sacrificial material layer 570 ′ is formed of a silicate glass having a high concentration of phosphorus (P) to a thickness of about 1.0 μm to 2.0 μm by an atmospheric pressure chemical vapor deposition (APCVD) method. Since the conventional sacrificial material layer 570 ′ covers the upper portion of the driving substrate 560 in which the MOS transistor 530 is embedded, the surface flatness is very poor, and thus spin on glass (SOG) is used. Planarization by a method or a method using chemical mechanical polishing (CMP). However, in the present invention, since the sacrificial material layer 570 ′ is formed on the rear surface of the driving substrate 560, it is not necessary to perform planarization.

Subsequently, a portion of the sacrificial material layer 570 ′ in which the drain pad 540b is formed is etched to expose a portion of the back surface of the driving substrate 560 to form the sacrificial layer 570.

Referring to FIG. 4B, a membrane material layer 590 ′ is stacked on top of the exposed back side of the driving substrate 560 and on top of the sacrificial layer 570. The membrane material layer 590 ′ is formed to have a thickness of about 0.1 μm to about 1.0 μm using silicon nitride by low pressure chemical vapor deposition.

The lower electrode material layer 600 'is formed of a material having excellent electrical conductivity such as platinum / tantalum (Pt / Ta) on the membrane material layer 590'. The lower electrode material layer 600 'is formed to a thickness of about 500 to 2000 micrometers by a sputtering method.

Next, the strain material layer 610 ′ is formed of PZT or PLZT, which is a piezoelectric material, on the lower electrode material layer 600 ′. The deformable material layer 610 ′ is formed to have a thickness of 0.1 μm to 1.0 μm by a sol-gel method. Subsequently, the deformable material layer 610 ′ is phase-shifted by a rapid thermal annealing (RTA) method.

The upper electrode material layer 620 'is formed on the strained material layer 610'. The upper electrode material layer 620 'is formed to have a thickness of about 500 to about 2000 kPa by sputtering a metal having excellent electrical conductivity and reflectivity such as aluminum.

Referring to FIG. 4C, the upper electrode material layer 620 ′ is patterned for each pixel to form the upper electrode 620. At the same time, a stripe 630 is formed in the center of the upper electrode 620. The stripe 630 uniformly operates the upper electrode 620 to prevent diffuse reflection of the incident light beam.

Subsequently, the strained material layer 610 ′, the lower electrode material layer 600 ′, and the membrane material layer 590 ′ are sequentially patterned for each pixel to form the strained layer 610, the lower electrode 600, and the membrane 590. To form. Next, the strained layer 610, the lower electrode 600, the membrane 590, the insulating substrate 510, and the field oxide layer 520 are sequentially formed from the other side of the strained layer 610 to the top of the drain pad 540b. Etching forms a distribution hole 640 vertically from the strained layer 610 to the drain pad 540b.

Subsequently, the inside of the distribution hole 640 is filled with a metal such as tungsten, platinum, or titanium to form a power distribution 650. The distributor 650 is formed by a sputtering method and electrically connects the drain pad 540b and the lower electrode 600. Therefore, the power distributor 650 is vertically formed from the lower electrode 600 to the top of the drain pad 540b in the distribution hole 640.

Referring to FIG. 4D, the sacrificial layer 570 is removed with hydrofluoric acid (HF) gas, followed by washing and rotation drying to form an air gap 580 to complete the thin film type optical path control apparatus.

As described above, in the thin film type optical path control device according to the present invention, an actuator is formed on the back surface of the driving substrate on which the drain pad is formed, so that the inside of the driving substrate can be easily recovered, and the photocurrent can be reduced. There is no need to form a layer, and there is an effect that a planarization process for planarizing the mirror is not necessary.

As described above, although the present invention has been described with reference to the drawings, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can.

Claims (1)

Oxidizing a predetermined portion of the insulating substrate 510 to form a field oxide layer 520 defining an active region; MOS transistor 530 including a gate oxide layer 530a, a gate electrode 530b, an interlayer insulating layer 530c, a source region 530d, and a drain region 530e in the active region defined by the field oxide layer 520. Forming a); Forming a metal layer (540) including a source line (540a) electrically connected to the source region (530d) and a drain pad (540b) electrically connected to the drain region (530e); Stacking a protective layer (550) on the metal layer (540) to form a driving substrate (560); Forming a sacrificial material layer 570 ′ on a rear surface of the driving substrate 560 after rotating the driving substrate 560 clockwise; Removing a portion of the sacrificial material layer 570 'formed with the drain pad 540b to form a sacrificial layer 570 exposing the insulating substrate 510; The membrane material layer 590 ', the lower electrode material layer 600', the strain material layer 610 'and the upper electrode material layer 620' are sequentially formed on the insulating substrate 510 and the sacrificial layer 570. Forming to; The upper electrode material layer 620 ', the strain material layer 610', the lower electrode material layer 600 'and the membrane material layer 590' are sequentially patterned for each pixel to form the upper electrode 620, Sequentially forming the strained layer 610 and the membrane 590; The strained layer 610, the lower electrode 600, the membrane 590, the insulating substrate 510, and the field vertically from the top of the other side of the strained layer 610 to the top of the drain pad 540b. Sequentially etching the oxide layer 520 to form a distribution hole 640; And forming a distributor (650) in the distribution hole (640) such that the lower electrode (600) and the drain pad (540b) are electrically connected to each other.

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