KR100258108B1 - Fabricating method for actuated mirror arrays - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film actuated mirror array is to prevent an upper layer and a transformed layer from being damaged when removing a sacrificial layer. CONSTITUTION: A number of metal oxide transistor transistors are built in a driving substrate(510) in a form of matrix. A passivation layer(530) is formed on the driving substrate and a drain pad(520) formed on the driving substrate. An actuator includes a membrane(560) with one side contacted with a drain pad(520) of the passivation layer and an air gap(550) interposed between the other side and the passivation layer, a lower electrode(570) formed on the membrane, a transformed layer(580) formed on the lower electrode, an upper electrode(590) formed on the transformed layer, a scribe(600) formed by patterning a desired portion of the upper electrode, a wiring hole(610) vertically formed from one side of the transformed layer to the drain pad through the lower electrode, the membrane, the passivation layer, and a wiring member(620) for electrically connecting the lower electrode with the drain pad.

Description

Manufacturing method of thin film type optical path control device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film type optical path control device, and more particularly, to a method for manufacturing a thin film type optical path control device that does not damage other layers that are formed when a sacrificial layer is removed and does not damage a transistor embedded in a driving substrate.

In general, a spatial light modulator, which is an apparatus for projecting optical energy onto a screen, may be variously applied to optical communication, image processing, and information display apparatus. Such devices are classified into a direct view type image display device and a projection type image display device according to a method of projecting a light beam incident from a light source onto a screen. CRT (Cathod Ray Tube) is a direct type image display device, and liquid crystal display (hereinafter referred to as LCD), DMD (Deformable Mirror Device), or AMA (Actuated) is a projection type image display device. Mirror Arrays).

The above-described CRT apparatus is an excellent display apparatus which is guaranteed an average brightness of 100 ft-L (white display) or more, a contrast ratio of 30: 1 or more, a lifetime of 10,000 hours or more. However, since the CRT has a large weight and volume and maintains high mechanical strength, it is difficult to make the screen completely flat, which causes distortion of the peripheral part. In addition, since CRTs excite phosphors with an electron beam to emit light, there is a problem that a high voltage is required to produce an image.

Therefore, LCDs have been developed to solve the above-mentioned problems of CRT. The advantages of such LCDs are explained in comparison with CRTs. LCDs operate at low voltages, consume less power, and provide images without distortion.

However, despite the advantages described above, the LCD has a low light efficiency of 1 to 2% due to the polarization of the light beam, and there is a problem that the response speed of the liquid crystal material therein is slow.

Accordingly, in order to solve the problems of the LCD as described above, a device such as a DMD or an AMA has been developed. Currently, AMA can achieve a light efficiency of 10% or more, while DMD has a light efficiency of about 5%. In addition, the AMA is not only affected by the polarity of the incident luminous flux but also does not affect the polarity of the luminous flux.

Typically, the respective actuators formed inside the AMA cause deformation depending on the electric field generated by the applied image signal and bias voltage. When this actuator causes deformation, each of the mirrors mounted on top of the actuator is inclined in proportion to the magnitude of the electric field.

Thus, these inclined mirrors can reflect light incident from the light source at a predetermined angle. Piezoelectric ceramics such as PZT (Pb (Zr, Ti) O ₃ ), or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as the constituent material of the actuator for driving the respective mirrors. As the constituent material of this actuator, electrodistorted ceramics such as PMN (Pb (Mg, Nb) O ₃ ) can be used.

The AMA is classified into a bulk type and a thin film type. Currently, AMA is the main trend of the thin-film optical path control device.

1 is a plan view of a conventional thin film type optical path control device.

Referring to FIG. 1, one side of the membrane 70 has a rectangular concave portion at a central portion thereof, and the concave portion is formed in a stepped shape toward both edges. The other side of the membrane 70 has a rectangular protrusion that narrows stepwise toward the central portion corresponding to the concave portion. Therefore, the concave portion of the membrane 70 is fitted with the rectangular protrusion of the adjacent membrane, and the rectangular protrusion is fitted with the concave portion of the adjacent membrane.

2 is a cross-sectional view taken along line AA ′ of the apparatus shown in FIG. 1.

Referring to FIG. 2, the thin film type optical path control apparatus includes a driving substrate 10 having a drain pad 20 formed on one side thereof, and an actuator 140 formed thereon.

M × N (M, N is an integer) transistors are embedded in the drive substrate 10 in a matrix form. In addition, the driving substrate 10 includes a protective layer 30 and an etch stop layer 40 formed on the drain pad 20.

The actuator 140 is formed such that one side of the etch stop layer 40 is in contact with a portion where the drain pad 20 is formed, and the other side is parallel to the etch stop layer 40 through an air gap 60. (membrane: 70), the lower electrode 80 formed on the membrane 70, the strained layer 90 formed on the lower electrode 80, the upper electrode 100 formed on the strained layer 90, From the other side of the stripe 110 and the deformable layer 90 formed on a predetermined portion of the upper electrode 100, the drain pads may be formed through the lower electrode 80, the membrane 70, the etch stop layer 40, and the protective layer 30. A distribution hole 120 vertically formed up to 20, and a distribution unit 130 formed to electrically connect the lower electrode 80 and the drain pad 20 to each other in the distribution hole 120.

Hereinafter, the manufacturing method of the above-described thin film type optical path control apparatus will be described with reference to the drawings.

3A to 3D are manufacturing process diagrams of the apparatus shown in FIG. 2. 3A to 3D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 3A, MxN (M, N is an integer) insulator glass (Phospho) is formed on an upper portion of a driving substrate 10 having a matrix embedded therein and a drain pad 20 formed on one side thereof. A protective layer 30 composed of Silicate Glass (PSG) is formed.

The protective layer 30 is formed to have a thickness of about 1.0 to 2.0 μm using a chemical vapor deposition (CVD) method. The protective layer 30 protects the drive substrate 10 during subsequent processing.

The etch stop layer 40 is formed of silicon nitride (Si ₃ N ₄ ) on the upper portion of the protective layer 30. The etch stop layer 40 is formed to a thickness of about 1000 to 2000 kPa by Low Pressure Chemical Vapor Deposition (LPCVD). The etch stop layer 40 prevents the protective layer 30 and its lower portion from being damaged during the subsequent etching process.

The sacrificial layer 50 is formed on the etch stop layer 40. The sacrificial layer 50 is formed of a silicate glass having a high concentration of phosphorus (P) to a thickness of about 1.0 to 2.0 μm by an Atmospheric Pressure Vapor Deposition (APCVD) method. In this case, since the sacrificial layer 50 covers the upper portion of the driving substrate 10 in which the transistor is embedded, the flatness of the surface thereof is very poor. Therefore, the surface of the sacrificial layer 50 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 50 in which the drain pad 20 is formed is etched to expose a portion of the etch stop layer 40.

Referring to FIG. 3B, the membrane material layer 70 ′ is stacked on top of the exposed etch stop layer 40 and on top of the sacrificial layer 50. The membrane material layer 70 ′ is formed to have a thickness of about 0.1 to 1.0 μm of silicon nitride by low pressure chemical vapor deposition. At this time, the membrane material layer 70 'is formed at approximately 800 ° C.

The lower electrode material layer 80 'is formed of a material having excellent electrical conductivity such as platinum / tantalum (Pt / Ta) on the membrane material layer 70'. The lower electrode material layer 80 'is formed to a thickness of about 500 to 2000 micrometers by a sputtering method.

Referring to FIG. 3C, the strain material layer 90 ′ is formed of PZT or PLZT, which is a piezoelectric material, on the lower electrode material layer 80 ′. The deformable material layer 90 ′ is formed to have a thickness of 0.1 μm to 1.0 μm by a sol-gel method. Subsequently, the deformable material layer 90 is phase-shifted by a rapid thermal annealing (RTA) method.

The upper electrode material layer 100 ′ is formed on the strained layer 90. The upper electrode material layer 100 ′ is formed to have a thickness of about 500 to about 2000 microseconds by sputtering a metal having excellent electrical conductivity and reflectivity such as aluminum.

Subsequently, the upper electrode material layer 100 ′ is patterned for each pixel to form the upper electrode 100. At the same time, a stripe 110 is formed in the center of the upper electrode 100. The stripe 110 uniformly operates the upper electrode 100 to prevent the incident light beam from being diffusely reflected.

Referring to FIG. 3D, the strained material layer 90 ′, the lower electrode material layer 80 ′, and the membrane material layer 70 ′ are sequentially patterned for each pixel to form the strained layer 90, the lower electrode 80, and the membrane. Form 70. Next, the strained layer 90, the lower electrode 80, the membrane 70, the etch stop layer 40, and the protective layer 30 are sequentially formed from the upper portion of the strained layer 90 to the upper portion of the drain pad 20. Etching forms a distribution hole 120 vertically from the strained layer 90 to the drain pad 20.

Subsequently, the inside of the distribution hole 120 is filled with a metal such as tungsten, platinum or titanium to form the power distribution 130. The distributor 130 is formed by a sputtering method and electrically connects the drain pad 20 and the lower electrode 80. Therefore, the distributor 130 is vertically formed from the lower electrode 80 to the upper portion of the drain pad 20 in the distribution hole 120. Finally, the sacrificial layer 50 is removed with hydrofluoric acid (HF) gas to form an air gap 60.

As described above, the conventional thin film type optical path control apparatus removes the sacrificial layer with hydrofluoric acid gas. Since hydrofluoric acid gas is acidic, it damages the upper electrode and the strained layer, and due to the high temperature process involved in forming the etch stop layer and the membrane. There was a problem that the transistor embedded in the driving substrate is damaged.

The present invention has been made to solve the conventional problems as described above, the object of the present invention is to form a sacrificial layer of amorphous silicon or polycrystalline silicon and then removed with XeF ₂ gas or BrF ₃ gas, accompanied by a high temperature process The present invention provides a method of manufacturing a thin film type optical path control apparatus capable of forming a membrane by a low temperature plasma chemical vapor deposition method without forming an etching prevention layer.

In order to achieve the above object, the present invention provides a driving substrate including an M × N (M, N is an integer) transistor (not shown) in a matrix form and including a drain pad on one side. Providing; Forming a protective layer on the driving substrate; Forming a sacrificial layer on top of the protective layer, one of amorphous silicon or polycrystalline silicon; Etching a portion of the sacrificial layer in which the drain pad is formed to expose a portion of the protective layer; Forming a membrane material layer on top of the exposed protective layer and on the sacrificial layer by plasma chemical vapor deposition; Forming a lower electrode material layer on top of the membrane material layer; Forming a strained material layer on top of the lower electrode material layer; Forming an upper electrode material layer on top of the strained material layer; Patterning the upper electrode material layer pixel by pixel to form an upper electrode; Patterning the deformable material layer, the lower electrode material layer and the membrane material layer pixel by pixel to form a deformable layer, the lower electrode and the membrane; Removing the sacrificial layer to form an air gap.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

1 is a plan view of a conventional thin film type optical path control device,

FIG. 2 is a cross-sectional view taken along line AA ′ of the apparatus of FIG. 1; FIG.

3a to 3d is a manufacturing process diagram of the device shown in FIG.

4 is a cross-sectional view of a thin film type optical path control device according to the present invention,

5A to 5D are manufacturing process diagrams of the apparatus shown in FIG.

<Description of the symbols for the main parts of the drawings>

510: driving substrate 520: drain pad 530: protective layer

540: sacrificial layer 550: air gap 560: membrane

570: lower electrode 580: strained layer 590: upper electrode

600: stripe 610: power distribution hole 620: power distribution

630: Actuator

Hereinafter, with reference to the accompanying drawings will be described in detail a thin film type optical path control apparatus according to the present invention.

4 is a cross-sectional view of a thin film type optical path control apparatus according to the present invention.

Referring to FIG. 4, the thin film type optical path control apparatus includes a driving substrate 510 having a drain pad 520 formed on one side thereof, and an actuator 640 formed thereon.

Inside the driving substrate 510, M × N transistors (M and N are integers) are built in a matrix. In addition, the driving substrate 510 includes a protective layer 530 formed on the top and the drain pad 520.

The actuator 630 may have a membrane 560 formed such that one side of the protective layer 530 is in contact with a portion where the drain pad 520 is formed and the other side thereof is parallel to the protective layer 530 via the air gap 550. , A lower electrode 570 formed on the membrane 560, a strained layer 580 formed on the lower electrode 570, an upper electrode 590 formed on the strained layer 580, and an upper electrode 590. A distribution hole vertically formed from the other side of the stripe 600 and the strained layer 580 formed by patterning a predetermined portion of the stripe to the drain pad 520 through the lower electrode 570, the membrane 560, and the protective layer 530. 610 and a distribution 620 formed in the distribution hole 610 so that the lower electrode 570 and the drain pad 520 are electrically connected to each other.

Hereinafter, the manufacturing method of the above-described thin film type optical path control apparatus will be described with reference to the drawings.

5A to 5D are manufacturing process diagrams of the apparatus shown in FIG. 4. 5A to 5D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 5A, M × N (M and N are integers) transistors (not shown) are embedded in a matrix form and a drain pad 520 is formed on one side of the driving substrate 510. The protective layer 530 is formed of silicate glass.

The protective layer 530 is formed to have a thickness of about 1.0 to 2.0 μm using a chemical vapor deposition (CVD) method. The protective layer 530 protects the driving substrate 510 during the subsequent process.

The sacrificial layer 540 is formed on the passivation layer 530. The sacrificial layer 540 is formed of amorphous silicon or polycrystalline silicon. The sacrificial layer 540 is formed to have a thickness of about 1.0 to 2.0 μm by chemical vapor deposition. Since the sacrificial layer 540 covers the upper portion of the driving substrate 510 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 540 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 540 in which the drain pad 520 is formed is etched to expose a portion of the protective layer 530.

Referring to FIG. 5B, a membrane material layer 560 ′ is formed over the exposed protective layer 530 and over the sacrificial layer 540. The membrane material layer 560 ′ is formed to have a thickness of about 0.1 μm to about 1.0 μm by silicon chemical vapor deposition. At this time, the membrane material layer 560 'is formed at approximately 400 ° C.

The lower electrode material layer 570 'is formed of an electrically conductive material such as platinum / tantalum (Pt / Ta) on the membrane material layer 560'. The lower electrode material layer 570 ′ is formed to a thickness of about 500 to about 2000 micrometers by a sputtering method.

Referring to FIG. 5C, the strain material layer 580 ′ is formed of PZT or PLZT, which is a piezoelectric material, on the lower electrode material layer 570 ′. The deformable material layer 580 ′ is formed to have a thickness of 0.1 μm to 1.0 μm by a sol-gel method. Subsequently, the deformable material layer 580 ′ is phase-shifted by a rapid thermal annealing (RTA) method.

The upper electrode material layer 590 'is formed on the deformable material layer 580'. The upper electrode material layer 590 'is formed to have a thickness of about 500 to about 2000 kPa by a sputtering method of a material having excellent electrical conductivity and reflective properties such as aluminum.

Next, the upper electrode material layer 590 ′ is patterned pixel by pixel to form the upper electrode 590. In this case, a portion of the strained material layer 580 ′ is exposed to the outside. Subsequently, the center portion of the upper electrode 590 is patterned to form a stripe 600. The stripe 600 uniformly operates the upper electrode 590 to prevent the incident light beam from being diffusely reflected.

Referring to FIG. 5D, after the upper electrode 590 is patterned for each pixel, the strained material layer 580 ′, the lower electrode material layer 570 ′, and the membrane material layer 560 ′ are patterned for each pixel to form a strained layer ( 580, the lower electrode 570 and the membrane 560 are formed. At this time, a portion of the sacrificial layer 540 is exposed. Subsequently, the strained layer 580, the lower electrode 570, the membrane 560, and the protective layer 530 are sequentially etched from the top of the other side of the strained layer 580 to the top of the drain pad 520, thereby deforming the strained layer ( The distribution hole 610 is vertically formed from the 580 to the drain pad 520.

Subsequently, the distribution 620 is formed by filling a metal such as tungsten, platinum, or titanium in the distribution hole 610. The distributor 620 is formed by a sputtering method, and electrically connects the drain pad 520 and the lower electrode 570.

Finally, the sacrificial layer 540 formed of amorphous silicon or polycrystalline silicon is removed with XeF ₂ gas or BrF ₃ gas to form an air gap 550. In the conventional thin film type optical path control apparatus, the sacrificial layer was formed of a silicate glass having a high concentration of phosphorus (P) and then removed by hydrofluoric acid (HF) gas. At this time, the hydrofluoric acid gas has a strong acidity to damage the upper electrode and the strained layer. In addition, in order to prevent the lower portion of the driving substrate from being damaged by the hydrofluoric acid gas, a separate etching prevention layer is formed. However, since the etch stop layer is accompanied by a high temperature process, the transistor embedded in the driving substrate is damaged by the high temperature. However, since the thin film type optical path control device of the present invention is formed of amorphous silicon or polycrystalline silicon and then removed by XeF ₂ gas or BrF ₃ gas, the upper electrode 590 and the strained layer 580 are not damaged. Since there is no need to form a separate etch stop layer, the manufacturing process is simplified.

Further, in the conventional thin film type optical path control device, the membrane is formed of nitride by low pressure chemical vapor deposition at 800 ° C. At this time, the transistor embedded in the driving substrate had a problem of being damaged by a high temperature of 800 ℃. However, in the present invention, since the membrane is formed by the plasma chemical vapor deposition method at 400 ° C, the transistor embedded in the driving substrate is not damaged.

As described above, the thin film type optical path control apparatus according to the present invention does not damage the upper electrode and the strained layer when removing the sacrificial layer, does not form a separate etch stop layer, and the membrane is formed by a low temperature plasma chemical vapor deposition method. There is an effect that the transistor embedded in the substrate is not damaged by high temperature.

As described above, although the present invention has been described with reference to the drawings, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can.

Claims (3)

Providing a driving substrate 510 having M × N (M, N is an integer) transistors (not shown) embedded in a matrix and including a drain pad 520 on one side thereof; Forming a protective layer (530) on the drive substrate (510); Forming a sacrificial layer (540) on top of the protective layer (530), one of amorphous silicon or polycrystalline silicon; Etching a portion of the sacrificial layer 540 in which the drain pad 520 is formed to expose a portion of the protective layer 530; Forming a membrane material layer (560 ') on the exposed protective layer (530) and on the sacrificial layer (550) by plasma chemical vapor deposition; Forming a lower electrode material layer (570 ') on top of the membrane material layer (560'); Forming a strained material layer (580 ') on top of the lower electrode material layer (570'); Forming an upper electrode material layer (590 ') on top of the strain material layer (580'); Patterning the upper electrode material layer 590 'pixel by pixel to form an upper electrode 590; The strained material layer 580 ′, the lower electrode material layer 570 ′, and the membrane material layer 560 ′ are patterned for each pixel to form the strained layer 580, the lower electrode 570, and the membrane 560. Making a step; And removing the sacrificial layer (540) to form an air gap (550). The method of claim 1, wherein the sacrificial layer (540) is removed with XeF ₂ gas. The method of claim 1, wherein the sacrificial layer (540) is removed with BrF ₃ gas.

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