KR100261770B1 - Tma and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin-film micromirror array-actuated(TMA) and manufacturing method thereof reduce the number of point-defects or line defects of an AMA caused during the manufacturing processes. CONSTITUTION: The first active matrix including the first MOS transistors is laminated on the second active matrix with the second MOS transistors. The first active matrix has parallel connection with the second active matrix. The first source, the first drain and the first gate of the first MOS transistor are connected to the second source, the second drain and the second gate of the second MOS transistor through the respective source pads, the respective drain pads and the respective gate pads. An actuator is formed in the upper of the second active matrix. A bottom electrode of the actuator is electrically connected to the second drain pad. The actuator is electrically connected to the first drain pad because the second drain pad of the second active matrix is electrically connected to the first drain pad of the first active matrix. Therefore, the first MOS transistor or the second MOS transistor drives the actuator even when the one or the other doesn't operate.

Description

Thin film type optical path control device and its manufacturing method

The present invention relates to a thin-film optical path control apparatus using an Actuated Mirror Array (AMA) and a manufacturing method thereof, and more particularly, to a point-defect or line-defect of an AMA device that may occur during the manufacturing process of the apparatus. The present invention relates to a thin-film optical path control apparatus capable of significantly reducing the number of line-defects and a method of manufacturing the same.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, such devices are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display devices include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. PZT (Pb (Zr, Ti) O <SB> 3 </ SB>) or PLZT ((Pb, La) (Zr, Ti) O <SB> 3 </ SB> as an actuator for driving the respective mirrors Piezoelectric materials such as) are used. The actuator can also be configured as a warping material such as PMN (Pb (Mg, Nb) O <SB> 3 </ SB>).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk type optical path adjusting device requires a very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Patent Application No. 96-42197 (Name of the invention: a method of manufacturing a thin film type optical path control device that can control the stress of the support layer) filed by the applicant of the Korean Patent Office on September 24, 1996 It is.

FIG. 1 shows a cross-sectional view of the thin film type optical path adjusting device described in the above prior application, and FIG. 2 shows an equivalent circuit diagram of the device shown in FIG.

1 and 2, the thin film type optical path adjusting device includes an active matrix 1 and an actuator 60. The active matrix 1 in which M x N (M, N is an integer) MOS transistors (not shown) and a drain pad 5a is formed on one surface thereof includes the active matrix 1 and the drain pad. A protective layer 10 stacked on the top of 5a and an etch stop layer 15 stacked on the top of the protective layer 10 are included. Here, reference numerals 2, 3 and 4 denote gates, drains and sources of the P-MOS transistors, respectively, and reference numeral 5b denotes source pads.

The actuator 60 has one side in contact with a portion of the etch stop layer 15 in which the drain pad 5a is formed, and the other side is formed in parallel with the etch stop layer 15 via the air gap 25. A support layer 30 having a cross section, a lower electrode 35 stacked on top of the support layer 30, a strained layer 40 stacked on top of the lower electrode 35, and an upper portion of the strained layer 40. The stacked upper electrode 45 and one side of the strained layer 40 are perpendicular to the drain pad 5a through the lower electrode 35, the support layer 30, the etch stop layer 15, and the protective layer 10. The via electrode 50 includes a via contact 55 formed to electrically connect the lower electrode 35 and the drain pad 5a to each other.

A stripe 46 is formed on one side of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly to prevent diffuse reflection of light incident from the light source.

In the M × N (M, N is an integer) P-MOS transistors embedded in the active matrix 1, the gate 2 serves as a switch for turning on / off the MOS transistor. The first signal (image signal) enters the source 4 from the outside. When the gate 2 is turned on, the actuator 60 connected to the drain 3 through the drain pad 5a is operated by the first signal transmitted from the source 4. . Here, Rpzt and Cpzt represent the resistance and capacitance of the strained layer 40, respectively.

Hereinafter, a method of manufacturing the thin film type optical path control device will be described with reference to FIGS. 3A to 3D. 3A to 3D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 3A, Phosphor-Silicate Glass is formed on an active matrix 1 in which M × N (M and N are integers) P-MOS transistors are embedded and a drain pad 5a is formed on one side thereof. : A protective layer 10 composed of PSG) is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm by using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded from subsequent processes.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 0.01 to 1.0 탆 using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 19 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm using the Atmospheric Pressure Vapor Deposition (APCVD) method. do. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 20 is planarized by using a spin-on glass (SOG) method or a chemical mechanical polishing (CMP) method. Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5a is formed is etched to expose a portion of the etch stop layer 15 to form a position where the supporting portion of the actuator 60 is to be formed.

Referring to FIG. 3B, a support layer 30 having a thickness of about 0.1 to 1.0 μm is formed on the exposed etch stop layer 15 and the sacrificial layer 20. The support layer 30 is formed of nitride using a low pressure chemical vapor deposition (LPCVD) method. At this time, the stress in the support layer 30 is controlled by forming the support layer 30 while varying the ratio of the reaction gas in the reaction vessel of low pressure.

The lower electrode 35 made of a metal such as platinum (Pt) or platinum-tantalum (Pt-Ta) is formed on the support layer 30. The lower electrode 35 is formed to have a thickness of about 0.01 to 1.0 탆 using the sputtering method. Subsequently, the lower electrode 35 is etched by a reactive ion etching process using an etching end point to separate the lower electrode 35 for each pixel, thereby making the first signal independent of each pixel (image signal). Allow to be applied (Iso-Cut process).

The deformation layer 40 made of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 35. The strained layer 40 is formed to have a thickness of about 0.1-1 .0 μm, preferably about 0.4 μm by using a sol-gel method, and then the strained layer 40 The piezoelectric material constituting the phase change phase using a rapid thermal annealing (RTA) method. The strained layer 40 is deformed by an electric field generated between the upper electrode 45 and the lower electrode 35.

The upper electrode 45 is formed on the strained layer 40. The upper electrode 45 is formed of a metal having excellent electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. The second signal (bias signal) is applied to the upper electrode 45 from the outside through a common electrode line (not shown). In addition, the upper electrode 45 also functions as a mirror that reflects light incident from the light source.

Subsequently, the upper electrode 45 is patterned into a predetermined pixel shape. In this case, the stripe 46 is patterned to form one side of the upper electrode 45. In addition, the strained layer 40 and the lower electrode 35 are each patterned to have a predetermined pixel shape.

Referring to FIG. 3C, the strained layer 40, the lower electrode 35, the support layer 30, the etch stop layer 15, and the protective layer may be formed from an upper portion of one side of the strained layer 40 to an upper portion of the drain pad 5a. The via hole 50 is formed by sequentially etching 10). Subsequently, a metal contact such as tungsten, platinum or titanium is sputtered to form a via contact 55 that electrically connects the drain pad 5a and the lower electrode 35. Therefore, the via contact 55 is formed vertically from the lower electrode 35 to the upper portion of the drain pad 5a in the via hole 50. Therefore, the first signal (image signal) applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5a, and the via contact 55 built in the active matrix 1.

Referring to FIG. 3D, a photoresist layer (not shown) is coated on the entire surface of the resultant product on which the via contact 55 is formed and patterned to expose the support layer 30. Subsequently, the support layer 30 is anisotropically etched using the photoresist layer as an etching mask to pattern the pixel in a predetermined pixel shape. Subsequently, after forming the air gap 59 by isotropically etching the sacrificial layer 20 by 49% hydrogen fluoride (HF) vapor using the photoresist layer as an etching mask, rinsing and drying are performed. To complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal (image signal) is applied to the lower electrode 35 through the drain pad 5a and the via contact 55 from the MOS transistor embedded in the active matrix 1. In addition, a second signal (bias signal) is applied to the upper electrode 45 through the common electrode line to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent in a direction opposite to the direction in which the support layer 30 is formed. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle and then projected onto a screen to form an image.

However, the above-described thin film type optical path control device may cause a failure of one or more transistors in the M × N MOS transistors embedded in the active matrix due to many factors generated during the manufacturing process. As a result, point-defect or line-defect of the AMA device corresponding to the MOS transistor may occur.

Accordingly, it is an object of the present invention to provide a thin film type optical path control apparatus and a method for manufacturing the same, which can significantly reduce the number of point-defects or line-defects of an AMA device that may occur due to elements in the manufacturing process.

1 is a cross-sectional view of the thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is an equivalent circuit diagram of the apparatus shown in FIG.

3A to 3D are cross-sectional views for explaining the manufacturing method of the apparatus shown in FIG.

4 is a plan view of the support layer of the thin film type optical path control apparatus according to the present invention.

5 is a cross-sectional view taken along line A-A 'of the apparatus shown in FIG.

6 is an equivalent circuit diagram of the apparatus shown in FIG.

7A to 7F are cross-sectional views for explaining the manufacturing method of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

131: active matrix 133: actuator

135: drain pad 137: protective layer

139: etch stop layer 141: sacrificial layer

143: support layer 145: lower electrode

147: strained layer 149: upper electrode

151 stripe 153 empty hole

155: beer contact 157: air gap

In order to achieve the above object, the present invention includes a first active matrix having M × N (M, N is an integer) first MOS transistors and a first drain pad formed on one side thereof; A second active matrix formed on the first active matrix and having M × N (M, N is an integer) second MOS transistors embedded therein and a second drain pad formed on one side thereof; And it provides a thin film-type optical path control device comprising an actuator formed on the second active matrix. The actuator may include: i) a support layer having one side in contact with an upper portion of the second active matrix and the other side parallel to the second active matrix via an air gap, ii) a lower electrode formed on the support layer, iii) the And a strained layer formed on the lower electrode, and iv) an upper electrode formed on the strained layer.

In addition, to achieve the above object, the present invention provides a method of manufacturing a semiconductor device comprising: providing a first active matrix in which M × N (M, N is an integer) first MOS transistors are built and a first drain pad is formed on one side; Providing a second active matrix having M × N (M, N is an integer) second MOS transistors disposed on the first active matrix and having a second drain pad formed on one side thereof; And i) forming a support layer on top of the second active matrix and forming a support layer in parallel with the second active matrix through one side of the second active matrix and through the air gap. Forming an actuator on the lower electrode, iii) forming a strained layer on top of the lower electrode, and iv) forming an upper electrode on top of the strained layer. Provided are methods of manufacturing the device.

In the thin film type optical path control device according to the present invention, the first signal (image signal) transmitted from the outside is applied to the lower electrode through the transistor, the drain pad, and the via contact embedded in the active matrix. At the same time, a second signal (bias signal) is applied to the upper electrode from the outside to generate an electric field between the upper electrode and the lower electrode. Due to this electric field, the strained layer between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction orthogonal to the electric field, whereby the actuator including the strained layer is bent at a predetermined angle. The upper electrode, which also functions as a mirror that reflects light, is formed on the actuator and is inclined with the actuator. Accordingly, the upper electrode reflects light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the thin film type optical path adjusting device according to the present invention, the active matrix is formed in a two-layer structure, that is, a structure in which a second active matrix is laminated on the first active matrix. M × N first MOS transistors are embedded in the first active matrix, and M × N second MOS transistors are embedded in the second active matrix. The first MOS transistor and the second MOS transistor are connected in parallel, and the first source, the first drain, and the first gate of the first MOS transistor are connected to the second MOS transistor through respective source pads, drain pads, and gate pads. Is connected to a second source, a second drain and a second gate. An actuator is formed on the second active matrix, and a lower electrode of the actuator is electrically connected to the second drain pad of the second active matrix.

Since the second drain pad of the second active matrix is electrically connected to the first drain pad of the first active matrix, the actuator is also electrically connected to the first drain pad. Thus, when any of the first or second MOS transistors do not operate, the actuator can be driven by the second or first MOS transistors connected in parallel thereto. In addition, since the active matrix of the present invention is formed in a vertically stacked two-layer structure, there is an advantage that the size of the active matrix does not have to be increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a support layer of the thin film type optical path control apparatus according to the present invention, FIG. 5 is a cross-sectional view taken along line AA ′ of the apparatus shown in FIG. 4, and FIG. 6 is an apparatus shown in FIG. 5. An equivalent circuit diagram of is shown.

4 to 6, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 131 and an actuator 133 formed on the active matrix 131.

The active matrix 131 includes a first M × N (M, N is an integer) first MOS transistor (eg, a first P-MOS transistor) and a first drain pad 135a formed on one surface thereof. An active matrix 131a and an M × N second MOS transistor (eg, a second P-MOS transistor) are formed on the first active matrix 131a and have a second drain pad 135b on one surface thereof. ) Is formed of the second active matrix 131b.

The first MOS transistor embedded in the first active matrix 131a includes a first gate 102, a first drain 104, and a first source 106, and is embedded in the second active matrix 131b. The second MOS transistor includes a second gate 112, a second drain 114, and a second source 116. The first MOS transistor and the second MOS transistor are connected in parallel, and include a first drain 104 and a second drain 114, a first source 106 and a second source 116, and a copper first gate 102. And the second gate 112 are electrically connected to each other through a first via contact 109, a second via contact 119, and a gate via contact (not shown), respectively. That is, the first via hole 108 is formed vertically from the bottom of the second drain pad 135b to the first drain pad 135a through the second active matrix 131b and the first protective layer 120. A first via contact 109 is formed in the first via hole 108 to electrically connect the first drain pad 135a and the second drain pad 135b. In addition, a second via hole 118 is vertically formed from the bottom of the second source pad 125b to the first source pad 125a through the second active matrix 131b and the first passivation layer 120. A second via contact 119 is formed in the second via hole 118 to electrically connect the first source pad 125a and the second source pad 125b. In addition, the first gate 102 and the second gate 112 may be perpendicular from the bottom of the second gate 112 to the first gate 102 through the second active matrix 131b and the first passivation layer 120. Gate via contacts (not shown) are formed to electrically connect the &lt; RTI ID = 0.0 &gt;

A first passivation layer 120 is formed between the first active matrix 131a and the second active matrix 131b, and the first passivation layer 120 is formed of the first active matrix 131a. 1 Protects MOS transistors. The second active matrix 131b is disposed on the second protective layer 137 and the second protective layer 137 stacked on the second active matrix 131b and the second drain pad 135b. The stacked etch stop layer 139 is included.

One side of the actuator 133 is in contact with a portion of the etch stop layer 139 in which the second drain pad 135b is formed, and the other side thereof is parallel to the etch stop layer 139 through the air gap 157. A support layer 143 having a cross-sectional shape formed thereon, a lower electrode 145 formed on the support layer 143, a strain layer 147 formed on the lower electrode 145, and an upper electrode formed on the strain layer 147. 149, and from one side of the strained layer 147 to the second drain pad 135b through the lower electrode 145, the support layer 143, the etch stop layer 139, and the second protective layer 137. The third via hole 153 includes a third via contact 155 formed to electrically connect the lower electrode 145 and the second drain pad 135b to each other. Here, since the second drain pad 135b is electrically connected to the first drain pad 135a through the first via contact 109, the lower electrode 145 of the actuator 133 may be the first drain pad. It is also electrically connected to 135a.

In addition, referring to FIG. 5, the plane of the support layer 143 is formed in a shape in which one side thereof has a rectangular concave portion at the center thereof, and the concave portion becomes stepped toward both edges. The other side of the plane of the support layer 143 has a rectangular protrusion that narrows stepwise toward the central portion corresponding to the concave portion. Therefore, the protrusion of the support layer of the actuator adjacent to the concave portion of the support layer 143 is fitted, and the rectangular protrusion is fitted to the concave portion of the support layer of the adjacent actuator.

The stripe 151 is formed at one side of the upper electrode 149. The stripe 151 operates the upper electrode 149 uniformly to prevent diffuse reflection of light incident from the light source.

Hereinafter, a method of manufacturing a thin film type optical path control apparatus according to a preferred embodiment of the present invention will be described in detail with reference to the drawings.

7A to 7F are cross-sectional views illustrating a method of manufacturing the apparatus shown in FIG. 5. In Figs. 7A to 7F, the same reference numerals are used for the same members as Fig. 5.

Referring to FIG. 7A, a first active matrix made of a semiconductor such as silicon (Si) or made of an insulating material such as glass or alumina (Al <SB> 2 </ SB> O <SB> 3 </ SB>) After forming 131a, a first device isolation layer 101 for defining a first active region in the first active matrix 131a using a conventional device isolation process, for example, local oxidation of silicon (LOCOS). ). Subsequently, after forming the first gate 102 on the first active region, the first drain 104 and the first source 106 are formed by an ion implantation process, thereby forming M × N first MOS transistors. (Eg, a first P-MOS transistor) is formed. Next, after forming a first insulating film 103 made of an oxide on the resultant, an opening for exposing the top of one side of the first drain 104 and the top of one side of the first source 106 by a photolithography process. Form them.

Subsequently, a metal, such as tungsten (W), is deposited on the resultant formed product and then patterned by a photolithography process to form a first drain pad 135a on one side of the first drain 104. The first source pad 125a is formed on one side of the first source 106.

Subsequently, a first passivation layer 120 is formed on the first active matrix 131a on which the first drain pad 135a and the first source pad 125a are formed. The first protective layer 120 is formed of a silicate glass (PSG) to have a thickness of about 1.0㎛ using a chemical vapor deposition (CVD) method. The first protective layer 120 prevents damage to the first MOS transistor embedded in the first active matrix 131a from a subsequent process. Since the first protective layer 120 covers the upper portion of the first active matrix 131a in which the first MOS transistor is embedded, the surface flatness is very poor. Therefore, the surface of the first protective layer 120 is planarized using a chemical mechanical polishing (CMP) method.

Subsequently, amorphous silicon or polycrystalline silicon is deposited on the planarized first passivation layer 120 by chemical vapor deposition (CVD). The amorphous silicon or polycrystalline silicon is then recrystallized by solid phase sintering at about 600 ° C. for 10 hours. Subsequently, the recrystallized layer is planarized by a chemical mechanical polishing (CMP) method to form a second active matrix 131b. Therefore, according to the present invention, the active matrix 131 is formed in a vertical two-layer structure in which the second active matrix 131b is stacked on the first active matrix 131a.

Referring to FIG. 7B, a second device isolation layer 111 is formed in the second active matrix 131b to define a second active region using a conventional device isolation process, for example, a LOCOS process. Next, after forming the second gate 112 on the second active region, the second drain 114 and the second source 116 are formed by an ion implantation process, thereby forming M × N second MOSs. A transistor (for example, a second P-MOS transistor) is formed.

Next, an insulating material such as an oxide is deposited on the resultant to form the second insulating film 113, and then the second insulating film 113, the second active matrix 131b, and the first using a photolithography process. By sequentially etching the passivation layer 120, the first via hole 108 and the second via hole exposing the first drain pad 135a, the first source pad 125a, and the first gate 102, respectively. 118 and gate via holes (not shown). Subsequently, after depositing a metal such as tungsten (W) on the resultant, the first via hole 108 and the second via hole using a chemical mechanical polishing (CMP) process or an etch-back process. 118 and the gate via hole are filled with the metal.

Next, a metal such as tungsten (W) is deposited on the resultant, and then patterned by a photolithography process, thereby forming a second drain pad 135b on one side of the second drain 114 and forming the second drain pad 135b. A second source pad 125b is formed on one side of the source 106. As a result, the first via contact 109 and the first source pad 125a and the second source pad 125b that electrically connect the first drain pad 135a and the second drain pad 135b are electrically connected to each other. A second via contact 119 for connecting and a gate via contact (not shown) for electrically connecting the first gate 102 and the second gate 112 are formed.

If the source / drain 106, 104 of the first MOS transistor and the source / drain 116, 114 of the second MOS transistor are directly electrically connected in the junction region, the active matrix 131a, 131b Si atoms may diffuse into the tungsten layer used as the via contact as the temperature increases. As such, when the diffusion movement of the silicon atoms is locally deep, junction spiking occurs, which may cause cracking of the PN junction, thereby causing a problem of breaking the junction. Therefore, in the present invention, the source / drain 106 and 104 of the first MOS transistor and the source / drain 116 and 114 of the second MOS transistor are not directly connected in the junction region in order to prevent junk spiking. The source pads 125a and 125b and the drain pads 135a and 135b are indirectly connected to each other.

Referring to FIG. 7C, a second passivation layer 137 is formed on the second active matrix 131b on which the second source pad 125b and the second drain pad 135b are formed. The second protective layer 137 is formed of a silicate glass (PSG) to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The second protective layer 137 prevents the second MOS transistor embedded in the second active matrix 131b from being damaged from a subsequent process.

Subsequently, an etch stop layer 139 is formed on the second passivation layer 137. The etch stop layer 139 is formed using a low pressure chemical vapor deposition (LPCVD) method so as to have a thickness of about 0.1 to 1.0 μm. The etch stop layer 139 prevents the second passivation layer 137 and the second active matrix 131b from being etched during the subsequent etching process.

Subsequently, a sacrificial layer 141 is formed on the etch stop layer 139. The sacrificial layer 141 is formed of phosphorus silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 141 covers the upper portion of the second active matrix 131b in which the second MOS transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 141 is planarized by polishing using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 141 in which the second drain pad 135b is formed is etched to expose a portion of the etch stop layer 139 to form a position where the support portion of the actuator 133 is to be formed. .

Referring to FIG. 7D, a support layer 143 having a thickness of about 0.1 to 1.0 μm is formed on the exposed etch stop layer 139 and the sacrificial layer 141. The support layer 143 is formed of a rigid material such as nitride or metal using low pressure chemical vapor deposition (LPCVD). At this time, the stress in the support layer 143 is adjusted by forming the support layer 143 while changing the ratio of the reaction gas in the low pressure reaction vessel.

Subsequently, a lower electrode 145 made of a metal having electrical conductivity such as platinum, tantalum, or platinum-tantalum is formed on the support layer 143. The lower electrode 145 is formed to have a thickness of about 0.01 to 1.0 µm using a sputtering method. The lower electrode 145, which is a signal electrode, receives a first signal (image signal) from a transistor embedded in the first active matrix 131a or the second active matrix 131b. 135b). Subsequently, the lower electrode 145 is etched by using a reactive ion etching method using an etch end point to separate the lower electrode 145 for each pixel so that an independent first signal is applied to each pixel. do.

Subsequently, a strained layer 147 made of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 145. The strained layer 147 is formed to a thickness of 0.1 to 1.0 탆 using any one of a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method. After being formed to have a thickness of about 0.4 [mu] m by the gel method, the piezoelectric material constituting the strained layer 147 is phase shifted and polarized using a rapid heat treatment (RTA) method. The deformation layer 147 is deformed by an electric field generated between the upper electrode 149 and the lower electrode 145.

Subsequently, an upper electrode 149 is formed on the strained layer 147. The upper electrode 149 is formed of a metal having excellent electrical conductivity and reflectivity, such as aluminum (Al), silver (Ag), or platinum (Pt), to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. . The second electrode (bias signal) is applied to the upper electrode 149 through a common electrode line (not shown), and at the same time, the upper electrode 149 also functions as a mirror that reflects light incident from the light source.

Next, the upper electrode 149, the strain layer 147, and the lower electrode 145 are sequentially patterned to have a predetermined pixel shape. That is, after forming a photoresist layer (not shown) resistant to the material to be etched on the upper electrode 149, the upper electrode 149 is patterned. In this case, a stripe 151 is formed at one side of the upper electrode 149 to uniformly operate the upper electrode 149 to prevent diffuse reflection of light incident from the light source. Subsequently, a photoresist protective layer (not shown) is again formed on the patterned upper electrode 149 and the strained layer 147, and then the strained layer 147 is patterned into a predetermined pixel shape. In this manner, the lower electrode 145 is also patterned into a predetermined pixel shape.

Referring to FIG. 7E, the strained layer 147 is formed from a portion of the strained layer 147 in which the second drain pad 135b is formed below the upper portion of the second drain pad 135b by using a photolithography process. ), The lower electrode 145, the support layer 143, the etch stop layer 139, and the second passivation layer 137 are sequentially etched to form the third via hole 153. Subsequently, a third via contact 155 is formed to deposit a metal such as tungsten (W), platinum (Pt), or titanium (Ti) to electrically connect the second drain pad 135b and the lower electrode 145. do. Accordingly, the third via contact 155 is vertically formed from the lower electrode 145 to the upper portion of the second drain pad 135b in the third via hole 153. Here, since the second drain pad 135b is electrically connected to the first drain pad 135a through the first via contact 109, the lower electrode 145 is also electrically connected to the first drain pad 135a. Is connected. Therefore, the first signal (image signal) applied from the outside is a transistor, a first drain pad 135a or a second drain pad 135b embedded in the first active matrix 131a or the second active matrix 131b, and It is applied to the lower electrode 145 through the third via contact 155.

Referring to FIG. 7F, after forming a photoresist protective layer (not shown) to cover the exposed surfaces of the upper electrode 149, the strained layer 147, and the lower electrode 145, the photoresist protective layer (not shown) is used as an etching mask. The support layer 143 is patterned to have a predetermined pixel shape.

Subsequently, the sacrificial layer 141 is etched using hydrogen fluoride (HF) vapor using the photoresist protective layer as an etching mask to form an air gap 157, followed by rinsing and drying to perform AMA. Complete the device.

As described above, after completing the M × N thin film type AMA devices, a metal such as chromium (Cr), nickel (Ni), or gold (Au) is sputtered or evaporated into the active matrix 131. It is deposited at the bottom to form an ohmic contact (not shown). Next, a TCP (Tape Carrier Package) (not shown) bonding for applying a second signal (bias signal) to the upper electrode 149 and a first signal (image signal) to the lower electrode 145 is prepared. The second active matrix 131b is cut to a predetermined thickness by using a normal photolithography process. Subsequently, a photoresist layer (not shown) is formed on the pad of the AMA panel so that the pad of the AMA panel (not shown) has a sufficient height during TCP bonding. Subsequently, a portion of the photoresist layer, in which no pad is formed, is patterned to expose the pad of the AMA panel. Next, the photoresist layer is etched by a dry etching method or a wet etching method, and the first active matrix 131a and the second active matrix 131b are completely cut into a predetermined shape, and then the pad of the AMA panel and the TCP are etched. The pad is connected to an anisotropic conductive film (ACF) (not shown) to complete the manufacture of the thin film type AMA module.

In the above-described thin film type optical path control device of the present invention, the first signal transmitted through the pad of TCP and the pad of AMA panel is the first drain pad 135a or the second drain from the MOS transistor embedded in the active matrix 131. The pad 135b and the third via contact 155 are applied to the lower electrode 145. At the same time, the second signal transmitted through the pad of the TCP, the pad of the AMA panel and the common electrode line is applied to the upper electrode 149 to generate an electric field between the upper electrode 149 and the lower electrode 145. Due to such an electric field, the deformation layer 147 formed between the upper electrode 149 and the lower electrode 145 causes deformation. The strained layer 147 contracts in a direction orthogonal to the electric field, and the actuator 133 including the strained layer 147 is bent in a direction opposite to the direction in which the support layer 143 is formed. Therefore, the upper electrode 149 which also functions as a mirror on the actuator 133 is inclined in the same direction. Accordingly, the light incident from the light source is reflected by the inclined upper electrode 149 at a predetermined angle, and then passes through the slit to be projected onto the screen to form an image.

As described above, according to the thin film type optical path adjusting device according to the present invention, the active matrix is formed in a two-layer structure, that is, a structure in which a second active matrix is laminated on the first active matrix. M × N first MOS transistors are embedded in the first active matrix, and M × N second MOS transistors are embedded in the second active matrix. The first MOS transistor and the second MOS transistor are connected in parallel, wherein the first source and the first drain of the first MOS transistor are connected to the second and second sources of the second MOS transistor through respective source pads and drain pads. Connected to the drain. An actuator is formed on the second active matrix, and a lower electrode of the actuator is electrically connected to the second drain pad of the second active matrix.

Since the second drain pad of the second active matrix is electrically connected to the first drain pad of the first active matrix, the actuator is also electrically connected to the first drain pad. Thus, if any of the first or second MOS transistors do not operate due to various factors in the manufacturing process, the actuator may be driven by the second or first MOS transistors connected in parallel thereto, thus causing a point-fault or line in the AMA device. The number of defects can be significantly reduced. In addition, since the active matrix of the present invention is formed in a vertically stacked two-layer structure, there is an advantage that the size of the active matrix does not have to be increased.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (6)

A first active matrix 131a in which M × N (M and N are integer) embedded therein and having a first drain pad 135a formed on one side thereof; A second active matrix 131b formed on the first active matrix and having M × N (M, N is an integer) second MOS transistors embedded therein and a second drain pad 135b formed on one side thereof; And i) a support layer 143 formed on one side of the second active matrix 131b and parallel to the second active matrix 131b via an air gap 153, and ii) the support layer ( An actuator having a lower electrode 145 formed on top of 143, iii) a strained layer 147 formed on top of the lower electrode 145, and iv) an upper electrode 148 formed on top of the strained layer 147 Thin film type optical path control device comprising a (133). The method of claim 1, further comprising a first passivation layer 120 formed between the first active matrix 131a and the second active matrix 131b to protect the first MOS transistor. Thin film type optical path control device. The method of claim 1, wherein the first drain pad 131a and the second drain pad 131b are vertically formed from the bottom surface of the second drain pad 131b to the first drain pad 131a. And a first via contact (109) for connecting. The second source device of claim 1, wherein the first source pad 125a is formed on one side of the first source 106 of the first MOS transistor, and the second is formed on one side of the second source 116 of the second MOS transistor. It is formed vertically from the bottom of the source pad (125b) and the second source pad (125b) to the first source pad (125a) to electrically connect the first source pad (125a) and the second source pad (125b). And a second via contact (119). The second active matrix 131b of claim 1, wherein the second active matrix 131b includes a second protective layer 137 and the second protective layer formed on the second active matrix 131b and the second drain pad 135b. Thin film type optical path control device further comprises an etch stop layer (139) formed on top of the 137. 2. The actuator 133 of claim 1, wherein the actuator 133 is vertically formed from an upper portion of the deformable layer 147 to the second drain pad 135b to form the lower electrode 145 and the second drain pad 135b. Thin film type optical path control device further comprises a third via contact (155) for electrically connecting the.

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