KR100257158B1 - Thin film transistor and method for manufacturing the same - Google Patents

Thin film transistor and method for manufacturing the same Download PDF

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KR100257158B1
KR100257158B1 KR1019970030434A KR19970030434A KR100257158B1 KR 100257158 B1 KR100257158 B1 KR 100257158B1 KR 1019970030434 A KR1019970030434 A KR 1019970030434A KR 19970030434 A KR19970030434 A KR 19970030434A KR 100257158 B1 KR100257158 B1 KR 100257158B1
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layer
thin film
film transistor
amorphous silicon
silicon layer
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KR19990006212A (en
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이근수
서국진
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김영환
현대전자산업주식회사
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Priority to TW087110034A priority patent/TW376588B/en
Priority to JP18343898A priority patent/JPH11121761A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE: A thin film transistor and a method of fabricating the same are to increase a field effect mobility and reduce an off leakage current and an optical leakage current, thereby improving a picture quality. CONSTITUTION: A gate electrode(31) is formed on a semiconductor substrate(30). A gate insulating layer(32) is formed on an entire structure. A channel layer(330) is formed on the gate insulating layer. The channel region includes a micro crystalline silicon layer(33A) and an amorphous silicon layer(33B). The micro crystalline silicon layer increases field effect mobility. The amorphous silicon layer includes chlorine, which reduces an optical and electrical conductivity. The amorphous silicon layer is deposited by a PECVD(plasma enhanced chemical vapor deposition) method. The amorphous silicon layer is selected from the group consisting of SiH2Cl2/SiH4 and SiCl4/SiH4.

Description

박막 트랜지스터 및 그의 제조 방법Thin film transistor and method of manufacturing the same

본 발명은 액정 표시 소자의 박막 트랜지스터(TFT-LCD) 및 그의 제조방법에 관한 것으로, 보다 구체적으로는, 박막 트랜지스터의 채널 구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT-LCD) of a liquid crystal display device and a manufacturing method thereof, and more particularly, to a channel structure of a thin film transistor and a manufacturing method thereof.

일반적으로, 액정 표시 소자는 텔레비젼 또는 그래픽 디스플레이 등의 표시소자로서 활발히 사용된다. 그중, 특히 액티브 매트릭스형 액정 표시 소자는 고속 응답성을 지니고, 높은 화소 개수를 갖는데 알맞으며, 디스플레이 화면의 고 화질화, 대형화, 컬러 화면화 등을 실현하는 것으로서 기대되어, 개발 연구가 진전되고 있다.Generally, liquid crystal display elements are actively used as display elements such as televisions or graphic displays. Among them, the active matrix liquid crystal display device is particularly suitable for having high speed response and having a high number of pixels, and is expected to realize high image quality, large size, color screen, and the like of the display screen, and development research is being advanced. .

이 액티브 매트릭스형 액정 표시 소자에서, 투명 절연 기판상에 게이트 라인과 드레인 라인 형성되고, 게이트 라인과 드레인 라인이 교차하는 점에는 다이오드나 박막 트랜지스터와 같은 스위칭 소자와 화소 전극이 각각 배치, 설계된다.In this active matrix liquid crystal display device, a gate line and a drain line are formed on a transparent insulating substrate, and switching elements such as diodes or thin film transistors and pixel electrodes are arranged and designed at the intersections of the gate line and the drain line.

화소 전극은 스위칭 소자에 의하여 구동이 독립적으로 제어되므로, 화소전극의 고속 구동이 가능하고, 또 고 화소수화나 대 면적화가 가능하다.Since the driving of the pixel electrode is independently controlled by the switching element, high-speed driving of the pixel electrode is possible, and high pixel number and large area can be achieved.

여기서, 스위칭 소자로는 급준한 온, 오프 특성을 지니는 박막 트랜지스터가 주로 이용된다.Here, as the switching element, a thin film transistor having steep on and off characteristics is mainly used.

이러한, 박막 트랜지스터의 전형적인 일 예가 제1도에 도시되어 있다.A typical example of such a thin film transistor is shown in FIG.

제1도를 참조하여 설명하면, 하부 기판(10)상부에 게이트 전극(11)을 형성한후, 게이트 전극(11)을 포함한 기판(10)상에 게이트 절연층(12)을 증착한다.Referring to FIG. 1, after the gate electrode 11 is formed on the lower substrate 10, the gate insulating layer 12 is deposited on the substrate 10 including the gate electrode 11.

이어, 활성층으로서, 수소화된 비정질 실리콘층(a-Si: H, 13)을 게이트 절연층(12)의 상부 전면에 걸쳐 증착한다. 그리고 나서, 수소화된 비정질 실리콘층 상부에 에치 스톱퍼용 절연막을 증착하고, 하부 게이트 전극(11)의 소정 부분을 포함하는 위치에만 존재하도록 패터닝하여, 에치 스톱퍼(14)를 형성한다.Subsequently, as an active layer, a hydrogenated amorphous silicon layer (a-Si: H, 13) is deposited over the upper entire surface of the gate insulating layer 12. Then, an insulating film for an etch stopper is deposited on the hydrogenated amorphous silicon layer and patterned so as to exist only at a position including a predetermined portion of the lower gate electrode 11 to form an etch stopper 14.

그 후, 불순물이 도핑된 비정질 실리콘층(n+ a-Si : H)을 적층하고, 박막 트랜지스터의 영역을 한정하기 위하여, 도핑된 비정질 실리콘층(n+ a-Si : H,(15)) 및 수소화된 비정질 실리콘층(a-Si : H,(13))을 패터닝하여, 오믹 접촉층(15)을 형성한다.Thereafter, an amorphous silicon layer (n + a-Si: H) doped with impurities and a layer of a thin film transistor are laminated to define an area of the thin film transistor, and hydrogenated doped amorphous silicon layer (n + a-Si: H, 15) and hydrogenation. The amorphous silicon layer (a-Si: H, 13) is patterned to form an ohmic contact layer 15.

다음으로 전체 상부에 소오스/드레인용 금속막을 소정 두께로 증착한 다음, 예정된 전그그이 형태로 소정 부분 패터닝한다. 이때, 에치 스톱퍼(14)가 노출되도록 패턴된 금속막(16) 및 도핑된 비정질 실리콘층(a-Si : H(15))을 식각하여 소오스/드레인 전극을 형성한다.Next, a source / drain metal film is deposited on the entire upper portion at a predetermined thickness, and then predetermined portions are patterned into a predetermined electric tag. At this time, the patterned metal layer 16 and the doped amorphous silicon layer (a-Si: H (15)) are etched to expose the etch stopper 14 to form a source / drain electrode.

그러나, 상술한 바와 같이, 수소화된 비정질 실리콘(이하 a-Si:H)막을 활성층으로 이용할 경우 다음과 같은 문제점이 발생된다.However, as described above, when the hydrogenated amorphous silicon (hereinafter referred to as a-Si: H) film is used as the active layer, the following problems occur.

상기한 수소화된 비정질 실리콘막은 전계 효과 이동도가 비교적 낮고, 광 전기 전도도가 높기 때문에, 백 라이드 조명하에서 광누설 전류가 발생된다. 즉, 광 조사가 이루어지면, 누설 전류가 흐르게 되어, 많은 양의 누설 전류가 발생하게 되는 것이다.Since the hydrogenated amorphous silicon film has a relatively low field effect mobility and high photoelectric conductivity, photoleakage current is generated under backlight illumination. That is, when light irradiation is made, a leakage current will flow and a large amount of leakage current will generate | occur | produce.

이러한, 낮은 전계 효과 이동도 특성을 방지하기 위하여, 종래의 다른 방법으로 채널층을 미세 결정질 실리콘(μc-Si)으로 형성하는 방법이 제안되었다. 그러나, 상기한 방법은 전계 효과 이동도는 개선되나, 오프 전류(off-current)가 심하게 발생된다.In order to prevent such low field effect mobility characteristics, a method of forming a channel layer from microcrystalline silicon (μc-Si) has been proposed by another conventional method. However, the above method improves the field effect mobility, but off-current is severely generated.

이를 방지하고자, 종래의 또 다른 방식으로는, 자기 정렬(Self-Alignment)된 형태의 박막 트랜지스터가 제안되었다.In order to prevent this, as another conventional method, a self-aligned thin film transistor has been proposed.

이 구조는 제2도에 도시된 바와 같이, 게이트 전극(21)이 형성된 하부 기판(20) 상부에 게이트 절연층(22)을 표면이 평탄하도록 형성한다. 이어서, 평탄화된 게이트 절연층(22) 상부에 상기 게이트 전극(21)을 포함하도록 패널층(23), 바람직하게는 비정질 실리콘층으로 형성한다. 그리고나서, 채널층(23) 상부의 소정 부분에 에치 스톱퍼(25)를 형성하고, 에치 스톱퍼(24) 양 측에 불순물을 주입하여, 오믹 접촉층(25)을 형성한 다음, 이 오믹 접촉층(25)과 콘택되도록 소오스/드레인 전극(26)을 형성한다.As shown in FIG. 2, the structure forms the gate insulating layer 22 on the lower substrate 20 on which the gate electrode 21 is formed so as to have a flat surface. Subsequently, the panel layer 23, preferably, an amorphous silicon layer, is formed to include the gate electrode 21 on the planarized gate insulating layer 22. Then, an etch stopper 25 is formed in a predetermined portion above the channel layer 23, impurities are injected into both sides of the etch stopper 24 to form an ohmic contact layer 25, and then the ohmic contact layer. The source / drain electrode 26 is formed to be in contact with 25.

그러나, 상술한 방법은 오프 전류는 방지되나, 백 라이트 조사시, 불투명한 게이트 전극에 의하여 차폐되지 않은 부분에서 광 누설 전류가 발생한다는 또 다른 문제점이 발생된다.However, the above-described method prevents the off current, but when the backlight is irradiated, another problem arises that the light leakage current occurs in the portion that is not shielded by the opaque gate electrode.

따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결하기 위한 것으로, 전계 효과 이동도를 증가시키고, 오프 누설 전류를 감소시킴과 동시에 백 라이트 조명시 광누설 전류를 감소시키는 박막 트랜지스터를 제공하는 것이다.Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a thin film transistor which increases the field effect mobility, reduces the off leakage current and reduces the light leakage current during backlight illumination. .

또한, 본 발명의 또 다른 목적은 상기한 박막 트랜지스터의 제조방법을 제공하는 것이다.Further, another object of the present invention is to provide a method of manufacturing the thin film transistor.

제1도는 종래의 기술에 따른 역스테거형 박막 트랜지스터의 단면도.1 is a cross-sectional view of a reverse staggered thin film transistor according to the prior art.

제2도는 종래의 기술에 따른 완전 자기 정렬형 박막 트랜지스터의 단면도.2 is a cross-sectional view of a fully self-aligned thin film transistor according to the prior art.

제3도는 본 발명에 따른 박막 트랜지스터의 단면도.3 is a cross-sectional view of a thin film transistor according to the present invention.

제4a도는 박막 트랜지스터의 채널층으로 수소화된 비정질 실리콘막을 사용하였을 때의 누설 전류량을 도시한 그래프.4A is a graph showing the amount of leakage current when a hydrogenated amorphous silicon film is used as a channel layer of a thin film transistor.

제4b도는 본 발명에 따른 박막 트랜지스터의 누설 전류량을 도시한 그래프.Figure 4b is a graph showing the leakage current amount of the thin film transistor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 20, 30 : 하부 기판 11, 21, 31 : 게이트 전극10, 20, 30: lower substrate 11, 21, 31: gate electrode

12, 22, 32 : 게이트 절연막 13, 23, 33 : 활성층12, 22, 32: gate insulating film 13, 23, 33: active layer

14, 24, 34 : 에치 스토퍼층 15, 25, 35 : 오믹 접촉층14, 24, 34: etch stopper layer 15, 25, 35: ohmic contact layer

16, 26, 36 : 소오스/드레인 전극 33A : 채널층16, 26, 36: source / drain electrodes 33A: channel layer

상기와 본 발명의 목적을 달성하기 위하여, 본 발명은, 게이트 전극이 구비된 하부기판과, 상기 게이트 전극을 포함한 기판 상에 증착된 게이트 절연층과, 상기 게이트 전극의 소정 부분을 포함하는 게이트 절연층 상부에 형성되는 활성층과, 상기 활성층의 일측과 오버랩되는 소오스와, 상기 채널층의 다층과 오버랩되는 드레인을 포함하는 박막 트랜지스터에 있어서, 상기 활성층은 미세 결정질 실리콘(μc-Si)과, 염소가 함유된 비정질 실리콘(a-Si : H(:Cl))이 순차적으로 적층된 구조를 갖는 것을 특징으로 한다.In order to achieve the above object and the object of the present invention, the present invention provides a lower substrate including a gate electrode, a gate insulating layer deposited on a substrate including the gate electrode, and a gate insulation including a predetermined portion of the gate electrode. In the thin film transistor including an active layer formed on an upper layer, a source overlapping with one side of the active layer, and a drain overlapping with the multilayer of the channel layer, the active layer includes fine crystalline silicon (μc-Si) and chlorine. It is characterized in that the amorphous silicon (a-Si: H (: Cl)) contained has a stacked structure sequentially.

또한, 본 발명은 게이트 전극이 구비된 하부 기판 상에 게이트 절연층을 형성하는 공정과, 상기 게이트 절연층 상에 활성층을 형성하는 공정과, 활성층 양 측에 소오스, 드레인을 형성하는 공정을 포함하는 박막 트랜지스터의 제조방법에 있어서, 상기 활성층을 형성하는 공정은, 미세 결정질 실리콘층을 형성하는 공정 및 상기 미세 결정질 실리콘층 상에 염소(Cl)를 포함한 수소화된 비정질 실리콘층을 형성하는 공정을 포함하는 것을 특징으로 한다.The present invention also includes a process of forming a gate insulating layer on a lower substrate provided with a gate electrode, a process of forming an active layer on the gate insulating layer, and a process of forming a source and a drain on both sides of the active layer. In the method of manufacturing a thin film transistor, the step of forming the active layer includes a step of forming a fine crystalline silicon layer and a step of forming a hydrogenated amorphous silicon layer containing chlorine (Cl) on the fine crystalline silicon layer. It is characterized by.

본 발명에 따르면, 박막 트랜지스터의 채널층을 전계 효가 이동도가 높은 미세 결정질 실리콘층(μc-Si)과, 광 및 암 전기전도도를 낮추는 특성을 지닌 염소가 함유된 비정질 실리콘층(a-Si : H(:Cl))의 이중 구조로 형성하여, 박막 트랜지스터의 오프 누설 전류를 감소시키고, 백 라이트에 대한 광 누설 전류를 감소시킬 수 있다.According to the present invention, the channel layer of the thin film transistor is a microcrystalline silicon layer (μc-Si) having high field efficiency mobility, and an amorphous silicon layer (a-Si) containing chlorine having characteristics of lowering light and dark electrical conductivity. By forming a double structure of H (: Cl)), the off leakage current of the thin film transistor can be reduced, and the light leakage current to the backlight can be reduced.

[실시예]EXAMPLE

이하 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부된 도면 제3도는 본 발명에 따른 박막 트랜지스터의 단면도이고, 제4a도는 채널층으로 수소화된 비정질 실리콘막을 사용하였을때의 누설 전류량을 도시한 그래프이고, 제4b도는 본 발명에 따른 박막 트랜지스터의 누설 전류량을 도시한 그래프이다.FIG. 3 is a cross-sectional view of the thin film transistor according to the present invention, and FIG. 4a is a graph showing the leakage current when a hydrogenated amorphous silicon film is used as the channel layer, and FIG. 4b is a leak of the thin film transistor according to the present invention. It is a graph showing the amount of current.

본 발명에 따른 역스테거형 박막 트랜지스터를 제3도를 참조하여 설명하면, 하부 기판(30)상부에 형성된 게이트 전극(31)을 공지의 방식으로 형성한 후, 게이트 전극(31)이 형성된 하부 기판(30) 상부에 게이트 절연층(32), 예를 들어, 실리콘 옥사이드(SiO2)와 옥시 나이트라이드(SiON) 및 실리콘 나이트 라이드(SiNx)의 적층막으로 형성한다.Referring to FIG. 3, the reverse staggered thin film transistor according to the present invention is formed by forming a gate electrode 31 formed on the lower substrate 30 in a known manner, and then forming a lower substrate on which the gate electrode 31 is formed. A gate insulating layer 32, for example, a stacked layer of silicon oxide (SiO 2 ), oxynitride (SiON), and silicon nitride (SiNx) is formed on the top of the layer 30.

이어, 게이트 절연층(32) 상부에 본 발명에 따른 채널층(330)을 형성한다. 여기서, 본 발명에 따른 채널층(330)은, 전계 효과 이동도를 증대시킬 수 있는 미세 결정질 실리콘층(μc-Si, 33A)과, 광 및 암 전기 전도도를 낮추는 특성을 지닌 염소가 함유된 비정질 실리콘층(a-Si : H(Cl) :33B)이 순차적을 적층된다.Next, the channel layer 330 according to the present invention is formed on the gate insulating layer 32. Here, the channel layer 330 according to the present invention includes a microcrystalline silicon layer (μc-Si, 33A) capable of increasing field effect mobility, and an chlorine-containing amorphous material having low light and dark electrical conductivity. Silicon layers (a-Si: H (Cl): 33B) are sequentially stacked.

이때, 염소를 포함한 비정질 실리콘층(a-Si : H(Cl) : 33B)은 SiH2Cl2/SiH4, SiHCl3/SiH4가스 및 SiCl4/SiH4가스와 같은 염소(Cl)가 포함된 혼합 기체를 포함하는 가스 중 선택된 어느 하나의 혼합 가스를 사용하여, 플라즈마 화학 기상 증착(PECVD)법을 형성함이 바람직하다.At this time, the amorphous silicon layer containing chlorine (a-Si: H (Cl): 33B) contains chlorine (Cl), such as SiH 2 Cl 2 / SiH 4 , SiHCl 3 / SiH 4 gas and SiCl 4 / SiH 4 gas It is preferable to form a plasma chemical vapor deposition (PECVD) method using a mixed gas selected from any one of the gases including the mixed gas.

이어서, 게이트 전극(31)을 포함하는 채널층(330) 상부 소정 부분에 공지의 방식에 따라, 에치 스톱퍼층(34)을 형성한다. 그 후에, 하부 기판(30) 결과물 상에 오믹 접촉층(35)으로서, 도핑된 비정질 실리콘층(n+ a-Si : H) 또는 도핑된 미세 결정질 실리콘층(n+ μc-Si)을 형성하고, 박막 트랜지스터의 영역을 한정하기 위하여 오믹 접촉층(35)과, 채널층(330)을 패터닝한다.Subsequently, an etch stopper layer 34 is formed on a predetermined portion of the channel layer 330 including the gate electrode 31 in a known manner. Thereafter, a doped amorphous silicon layer (n + a-Si: H) or a doped microcrystalline silicon layer (n + μc-Si) is formed on the bottom substrate 30 as an ohmic contact layer 35, and the thin film is formed. The ohmic contact layer 35 and the channel layer 330 are patterned to define a region of the transistor.

다음으로, 전체 상부에 소오스/드레인용 금속막을 소정 두께로 증착한 다음, 예정된 전극의 형태로 소정 부분 패터닝된다. 이때, 에치 스토퍼층(34)이 노출되도록 금속막(36) 및 오믹 접촉층(35)을 소정 부분 식각하여 소오스/드레인 전극을 형성함으로서, 박막 트랜지스터가 완성된다.Next, a source / drain metal film is deposited on the whole to a predetermined thickness, and then a predetermined portion is patterned in the form of a predetermined electrode. At this time, the thin film transistor is completed by forming a source / drain electrode by etching the metal film 36 and the ohmic contact layer 35 to expose the etch stopper layer 34.

본 실시예에서는, 미세 결정질 실리콘층(μc-Si : 33A)이 활성층에서 채널층 역할을 하여, 박막 트랜지스터의 전계효과 이동도가 한층 더 개선된다.In this embodiment, the microcrystalline silicon layer (μc-Si: 33A) acts as a channel layer in the active layer, so that the field effect mobility of the thin film transistor is further improved.

또한, 광 누설 전류는 채널층 상부에 관계되므로, 수소화된 비정질 실리콘층보다 광 및 암 전기전도도가 낮은, 염소(Cl)가 함유된 비정질 실리콘층(a-Si : H(Cl))을 사용하므로 광 누설 전류를 감소시키게 된다.In addition, since the light leakage current is related to the upper part of the channel layer, an amorphous silicon layer (a-Si: H (Cl)) containing chlorine (Cl), which has lower light and dark electrical conductivity than the hydrogenated amorphous silicon layer, is used. It reduces the light leakage current.

또, 상기 염소(Cl)이 함유된 비정질 실리콘층(a-Si : H(Cl))은 염소(Cl)의 함유량에 따라, 수소의 양이 변화되어, 활성층의 전기 전도도를 낮추는 역할을 한다.In addition, the amorphous silicon layer (a-Si: H (Cl)) containing chlorine (Cl) changes the amount of hydrogen according to the content of chlorine (Cl), thereby lowering the electrical conductivity of the active layer.

제4a도 및 4b도는 각각 종래의 수소화된 비정질 실리콘으로 활성층으로 형성한 경우의 박막트랜지스터와, 본 발명의 따른 이중구조의 활성층을 갖는 박막트랜지스터의 암 및 빛 조사시의 전류 전압 특성을 비교한 그래프이다.4a and 4b are graphs comparing current and voltage characteristics during dark and light irradiation of a thin film transistor having a conventional active layer made of hydrogenated amorphous silicon and a thin film transistor having a double layer active layer according to the present invention. to be.

암인 상태(Light Intensity =0)에서의 오프 누설전류를 비교하여 보면, 종래의 박막 트랜지스터에 비하여 본 발명에 따른 박막 트랜지스터의 오프 누설전류가 1/100 정도 작게 나타난다. 이는 비정질 실리콘층이 염소(Cl)를 포함하므로써 전기 전도도가 낮아지기 때문이다. 또한 광이 조사된 상태(light Intensity 〉 0)에서의 광누설 전류를 비교하여 보면, 종래의 경우에 비하여 1/10 정도 작게 나타난다. 즉, 백라이트 조명시의 광 누설전류를 대폭 감소시킬 수 있게 된다.In comparison with the off-leakage current in the dark state (Light Intensity = 0), the off-leakage current of the thin film transistor according to the present invention is about 1/100 smaller than that of the conventional thin film transistor. This is because the electrical conductivity is lowered because the amorphous silicon layer contains chlorine (Cl). In addition, when comparing the light leakage current in the light irradiated state (light Intensity> 0), it appears to be about 1/10 smaller than the conventional case. In other words, it is possible to significantly reduce the light leakage current during backlight illumination.

이상에서와 같이, 본 발명의 박막트랜지스터의 제조 방법은 활성층 형성 공정에 있어서, 채널층으로서 미세 결정질 실리콘을 증착하고 미세 결정질 상부에 비정질 실리콘층을 증착하여 이중 구조의 활성층을 형성한다. 따라서 채널층의 전계효과 이동도를 향상시킬 수 있으며, 채널층 상부의 염소가 함유된 비정질 실리콘층을 사용하여 오프 누설전류 및 광 누설전류를 감소시킬 수 있다.As described above, in the method of manufacturing the thin film transistor of the present invention, in the active layer forming process, the microcrystalline silicon is deposited as a channel layer and an amorphous silicon layer is deposited on the microcrystalline top to form an active layer having a double structure. Therefore, the field effect mobility of the channel layer can be improved, and the off leakage current and the light leakage current can be reduced by using an amorphous silicon layer containing chlorine on the channel layer.

또한, TFT-LCD 적용시 누설 전류의 감소로 인하여 화면의 깜박거림(fliker)을 방지하므로써, 화면의 질을 향상시킬 수 있으며 고 품질의 TFT-LCD의 제작에 이용할 수 있다.In addition, by preventing the flicker of the screen due to the reduction of the leakage current when applying the TFT-LCD, the quality of the screen can be improved and can be used to manufacture high-quality TFT-LCD.

Claims (6)

게이트 전극이 구비된 하부기판과, 상기 게이트 전극을 포함한 기판 상에 증착된 게이트 절연층과, 상기 게이트 전극의 소정 부분을 포함하는 게이트 절연층 상부에 형성되는 활성층과, 상기 활성층의 일측과 오버랩되는 소오스와, 상기 채널층의 다층과 오버랩되는 드레인을 포함하는 박막 트랜지스터에 있어서, 상기 활성층은 미세 결정질 실리콘(μc-Si)과, 염소가 함유된 비정질 실리콘(a-Si : H(:Cl))이 순차적으로 적층된 구조를 갖는 것을 특징으로 하는 박막 트랜지스터.A lower substrate provided with a gate electrode, a gate insulating layer deposited on the substrate including the gate electrode, an active layer formed on the gate insulating layer including a predetermined portion of the gate electrode, and overlapping with one side of the active layer A thin film transistor comprising a source and a drain overlapping a multilayer of the channel layer, wherein the active layer comprises microcrystalline silicon (μc-Si) and chlorine-containing amorphous silicon (a-Si: H (: Cl)). The thin film transistor which has this structure laminated sequentially. 제1항에 있어서, 상기 미세 결정질 실리콘층은 활성층내의 채널층으로 동작되어지는 것을 특징으로 하는 박막 트랜지스터.The thin film transistor of claim 1, wherein the microcrystalline silicon layer is operated as a channel layer in an active layer. 제1항에 있어서, 상기 염소를 포함한 비정질 실리콘층의 염소의 양에 따라 비정질 실리콘층 내의 수소량을 변화시켜 전기 전도도를 낮추는 것을 특징으로 하는 박막 트랜지스터.The thin film transistor according to claim 1, wherein the amount of hydrogen in the amorphous silicon layer is changed in accordance with the amount of chlorine in the amorphous silicon layer containing chlorine to lower electrical conductivity. 게이트 전극이 구비된 하부 기판 상에 게이트 절연층을 형성하는 공정과, 상기 게이트 절연층 상에 활성층을 형성하는 공정과, 활성층 양 측에 소오스, 드레인을 형성하는 공정을 포함하는 박막 트랜지스터의 제조방법에 있어서, 상기 활성층을 형성하는 공정은, 미세 결정질 실리콘층을 형성하는 공정 및 상기 미세 결정질 실리콘층 상에 염소(Cl)를 포함한 수소화된 비정질 실리콘층을 형성하는 공정을 포함하는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.A method of manufacturing a thin film transistor comprising: forming a gate insulating layer on a lower substrate provided with a gate electrode; forming an active layer on the gate insulating layer; and forming a source and a drain on both sides of the active layer. The thin film comprising the step of forming the active layer, the step of forming a microcrystalline silicon layer and the step of forming a hydrogenated amorphous silicon layer containing chlorine (Cl) on the fine crystalline silicon layer Method of manufacturing a transistor. 제4항에 있어서, 상기 염소를 포함한 비정질 실리콘층은 플라즈마 인가 화학 기상 증착(PECVD)법으로 증착되는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.The method of claim 4, wherein the amorphous silicon layer including chlorine is deposited by a plasma applied chemical vapor deposition (PECVD) method. 제5항에 있어서, 상기 염소를 포함한 비정질 실리콘층은 SiH2Cl2/SiH4, 가스, SiHCl3/SiH4가스 및, SiCl4/SiH4가스와 같은 염소(Cl)를 포함하는 가스중 선택되는 하나의 가스를 이용하여 형성되는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.The method of claim 5, wherein the amorphous silicon layer containing chlorine is selected from a gas containing chlorine (Cl), such as SiH 2 Cl 2 / SiH 4 , gas, SiHCl 3 / SiH 4 gas, and SiCl 4 / SiH 4 gas Method for manufacturing a thin film transistor, characterized in that formed using one gas.
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