KR100252757B1 - Method of forming metal pattern - Google Patents

Method of forming metal pattern Download PDF

Info

Publication number
KR100252757B1
KR100252757B1 KR1019930020194A KR930020194A KR100252757B1 KR 100252757 B1 KR100252757 B1 KR 100252757B1 KR 1019930020194 A KR1019930020194 A KR 1019930020194A KR 930020194 A KR930020194 A KR 930020194A KR 100252757 B1 KR100252757 B1 KR 100252757B1
Authority
KR
South Korea
Prior art keywords
metal
pattern
film
polyimide film
forming
Prior art date
Application number
KR1019930020194A
Other languages
Korean (ko)
Other versions
KR950009948A (en
Inventor
전종포
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019930020194A priority Critical patent/KR100252757B1/en
Publication of KR950009948A publication Critical patent/KR950009948A/en
Application granted granted Critical
Publication of KR100252757B1 publication Critical patent/KR100252757B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE: A method of forming a metal pattern is provided to increase the reliability of elements by preventing pollutants from forming during metal etching. CONSTITUTION: A connection hole(1) is formed by etching the area where a metal pattern is to be formed, and a first polyimide film(2) is applied on the entire surface. An insulating film(3) and a photosensitive film(4) are formed successively on the first polyimide film(2) to give a photosensitive film pattern. An insulating film pattern and a first polyimide film pattern are formed successively using the photosensitive film pattern. Metal is formed on top of the connection hole(1) and the insulating film pattern and then alloyed. A second polyimide film is applied on the entire surface and the second polyimide film is etched so that the metal formed on top of the insulating film pattern is exposed to form a remaining polyimide film. The exposed metal is removed and a third polyimide film is applied on the entire surface.

Description

금속패턴 형성방법Metal pattern formation method

제1(a)도 내지 제1(i)도는 본 발명의 일실시예에 따른 금속 배선 형성 공정 단면도.1 (a) to 1 (i) are cross-sectional views of a metal wiring forming process according to an embodiment of the present invention.

제2(a)도 내지 제2(f)도는 본 발명의 다른 실시예에 따른 금속 배선 형성 공정 단면도.2 (a) to 2 (f) are cross-sectional views of a metal wiring forming process according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 접속 홀 2, 6, 7 : 폴리이미드막1: Connection hole 2, 6, 7: Polyimide membrane

2′: 폴리이미드막 패턴 3 : 산화막2 ': polyimide film pattern 3: oxide film

3′: 산화막 패턴 4 : 감광막3 ': oxide film pattern 4: photosensitive film

4′: 감광막 패턴 5, 5′: A14 ': Photosensitive film pattern 5, 5': A1

2′: 폴리이미드막 패턴 6′: 잔류 폴리이미드막2 ': polyimide film pattern 6': residual polyimide film

본 발명은 금속패턴 형성방법에 관한 것으로, 특히 내열성 폴리이미드(polyimide)막을 사용하여 금속패턴 형성을 이루기 위한 폴리싱(polishing) 공정을 필요로 하지 않는 금속패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal pattern, and more particularly, to a method of forming a metal pattern that does not require a polishing process for forming a metal pattern using a heat resistant polyimide film.

종래의 반도체 소자의 제조공정중에서 금속패턴을 형성하기 위하여는 균일한 두께의 금속을 코팅하고 리소그라피(Lithography) 공정을 사용하여 불필요한 금속을 식각함으로써 금속패턴을 형성하게 된다.In order to form a metal pattern in a conventional semiconductor device manufacturing process, a metal pattern is formed by coating a metal having a uniform thickness and etching unnecessary metal by using a lithography process.

그러나 상기 종래의 금속패턴 형성은 빛이 금속층에서 반사되는 것을 막기 위하여 무반사층을 사용하여 금속을 식각함으로써 패턴을 형성하기 때문에 공정 자체에서의 오염물질의 발생뿐만 아니라 공정의 복잡성과 금속부식의 문제점이 따랐다.However, in the conventional metal pattern formation, the pattern is formed by etching the metal using an antireflective layer to prevent light from being reflected from the metal layer. Followed.

상기 문제점을 해결하기 위하여 안출된 본 발명은 금속패턴을 형성함에 있어 금속식각을 통해 패턴을 이루지 않고 다층 레지스트와 폴리이미드막의 내열성을 이용하여 공정의 안정성과 아우러 미세 패턴을 형성하여 차세대 고집적 소자의 금속패턴 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention does not form a pattern through metal etching in forming a metal pattern, and forms process microstructure and stability of the process using a heat resistance of a multilayer resist and a polyimide film to form a metal of a next-generation highly integrated device. The purpose is to provide a pattern forming method.

상기 목적을 달성하기 위하여 본 발명은, 금속패턴 형성방법에 있어서, 금속패턴이 형성될 부위를 식각하여 접속 홀을 만들고 전체 구조 상부에 제 1 폴리이미드막을 도포하는 단계와; 상기 제 1 폴리이미드막상에 절연막, 감광막을 차례로 형성하고 감광막 패턴을 형성하는 단계와; 상기 감광막 패턴을 이용하여 절연막 패턴및 제 1 폴리이미드막 패턴을 순차적으로 형성하는 단계와; 금속을 접속 홀과 절연막 패턴 상부 부위에 형성하고 얼로이(Alloy) 시키는 단계와; 전체구조 상부에 제 2 폴리이미드막을 도포하여 상기 절연막 패턴상에 형성되어 있는 상부의 금속이 노출되도록 제 2 폴리이미드막을 에치백 식각하여 잔류 폴리이미드막을 형성하는단계와; 노출된 금속을 제거하고, 제 3 폴리이미드막을 전면에 도포하여 금속패턴을 형성하는 단계를 포함하여 이루어 지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a metal pattern, comprising: forming a connection hole by etching a portion where a metal pattern is to be formed and applying a first polyimide film on the entire structure; Forming an insulating film and a photosensitive film on the first polyimide film in order and forming a photosensitive film pattern; Sequentially forming an insulating film pattern and a first polyimide film pattern using the photosensitive film pattern; Forming and alloying a metal in an upper portion of the connection hole and the insulating layer pattern; Applying a second polyimide film over the entire structure to etch back-etch the second polyimide film to expose the upper metal formed on the insulating film pattern to form a residual polyimide film; And removing the exposed metal and applying a third polyimide film to the entire surface to form a metal pattern.

이하, 첨부된 도면 제1(a)도 내지 제1(i)도와 제2(a)도 내지 제2(i)도를 참조하여 본 발명에 따른 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1 (a) to 1 (i) and 2 (a) to 2 (i).

먼저, 본 발명에 따른 일실시예를 제1(a)도 내지 제1(i)도를 통하여 상세히 설명한다.First, an embodiment according to the present invention will be described in detail with reference to FIGS. 1 (a) to 1 (i).

제1(a)도와 같이 금속패턴이 형성될 부위에 습식 및 건식식각을 하여 접속 홀(1)을 만들고 전체 구조 상부에 폴리이미드막(2), 산화막(3), 감광막(4)을 차례로 형성하고, 제1(b)도, 제1(c)도, 제1(d)도에 차례로 도시된 바와 같이 상기 감광막 패턴(4′)을 형성하여 산화막 패턴(3′) 및 폴리이미드막 패턴(2′)을 순차적으로 형성한다.As shown in FIG. 1 (a), the connection hole 1 is formed by wet and dry etching at the site where the metal pattern is to be formed, and the polyimide film 2, the oxide film 3, and the photosensitive film 4 are sequentially formed on the entire structure. As shown in Figs. 1 (b), 1 (c), and 1 (d), the photosensitive film pattern 4 'is formed to form an oxide film pattern 3' and a polyimide film pattern ( 2 ') are formed sequentially.

이어서, 제1(e)도와 같이 1%의 Si을 포함한 A1 또는 0.5%의 Cu를 포함한 A1(5, 5′)을 증착하여 얼로이(Alloy) 시키는데, 이때 상기 A1(5, 5′)의 증착은 접속 홀(1)과 산화막 패턴(3′)상부 부위에 형성되도록 한다.Subsequently, as shown in FIG. 1 (e), A1 containing 1% of Si or A1 (5, 5 ') containing 0.5% of Cu is deposited and alloyed, wherein A1 (5, 5') of Deposition is made to be formed in the upper portion of the connection hole 1 and the oxide film pattern 3 '.

그리고, 제1(f)도에 도시된 바와 같이 다시 폴리이미드막(6)을 도포하여 제1(g)도와 같이 산화막 패턴(3′)상에 형성되어 있는 A1(5)이 노출되도록 O2플라즈마(plasma)를 이용하여 에치백 식각하여 잔류 폴리이미드막(6′)을 형성한다.And, a 1 (f) O 2 that also the back coating are the 1 (g), A1 (5) which is formed on the oxide film pattern (3 ') As shown in Fig. Exposure to a polyimide film 6, as shown in The residual polyimide film 6 'is formed by etching back using plasma.

이어서, 제1(h)도와 같이 노출된 A1(5)을 제거하고, 또다시 폴리이미드막(7)을 전면에 도포하여 금속패턴을 완성한다.Subsequently, the exposed A1 (5) is removed as shown in FIG. 1 (h), and the polyimide film 7 is applied to the entire surface to complete the metal pattern.

또한, 본 발명의 다른 실시예를 제2(a)도 내지 제2(f)도를 참조하여 설명하면, 본 발명의 다른 실시예에서의 제2(a)도는 상기 일시예의 제1(a)도 내지 제1(d)도와는 동일한 공정을 수행한 상태를 나타내고 있으며, 제2(b)도에서 A1(5) 을 증착하기 전에 Ti 또는 TiN등으로 구성된 금속막(8)을 추가로 형성하여 금속합금 배선을 형성하는 것으로 그 이외의 공정은 상기 일실시예와 동일하게 실시한다.In addition, another embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (f), and FIG. 2 (a) in another embodiment of the present invention is the first (a) of the temporary example. 1 to (d) show a state in which the same process is performed, and before the deposition of A1 (5) in FIG. 2 (b), a metal film 8 made of Ti or TiN is additionally formed. A metal alloy wiring is formed, and the other processes are performed similarly to the said one Example.

상기와 같이 이루어 지는 본 발명은 불필요한 금속층이 증착된 부위 금속을 폴리싱 하지 않고, 일정부위에 형성된 금속막만을 접속홀에 증착된 금속과 분리된 상태에서 식각하여 금속식각에서 형성되는 오염물질을 방지함으로써 반도체 소자의 미세 금속배선을 안정된 공정으로 형성하여 이에따라 소자의 신뢰도를 증가 시킬수 있는 효과가 있다.The present invention made as described above does not polish the metal on which the unnecessary metal layer is deposited, and by etching only the metal film formed in a predetermined portion separated from the metal deposited in the connection hole to prevent the contaminants formed in the metal etching By forming a fine metal wiring of the semiconductor device in a stable process there is an effect that can increase the reliability of the device.

Claims (5)

금속패턴 형성방법에 있어서, 금속패턴이 형성될 부위를 식각하여 접속 홀(1)을 만들고 전체구조 상부에 제 1 폴리이미드막(2)을 도포하는 단계와; 상기 제 1 폴리이미드막(2)상에 절연막(3), 감광막(4)을 차례로 형성하고 감광막 패턴(4′)을 형성하는 단계와; 상기 감광막 패턴(4′)을 이용하여 절연막 패턴(3′) 및 제 1 폴리이미드막 패턴(2′)을 순차적으로 형성하는 단계와; 금속(5, 5′)을 접속 홀(1)과 절연막 패턴(3′) 상부 부위에 형성하고 얼로이(Alloy) 시키는 단계와; 전체구조 상부에 제 2 폴리이미드막(6)을 도포하여 상기 절연막 패턴(3′)상에 형성되어 있는 금속(5)이 노출되도록 제 2 폴리이미드막(6)을 에치백 식각하여 잔류 폴리이미드막(6′)을 형성하는 단계와; 노출된 금속(5)을 제거하고, 제 3 폴리이미드막(7)을 전면에 도포하여 금속패턴을 형성하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 금속패턴 형성방법.A method of forming a metal pattern, comprising: forming a connection hole (1) by etching a portion where a metal pattern is to be formed, and applying a first polyimide film (2) over the entire structure; Forming an insulating film (3) and a photoresist film (4) on the first polyimide film (2) in order and forming a photoresist film pattern (4 '); Sequentially forming an insulating film pattern 3 'and a first polyimide film pattern 2' using the photosensitive film pattern 4 '; Forming metal (5, 5 ') in the connection hole (1) and the upper portion of the insulating film pattern (3') and alloying them; Applying the second polyimide film 6 on the entire structure to etch back-etch the second polyimide film 6 so as to expose the metal 5 formed on the insulating film pattern 3 '. Forming a film 6 '; Removing the exposed metal (5) and applying a third polyimide film (7) to the entire surface to form a metal pattern. 제1항에 있어서, 상기 접속 홀(1)은 습식식각 및 건식식각을 통해 형성하여 경사진 접속홀을 형성하는 것을 특징으로 하는 금속패턴 형성방법.The method of claim 1, wherein the connection hole is formed through wet etching and dry etching to form a sloped connection hole. 제1항에 있어서, 상기 금속(5, 5′)은 1% Si을 포함한 A1 또는 0.5%의 Cu를 포함한 A1인 것을 특징을 하는 금속패턴 형성방법.The method of claim 1, wherein the metal (5, 5 ') is A1 containing 1% Si or A1 containing 0.5% Cu. 제1항에 있어서, 상기 금속(5, 5′)은 증착하기 전에 Ti 또는 TiN막(8)을 증착하여 금속합금막을 형성하는 단계를 더 포함하고 있는 것을 특징으로 하는 금속패턴 형성방법.2. The method of claim 1, wherein the metal (5, 5 ') further comprises depositing a Ti or TiN film (8) to form a metal alloy film prior to deposition. 제1항에 있어서, 상기 잔류 폴리이미드막(6′)의 형성은 상기 제 2 폴리이미드막(6)의 상부를 O2플라즈마(plasma)를 이용하여 에치백 식각하여 형성하는 것을 특징으로 하는 금속패턴 형성방법.2. The metal according to claim 1, wherein the residual polyimide film 6 'is formed by etching back the upper portion of the second polyimide film 6 using an O 2 plasma. Pattern formation method.
KR1019930020194A 1993-09-28 1993-09-28 Method of forming metal pattern KR100252757B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930020194A KR100252757B1 (en) 1993-09-28 1993-09-28 Method of forming metal pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930020194A KR100252757B1 (en) 1993-09-28 1993-09-28 Method of forming metal pattern

Publications (2)

Publication Number Publication Date
KR950009948A KR950009948A (en) 1995-04-26
KR100252757B1 true KR100252757B1 (en) 2000-06-01

Family

ID=19364980

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930020194A KR100252757B1 (en) 1993-09-28 1993-09-28 Method of forming metal pattern

Country Status (1)

Country Link
KR (1) KR100252757B1 (en)

Also Published As

Publication number Publication date
KR950009948A (en) 1995-04-26

Similar Documents

Publication Publication Date Title
US4004044A (en) Method for forming patterned films utilizing a transparent lift-off mask
US4202914A (en) Method of depositing thin films of small dimensions utilizing silicon nitride lift-off mask
EP0145272A2 (en) Metal/semiconductor deposition
US5776836A (en) Self aligned method to define features smaller than the resolution limit of a photolithography system
KR100252757B1 (en) Method of forming metal pattern
JPH07307333A (en) Pattern forming method
JPH01266746A (en) Semiconductor device
GB2291977A (en) Forming patterns of semiconductor devices
KR100781445B1 (en) Method for manufacturing metal layer in semiconductor device
KR0138008B1 (en) Fabrication method of metal contact in semiconductor device
KR950003224B1 (en) Fabricationg method of semiconductor device having multi-layer structure
KR920002026B1 (en) Metal layer connecting method using multi-layer photolithographic technics
KR100291412B1 (en) Method for applying photoresist
KR0144140B1 (en) Metal wiring method
JPS60196958A (en) Manufacture of semiconductor integrated circuit
KR100372657B1 (en) Method for forming contact of semiconductor device
JPS6334928A (en) Formation of through hole
KR100206896B1 (en) Method for forming contact of bypola device
JP2699498B2 (en) Method for manufacturing semiconductor device
JPH039520A (en) Manufacture of semiconductor device
JPS61180456A (en) Manufacture of semiconductor device
JPH023926A (en) Forming method of wiring
JPS6148942A (en) Method of forming electrode of semiconductor device
KR970072100A (en) A method of forming a multilayer metal wiring layer on a silicon substrate
KR20000066123A (en) Manufacturing method for contact hole in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080102

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee