JPH023926A - Forming method of wiring - Google Patents
Forming method of wiringInfo
- Publication number
- JPH023926A JPH023926A JP15442488A JP15442488A JPH023926A JP H023926 A JPH023926 A JP H023926A JP 15442488 A JP15442488 A JP 15442488A JP 15442488 A JP15442488 A JP 15442488A JP H023926 A JPH023926 A JP H023926A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gold
- mask
- wiring
- eliminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 70
- 239000010931 gold Substances 0.000 claims abstract description 70
- 229910052737 gold Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 238000007747 plating Methods 0.000 claims abstract description 29
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000000992 sputter etching Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は配線の形成方法に関し、特に半導体装置の金め
つき配線を含む配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming wiring, and particularly to a method for forming wiring including gold-plated wiring for semiconductor devices.
従来の金めつき配線を含む配線の形成方法を第３図を用
いて説明する。A conventional method for forming wiring including gold-plated wiring will be explained with reference to FIG.
まず第３図（ａ）に示すように、半導体基板１の上にＳ
ｉＣ２等からなる絶縁Ｍ２を形成した後、スパッタ蒸着
法によりＴｉ等からなる下層の金属膜３Ａ及び金膜４を
形成する。First, as shown in FIG. 3(a), an S
After forming the insulation M2 made of iC2 or the like, a lower metal film 3A made of Ti or the like and a gold film 4 are formed by sputter deposition.
次に第３図（ｂ）に示すように、フォトレジスト５を形
成したのち開口部１０を設け、この開口部１０に電解め
っき法により金めつき層７を形成する。Next, as shown in FIG. 3(b), after forming a photoresist 5, an opening 10 is provided, and a gold plating layer 7 is formed in this opening 10 by electrolytic plating.
次に第３図（Ｃ）に示すように金めつき層７を完全に覆
うようなフォトレジストからなるマスク８を形成する。Next, as shown in FIG. 3(C), a mask 8 made of photoresist is formed so as to completely cover the gold plating layer 7.
次に第１−図（ｄ）に示すように、マスク８を用いスパ
ッタ蒸着した金Ｍ４及び下層の金属膜３Ａを除去するこ
とにより下層の金属膜３Ａと金膜４とからなる第１の配
線及び、下層の金属膜３Ａ、金膜４及び金めつき層７と
からなる第２の配線を形成していた。Next, as shown in FIG. 1(d), by removing the sputter-deposited gold M4 and the lower metal film 3A using a mask 8, a first wiring consisting of the lower metal film 3A and the gold film 4 is formed. In addition, a second wiring including the lower metal film 3A, the gold film 4, and the gold plating layer 7 was formed.
上述した従来の配線の形成方法は、金めつき層７を形成
した後、金めつき層７を完全に覆うフォトレジストから
なるマスク８で電解金めっき時の給電用金属であるスパ
ッタ蒸着しな金膜４及び下層の金属膜３Ａを除去するよ
うになっているので、金めつき層７が２〜３μｍと厚い
場合、金めつき層７を完全に覆うマスク８の膜厚も厚く
しなければならないため、微細な配線形成が困難である
という欠点がある。The conventional wiring formation method described above involves forming the gold plating layer 7 and then using a mask 8 made of photoresist that completely covers the gold plating layer 7 to perform sputter deposition, which is a power supply metal during electrolytic gold plating. Since the gold film 4 and the underlying metal film 3A are removed, if the gold plating layer 7 is as thick as 2 to 3 μm, the thickness of the mask 8 that completely covers the gold plating layer 7 must also be increased. Therefore, it has the disadvantage that it is difficult to form fine wiring.
本発明の１配線の形成方法は、絶縁膜上に給電用金属膜
及び金膜を順次形成する工程と、前記金膜を選択的に除
去する工程と、電解めっき法により前記金膜の一部上に
金めつき層を形成する工程と、前記金めっき層及び金膜
をマスクとして前記給電用金属膜を除去する工程とを含
んで構成される。The method for forming one wiring of the present invention includes a step of sequentially forming a power supply metal film and a gold film on an insulating film, a step of selectively removing the gold film, and a part of the gold film by electrolytic plating. The method includes a step of forming a gold plating layer thereon, and a step of removing the power supply metal film using the gold plating layer and the gold film as a mask.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｂ）は本発明第１の実施例を説明する
ための工程順に示した半導体チップの断面図である。FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
まず第１図（ａ＞に示すように、半導体基板１上に５１
０２Ｍ等からなる厚さ１μｍの絶縁膜２を形成したのち
、スパッタ蒸着法によりＴｉからなる厚さ０．１μｍの
給電用金属膜３と厚さ０．５）ｘｍの金膜４を形成する
。次でフォトレジスト膜を形成したのちバターニングし
配線パターンを転写したマスク５を形成する。First, as shown in FIG. 1 (a), 51
After forming an insulating film 2 made of 0.2M or the like with a thickness of 1 μm, a power supply metal film 3 made of Ti with a thickness of 0.1 μm and a gold film 4 with a thickness of 0.5)xm are formed by sputter deposition. Next, a photoresist film is formed and then patterned to form a mask 5 on which a wiring pattern is transferred.
次に第１図（ｂ）に示すように、マスク５を用い、金膜
４をイオンミリング法により選択的に除去したのち、マ
スク５を除く。Next, as shown in FIG. 1(b), the gold film 4 is selectively removed by ion milling using a mask 5, and then the mask 5 is removed.
次に第１図（Ｃ）に示すように、金膜４の一部上に開口
したフォトレジストからなるマスク６を形成したのち、
給電用金属膜３を電解金めっきの給電金属として金めつ
き層７を形成する。Next, as shown in FIG. 1(C), after forming a mask 6 made of photoresist with an opening on a part of the gold film 4,
A gold plating layer 7 is formed using the power feeding metal film 3 as a power feeding metal for electrolytic gold plating.
次に第１図（ｄ）に示すように、マスク６を除去したの
ち金めっき層７及び金膜４をマスクに給電用金属膜３を
反応性イオンエツチング法により除去し、給電用金属Ｊ
ＩＭ３と金膜４からなる第１．の配線及び給電用金属膜
３、金属４及び金めつき層７からなる低抵抗の第２の配
線を形成する。Next, as shown in FIG. 1(d), after removing the mask 6, the power supply metal film 3 is removed by reactive ion etching using the gold plating layer 7 and the gold film 4 as a mask, and the power supply metal J
The first layer consists of IM3 and gold film 4. A low-resistance second wiring consisting of the power supply metal film 3, metal 4, and gold plating layer 7 is formed.
このように第１の実施例によれば、配線の幅は第１図（
ｂ）に示した金Ｍ４の幅と同一に形成できるなめ、微細
な配線を形成することができる。In this way, according to the first embodiment, the width of the wiring is as shown in FIG.
Since it can be formed to have the same width as the gold M4 shown in b), fine wiring can be formed.
第２図（ａ）〜（ｄ）は本発明の第２の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.
まず第２図（ａ）に示すように、半導体基板１上に絶縁
膜２、給電用金属膜３及びスパッタ蒸着法による金膜４
を形成した後、フォトレジストからなるマスク５を形成
し電解めっき法により金めつき層７を金膜４以上の膜厚
に形成する。First, as shown in FIG. 2(a), an insulating film 2, a power supply metal film 3, and a gold film 4 formed by sputter deposition are deposited on a semiconductor substrate 1.
After forming, a mask 5 made of photoresist is formed, and a gold plating layer 7 is formed to a thickness equal to or greater than the gold film 4 by electrolytic plating.
次に第２図（ｂ）に示すように、マスク５を除去したの
ち、金めつき層７をマスクとしてイオンミリング法によ
り金膜４を除去する。Next, as shown in FIG. 2(b), after removing the mask 5, the gold film 4 is removed by ion milling using the gold plating layer 7 as a mask.
次に第２図（ｃ）に示すように、フォトレジストで金め
つき層７の一部上に開口したマスク８を形成したのち電
解めっき法により、第２の金めつき層９を形成する。Next, as shown in FIG. 2(c), a mask 8 with an opening is formed on a part of the gold plating layer 7 using photoresist, and then a second gold plating layer 9 is formed by electrolytic plating. .
次に第２図（ｄ）に示すように金めつき層７と金膜４と
をマスクとして、反応性イオンエツチング法により給電
用金属膜３を除去し、給電用金属膜３、金膜４、金めつ
き層７からなる第１の配線と、この上面に第２の金めつ
き層９を有する第２の配線を形成する。Next, as shown in FIG. 2(d), using the gold plating layer 7 and the gold film 4 as masks, the power supply metal film 3 is removed by reactive ion etching, and the power supply metal film 3 and the gold film 4 are etched. , a first wiring consisting of a gold plating layer 7 and a second wiring having a second gold plating layer 9 on the upper surface thereof are formed.
この第２の実施例では、金めつき層７をスパッタ蒸着の
金Ｍ４より厚く形成するようになっているので、配線形
成後の金膜の厚さを第１の実施例よりも厚くすることが
できるので配線抵抗をより低減できる利点がある。In this second embodiment, the gold plating layer 7 is formed to be thicker than the sputter-deposited gold M4, so the thickness of the gold film after wiring formation can be made thicker than in the first embodiment. This has the advantage of further reducing wiring resistance.
尚、上記実施例においては給電用金属膜としてＴｉを用
いた場合について説明したが、これに限定されるもので
はな（、’Ｉ” ｉ ＮやＰＬ等を用いることができる
。In the above embodiments, the case where Ti is used as the power feeding metal film is described, but the present invention is not limited to this ('I'' i N, PL, etc. can be used).
以上説明したように本発明は、絶縁膜上に給電用金属膜
及び金膜を形成した後、金膜の一部を除去し、電解めっ
き法により金膜の一部上に、金めつき屑を形成した後、
金めつき層及び金膜をマスクとして、給電用金属膜を除
去することにより、微細な配線を形成できるという効果
がある。従って半導体装置をより小型化できる。As explained above, in the present invention, after forming a power supply metal film and a gold film on an insulating film, a part of the gold film is removed, and gold plating scraps are deposited on a part of the gold film by electrolytic plating. After forming the
By removing the power supply metal film using the gold plating layer and the gold film as a mask, there is an effect that fine wiring can be formed. Therefore, the semiconductor device can be further miniaturized.
第１図（ａ） 〜＜ｄ）及び第２図（ａ） 〜（ｄ）は
本発明の第１及び第２実施例を説明するための工程順に
示した半導体チップの断面図、第３図（ａ）〜（ｄ）は
従来の配線の形成方法を説明するための工程順に示した
半導体チップの断面図である。
１・・・半導体基板、２・・・絶縁体、３・・・給電用
金属膜、３Ａ・・・下層の金属膜、４・・・金膜、５．
６．８・・・マスク、７・・・金めつき層、９・・・第
２の金めつき層。
力
？
図FIGS. 1(a) to <d) and FIGS. 2(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention, and FIG. (a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional wiring forming method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulator, 3... Metal film for power supply, 3A... Lower layer metal film, 4... Gold film, 5.
6.8...Mask, 7...Gold plating layer, 9...Second gold plating layer. Power? figure
Claims (1)
、前記金膜を選択的に除去する工程と、電解めっき法に
より前記金膜の一部上に金めっき層を形成する工程と、
前記金めっき層及び金膜をマスクとして前記給電用金属
膜を除去する工程とを含むことを特徴とする配線の形成
方法。A step of sequentially forming a power supply metal film and a gold film on an insulating film, a step of selectively removing the gold film, and a step of forming a gold plating layer on a part of the gold film by electrolytic plating. ,
A method for forming wiring, comprising the step of removing the power supply metal film using the gold plating layer and the gold film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15442488A JPH023926A (en) | 1988-06-21 | 1988-06-21 | Forming method of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15442488A JPH023926A (en) | 1988-06-21 | 1988-06-21 | Forming method of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023926A true JPH023926A (en) | 1990-01-09 |
Family
ID=15583867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15442488A Pending JPH023926A (en) | 1988-06-21 | 1988-06-21 | Forming method of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023926A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6599834B2 (en) * | 2001-05-28 | 2003-07-29 | Sharp Kabushiki Kaisha | Process of manufacturing a semiconductor device with an electroplated wiring layer |
| JP2006346109A (en) * | 2005-06-15 | 2006-12-28 | Toyota Motor Corp | Biological information detection sensor and biological state detector |
-
1988
- 1988-06-21 JP JP15442488A patent/JPH023926A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6599834B2 (en) * | 2001-05-28 | 2003-07-29 | Sharp Kabushiki Kaisha | Process of manufacturing a semiconductor device with an electroplated wiring layer |
| JP2006346109A (en) * | 2005-06-15 | 2006-12-28 | Toyota Motor Corp | Biological information detection sensor and biological state detector |
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