KR100244236B1 - Apparatus for detecting vsb mode of digital tv - Google Patents

Abstract

The present invention relates to a VSB mode detection apparatus in a US-oriented digital TV receiver using a residual sideband (VSB) method, and particularly, the last 8 symbols of a VSB mode signal interval (= 24 symbols) of a field sync signal inserted at every 313 data segment positions. By extracting only the most significant bit having code information from a certain bit of digital data while detecting the VSB mode inserted at the transmitting side, the hardware is simplified, which makes integration easier and IC size smaller, resulting in lower cost. do. In addition, if the extracted code bits are serially outputted, they are sequentially converted to 8-bit parallel data by sequentially delaying them for a predetermined clock and the combination of the parallel data is determined to determine whether there is an error in the input data. When an error is detected, the operation of all circuits used for VSB mode detection is stopped and the VSB mode signal section of the next vertical synchronization signal is waited. When an error occurs in the input data, the VSB mode detection is stopped. Can be detected.

Description

VBS mode detection device of digital television

The present invention relates to a VSB mode detection apparatus in a digital TV receiver for a US using a residual side band (VSB) method.

In 1994, the Grand Alliance (GA), an organization that unified digital television, such as high-definition television (HDTV), decided 8VSB for terrestrial broadcast and 2,4,8,16VSB for CATV as the modulation subsystem. . The FCC Advisory Committee on Advanced Television Service (ACATS) has since decided to adopt 8VSB for terrestrial broadcasting.

In other words, if two symbols (1 bit) are assigned as one symbol, the transmission speed is 10.76 Mbit / s, which is 2VSB, and 4 symbols (2 bits) are 21.5 Mbit / s, and 8 symbols (3 bits) are 32.3 Mbit / s. If s and 16 symbols (4 bits) are 43 Mbit / s, each is called 4VSB, 8VSB, 16VSB. At this time, which VSB method is used for CATV from 2VSB to 16VSB is determined by noise, interference, transmission rate, etc. CATV operator selects each VSB modulation method of 2 to 16 for each CATV station.

In the case of terrestrial broadcasting 8VSB, for example, a transmitter such as a broadcasting station passes a mapper that changes the power level to a desired power level before transmitting a signal. The output level of the mapper is 8 symbol values (amplitude levels) , -168, -120, -72, -24, 24, 72, 120, 168. In addition, the mapper forcibly generates and inserts four symbol data segment sync signals for every 832 symbols by appointment, and creates and inserts a field sync signal at the position of 313 data segments. 0 and 1, and the mapper output level is '120' when the synchronization is '1' and '-120' when the synchronization is '0'. Here, the data segment sync signal corresponds to a horizontal sync signal in the NTSC signal, and the field sync signal corresponds to a vertical sync signal and is not a signal of the same type.

On the receiving side, such as a digital TV, when the RF signal modulated in the 8 VSB method is received through the antenna as shown in FIG. 1, the tuner 11 selects a frequency of a desired channel by tuning and converts it into an IF signal. The FPLL unit 12 demodulates the IF signal output from the tuner 11 into baseband I and Q signals to lock frequency and phase. That is, the FPLL unit 12 is a circuit in which a frequency tracking loop and a PLL are integrated, and locks a frequency first and then locks a phase when the frequency is locked. The analog / digital (A / D) converter 13 converts the I signal of the FPLL unit 12 into digital data of a predetermined bit (for example, 10 bits). Here, the Q signal is used for carrier recovery in the FPLL section 12. The synchronization recovery unit 14 restores the data segment synchronization signal, the field synchronization signal, etc., which were inserted at the time of transmission using the digitally converted 10-bit data for use in timing recovery, equalization, and the like. These synchronization signals are designed to facilitate the recovery of the received data. When they are detected incorrectly, the recovery of the data is not performed properly, which greatly affects the whole system. The equalization and error correction unit 15 uses the data segment restored in the synchronization recovery unit 14, field synchronization signals as a training signal, linear distortion of amplitude causing interference between symbols, and ghosts generated by reflections from buildings or mountains. After the equalization is performed to correct the error, the error generated through the transmission channel is corrected. The video decoder 16 decodes the equalized and error corrected signal by an MPEG algorithm to make the signal visible to the viewer.

Such digital TV receivers will also need to operate for CATV in the future along with terrestrial broadcast receivers. That is, they must be compatible. To do this, it is necessary to accurately detect the VSB mode of the currently received data.

An object of the present invention is to provide a VSB mode detection apparatus of a digital TV that detects a VSB mode using only the sign bits of the input digital data.

Another object of the present invention is to provide a VSB mode detection apparatus of a digital TV that detects a VSB mode by using sign bits of the last 8 symbols of a VSB mode signal interval included in a field synchronization signal among input digital data.

It is still another object of the present invention to determine the presence or absence of an error in a VSB mode signal included in a field synchronization signal of a received signal. When an error is detected, the operation of all circuits used for VSB mode detection is stopped and the next field synchronization signal is detected. An apparatus for detecting a VSB mode of a digital TV waiting for a VSB mode signal interval is provided.

The apparatus for detecting VSB mode of a digital TV according to the present invention for achieving the above object is a code bit extraction unit for extracting only the most significant bit having code information when analog data output from the tuner is converted into a predetermined bit of digital input. And a serial / parallel conversion unit for converting data of code bits input in series from the code bit extraction unit in parallel by sequentially delaying a predetermined clock, and data output in parallel from the serial / parallel conversion unit. An error detection unit for determining whether there is an error of data input by combining, and data having actual VSB mode information among parallel data output from the serial / parallel conversion unit only when an enable signal is inputted, and storing the VSB mode signal. And a storage unit for outputting the data to the storage unit if it is determined that there is no error. And a comparison counter for comparing data with data stored in the storage unit, and a confidence counter that increases or decreases reliability according to a comparison result of the comparison unit and outputs an enable signal to the storage unit only when the reliability is lower than a specific threshold. It is characterized by.

The code bit extractor operates only during the last 8 symbols of the 24 symbol VSB mode signal periods included in the field sync signal.

Data output in parallel from the serial / parallel converter is the sign bit of the last 8 symbols of the VSB mode signal section of the field sync signal, and the upper 4 bits are 1-bit parity for controlling the number of '1's to be even. It consists of three bits of data with actual VSB mode information, and the lower four bits are characterized by an inverted form of the upper four bits.

The error detector includes first to fourth comparators for comparing the inverted data among the outputs of the serial / parallel converter and the high-order 4 bit data among the outputs of the serial / parallel converter. A fifth comparator for comparing whether the number of '1's is an even number, a sixth comparator for comparing whether the number of' 1's of the lower 4 bit data among the outputs of the serial / parallel converter is even, and the first comparator; And an error discriminating unit configured to OR the outputs of the sixth comparator to determine the presence or absence of an error.

Each of the first to fourth comparators is configured with an exclusive Noah gate, and the fifth and sixth comparators are configured with an exclusive ora gate, respectively.

When the error detection unit detects an error, the confidence counter controls all circuit blocks to stop the operation and wait for the VSB mode signal section of the next field sync signal by maintaining the previous value regardless of input.

1 is a block diagram of a general digital TV receiver

2 illustrates VSB mode related information included in a field sync signal;

3 is a block diagram of an apparatus for detecting a VSB mode of a digital TV according to the present invention;

4 is a detailed block diagram of the serial / parallel converter and the error detector of FIG.

Explanation of symbols for the main parts of the drawings

31: code bit extraction unit 32: serial / parallel conversion unit

33: error detection unit 34: flip-flop

35: Comparator 36: Confidence Counter

37: delay

Hereinafter, the embodiment of the present invention will be further described with reference to the features of the present invention.

)이다.In general, the information on the VSB mode is inserted into the field synchronization signal section and transmitted by the transmitting side. That is, a VSB mode region composed of 24 symbols (= bits) is allocated to the field sync signal section inserted with one data segment length for every 313 data segment positions. As shown in FIG. 2, the 24 symbols are divided into three regions of 8 symbols each. The preceding 16 symbols, that is, 2 bytes, are not used in the present invention, and only the last 1 byte, that is, 8 symbols, is used. At this time, the last 1 byte is divided into 4 bits again. The previous 4 bits are composed of 1 bit parity (P) and 3 bits of data (A, B, C) having information on the actual VSB mode. The last four bits are the inverted four bits (P, A, B, C) (

)to be.

At this time, the parity P is such that the number of '1's is even, and the A, B, and C values of each VSB mode are determined as shown in Table 1 below by appointment.

P A B C Other Cable broadcasting 0 0 0 0 2 VSB One 0 0 One 4 VSB One 0 One 0 8 VSB 0 0 One One 16 VSB For terrestrial broadcasting 0 One 0 One 8 VSB

In this way, the field synchronization signal section inserts the data we know at the transmitting side, and the VSB mode signal is also promised in advance. In addition, it can be seen that, as described above, only two levels (that is, +120 and -120) exist in the value of the field sync signal in which the VSB mode information is inserted.

Accordingly, the present invention detects the VSB mode inserted in the field synchronization signal section at the transmitting side using only the code bits of the received received data so that the digital TV can receive not only terrestrial broadcasting but also cable broadcasting while simplifying hardware. do.

An apparatus for detecting a VSB mode of a digital TV according to the present invention for realizing this is shown in FIG. 3.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an apparatus for detecting a VSB mode of a digital TV according to the present invention, in which only the most significant bit having sign information is extracted from a predetermined bit (for example, 10 bits) of digital data to be output in series; A serial / parallel converter which delays the code bits output from the code bit extractor 31 and the code bit extractor 31 for a predetermined clock (that is, 8 clocks) and simultaneously outputs an enable signal. 32), an error detector 33 for detecting the presence or absence of an error generated in the input data from the parallel data of the serial / parallel converter 32, and the serial / parallel converter 32 only when an enable signal is input. The flip-flop 34, which stores the data (A, B, C) having the actual VSB mode information among the parallel data output from the), the data input to the flip-flop 34 and the data stored in the flip-flop 34 Rain like The comparator 35 and a reliability increase or decrease according to a comparison result of the comparator 35, and output an enable signal to the flip-flop 34 only when the reliability is lower than a specific threshold and the error detector If an error is detected at (33), it is composed of a reliability counter 36 which stops the operation of all the above-described blocks and controls to wait for the VSB mode signal section of the next field sync signal. In this case, the output of the flip-flop 34 is a VSB mode signal detected, and the serial / parallel converter 32 and the confidence counter 36 make a difference between the clocks made by the flip-flop delay 37. Is enabled with.

As illustrated in FIG. 4, the serial / parallel converter 32 delays seven delays 41 sequentially during seven clocks when a sign bit of the last eight symbols is serially input in a VSB mode signal section of a field synchronization signal. 47, each output of the seven delayers 41 to 47 is stored, and eight data are simultaneously outputted by the enable signal generated at the time when the last bit, that is, the sign bit of the eighth symbol, is inputted. It is composed of a flip-flop 48.

The error detection unit 33 includes four exclusive NOR gates 51 to 54 and the flip-flop 48 that compare data among the outputs of the flip-flop 48 to each other to maintain an inversion relationship. An exclusive OR gate 55 that compares whether the number of '1' of the upper 4 bits of the output of the output is even and the number of '1' of the lower 4 bits of the output of the flip-flop 48 remains even. Ora gate 57 for detecting an error by logically combining the exclusive ora gate 56 for comparing whether or not, and the outputs of the two or more ora gates 55 and 56, respectively. It consists of.

)만을 이용한다. 이때, 각 심볼은 A/D 변환부(13)를 거치면서 10비트의 데이터 값을 갖고 있다. 즉, 노이즈를 고려하지 않은 이상적인 경우라면 필드 동기 신호 구간의 모든 데이터는 +120 또는 -120이다.The present invention configured as described above operates only in the VSB mode signal section of the field sync signal. That is, in the VSB mode detecting apparatus according to the present invention, when the field synchronizing signal is detected by the synchronizing recovery unit 14, the data of the last 8 symbols of the 24 symbol VSB mode related information included in the field synchronizing signal (

Use only). At this time, each symbol has a 10-bit data value through the A / D conversion unit 13. That is, in an ideal case in which noise is not considered, all data of the field sync signal interval is +120 or -120.

)이 입력되는 시점에서 인에이블되면 8개의 데이터가 동시에 플립플롭(48)으로부터 출력된다. 여기서, 병렬로 출력되는 8 비트의 데이터는

의 배열를 갖는다. 즉, 상기 직/병렬 변환부(32)는 직렬로 입력되는 데이터를 8 클럭 동안 모은 후 동시에 8 비트의 데이터(

)를 출력한다.Therefore, the sign bit extracting unit 31 extracts only the most significant bit having the sign information from the 10-bit digital data input, and if the number is positive, 1 is positive and the number 0 is negative, the delay unit 41 of the serial / parallel converter 32 is used. ) The delay unit 41 of the serial / parallel converter 32 stores one bit of data input from the code bit extractor 31 and outputs the data to the delay unit 42 connected in series at the next clock. If this process is repeated for seven clocks, data is sequentially stored in the seven delays 41 to 47. At this time, the data of each of the delays 41 to 46 is outputted to the flip-flop 48 in synchronization with the clock and to the next delay, and the data of the seventh delay 47 is only to the flip-flop 48. Since the flip-flop 48 is outputted, the last symbol of the 8 symbols (

When is enabled at the time of input, 8 data are output from the flip-flop 48 at the same time. Here, 8 bits of data output in parallel

Has an array of That is, the serial / parallel converter 32 collects data inputted in series for 8 clocks and simultaneously displays 8 bits of data (

)

)에 에러가 발생하지 않았다면 P 와

, A 와

, B 와

, C 와

는 서로 반전 관계에 있고, 상위 4비트 데이터( P , A , B , C )의 '1' 개수는 패리티(P)에 의해 짝수를 유지하고, 하위 4비트 데이터(

,

,

,

)의 '1'의 개수도 패리티(

)에 의해 짝수를 유지한다.The error detection unit 33 detects whether an error has occurred in the output data of the serial / parallel conversion unit 32. If the 8-bit data output in parallel from the serial / parallel conversion unit 32 (

If no error occurred at P Wow

, A Wow

, B Wow

, C Wow

Are inverted relative to each other and the upper 4 bits of data ( P , A , B , C '1' number is kept even by parity (P), and lower 4 bit data (

,

,

,

Number of "1" is also parity (

Keep the even number

데이터를, 배타적 노아 게이트(52)는 A 데이터와

데이터를, 배타적 노아 게이트(53)는 B 데이터와

데이터를, 배타적 노아 게이트(54)는 C 데이터와

데이터를 비교하여 두 데이터가 서로 반전 관계에 있으면 '0'을, 아니면 '1'을 출력한다. 그러므로, 상기 4개의 배타적 노아 게이트(51∼54)의 출력중 어느 하나라도 1이 되면 에러가 발생하였음을 의미한다.Thus, the exclusive Noah gate 51 P Data and

Data, the exclusive Noah gate 52 A Data and

Data, exclusive Noah gate 53 B Data and

Data, the exclusive Noah gate 54 C Data and

Compares the data and outputs '0' if the two data are inverted with each other and '1'. Therefore, if any one of the outputs of the four exclusive NOR gates 51 to 54 becomes 1, it means that an error has occurred.

,

,

,

)는 배타적 오아 게이트(56)에서 '1'의 개수가 짝수인지를 비교한다. 이때, 상위 4비트 데이터( P , A , B , C )의 '1'의 개수가 짝수이면 배타적 오아 게이트(55)의 출력이 '0'이 되고, 하위 4비트 데이터(

,

,

,

)의 '1'의 개수가 짝수이면 배타적 오아 게이트(56)의 출력이 '0'이 된다. 상기 배타적 노아 게이트(51∼54)의 출력과 배타적 오아 게이트(55,56)의 출력은 오아 게이트(57)에 의해 논리합된다. 따라서, 상기 오아 게이트(57)의 출력이 '0'이면 필드 동기 신호의 VSB 모드 신호 구간의 마지막 8 심볼의 데이터에 에러가 발생하지 않았음을 의미하고, '1'이면 에러가 발생하였음을 의미한다.In addition, the higher 4 bit data ( P , A , B , C ) At the exclusive or gate 55, the lower 4 bit data (

,

,

,

) Compares whether the number of '1's in the exclusive ora gate 56 is even. At this time, the upper 4-bit data ( P , A , B , C If the number of '1' is an even number, the output of the exclusive OR gate 55 becomes '0', and the lower 4 bit data (

,

,

,

If the number of '1' is an even number, the output of the exclusive OR gate 56 becomes '0'. The output of the exclusive NOR gates 51 to 54 and the output of the exclusive OR gates 55 and 56 are ORed by the OR gate 57. Accordingly, if the output of the OR gate 57 is '0', it means that no error has occurred in the data of the last 8 symbols of the VSB mode signal section of the field sync signal, and '1' means that an error has occurred. do.

The output of the error detector 33 is output to the confidence counter 36, and the confidence counter 36 recognizes that an error has occurred when the output of the error detector 33 is '1', and thus all circuit blocks 31 to 31. 37) This operation stops and waits for the VSB mode signal section of the next field sync signal. That is, the confidence counter 36 does not perform any operation when the output of the error detector 33 is '1'. For example, if the count value is 10, all of the circuits are maintained as they are. Blocks 31 to 37 stop operation and wait for the VSB mode signal period of the next field sync signal.

On the other hand, if the error is not detected by the error detector 33, only 3 bits (A, B, C) having actual VSB mode information among the 1-byte outputs of the serial / parallel converter 32 are flip-flop 34 Is entered. The flip-flop 34 stores 3-bit data which is input only when the enable signal is input, but does not store any data other than the input.

An enable signal input to the flip-flop 34 is generated by the confidence counter 36. That is, the confidence counter 36 outputs a disable signal to the flip-flop 34 when the reliability, that is, the count value is greater than or equal to a certain threshold value, and outputs the enable signal to the flip-flop 34 when the confidence value is less than the specific threshold value. Is designed to output. Here, the specific threshold value depends on the designer, and it is assumed in the present invention to be '1'.

In addition, the confidence counter 36 increases or decreases the reliability by the output of the comparator 35. The comparator 35 is provided to the flip-flop 34 and the 3-bit data inputted to the flip-flop 34. The stored three bits of data are compared and the result is output to the confidence counter 36.

According to an embodiment of the present invention, when the system is reset by the reset signal, the flip-flop 34 is designed such that a terrestrial broadcasting VSB mode signal 101 is set to an initial value, that is, a default value. In this case, assuming that the VSB mode signal inserted by the transmitting side is '101', which is a terrestrial broadcast, the comparator 35 outputs '1' since both input data are the same as '101'.

When '1' is output from the comparator 35, the confidence counter 36 increases the reliability by one step. Therefore, the reliability of the confidence counter 36, that is, the count value changes from 0 to 1. In this case, since the input and output of the confidence counter 36 differ by one clock, when the count value of the confidence counter 36 changes to 1, the output counter 0 is the previous value 0, so that the confidence counter 36 is the flip-flop ( Output the enable signal. Accordingly, the flip-flop 34 stores 3-bit data '101' which is initially input.

In this case, since the VSB mode signal is not changed before power on / off or channel switching, data input to the flip-flop 34 for each VSB mode signal section of a subsequent field sync signal becomes '101', and the comparator ( The output of 35) continues to be '1'. The confidence counter 36 increases the reliability by one step each time it is enabled through the delayer 37 when '1' is output from the comparator 35. The confidence counter 36 is enabled one clock later than the flip-flop 48 of the serial / parallel converter 32 by the delay 37 of the flip-flop. In this case, since the reliability of the confidence counter 36 is a specific threshold value, that is, 1 or more, a disable signal is output to the flip-flop 34, and the flip-flop 34 no longer stores the input data. This is because '101' should always be input to the flip-flop 34. In order to prevent this value from being output as a VSB mode signal by disabling the flip-flop 34 when another value is instantaneously entered due to an error or the like. .

Meanwhile, as another example of the present invention, the initial value of the flip-flop 34 is set to '101', which is 8 VSB of terrestrial broadcasting, and the VSB mode signal inserted by the transmitting side is '011', which is 16 VSB of cable broadcasting. If it is assumed, among the 8 bits output from the serial / parallel converter 32, the 3-bit data A, B, and C having the actual VSB mode information are '011'. In this case, if an error is not detected by the error detector 33, the comparator 35 may input 3-bit data input to the flip-flop 34, that is, a value output from '011' and the flip-flop 34, that is, an initial value. Compare '101' set to. Therefore, the output of the comparator 35 becomes '0', and the confidence counter 36 decreases the reliability by one step.

At this time, since the reliability of the confidence counter 36 is '0' and can not be further reduced, the confidence counter 36 outputs an enable signal to the flip-flop 34 while maintaining the reliability at '0'. The flip-flop 34 stores 3-bit data '011' input by the enable signal.

When the VSB mode signal section of the next field sync signal is generated and no error is detected by the error detector 33, the data input to the flip-flop 34 through the serial / parallel converter 32 becomes '011', and the flip is performed. The data stored in the flop 34 also becomes '011'. The comparator 35 outputs '1' because the two input data are the same as '011', and the confidence counter 36 increases the reliability by one step. Thus, the value of the confidence counter 36 changes from 0 to 1.

In this case, since the input and output of the confidence counter 36 differ by one clock, when the count value of the confidence counter 36 changes to 1, the output counter 0 is the previous value 0, so that the confidence counter 36 is the flip-flop ( Output the enable signal. The flip-flop 34 stores input 3-bit data '011'. After that, since the reliability of the confidence counter 36 is 1 or more, the flip-flop 34 does not store any more input data, and the VSB mode signal output from the flip-flop 34 is always '011'. .

In this way, the VSB mode inserted at the transmitting side can be detected accurately, so that the digital TV receiver can also operate for CATV together with the terrestrial broadcasting receiver.

As described above, according to the VSB mode detection apparatus of the digital TV according to the present invention, the circuit is simplified by detecting the VSB mode inserted at the transmitting side using only the most significant bit having the code information among the input digital data. When integrated, the integration is easy and the IC size is reduced, which lowers the cost. In addition, if an error is detected in the VSB mode signal included in the field synchronization signal of the received signal, if an error is detected, the operation of all circuits used for the VSB mode detection is stopped and the VSB mode signal of the next field synchronization signal is detected. By waiting the interval, there is an effect of detecting the correct VSB mode. In addition, the digital TV receiver according to the present invention can operate for CATV with reception of terrestrial broadcasting.

Claims (13)

A sign bit extraction unit for extracting only the most significant bit having sign information when the analog data outputted from the tuner is converted into a predetermined bit of digital data and inputted; A serial / parallel converter for sequentially delaying data of code bits input in series from the code bit extractor for a predetermined clock and simultaneously outputting data sequentially delayed together with data input by an enable signal; An error detection unit configured to logically combine data output in parallel from the serial / parallel conversion unit to determine whether or not an error of input data is present; A storage unit for storing data having actual VSB mode information among parallel data outputted from the serial / parallel conversion unit only when an enable signal is inputted, and outputting the data as a VSB mode signal; A comparison unit comparing the data input to the storage unit with the data stored in the storage unit when it is determined that there is no error in the error detection unit; And a confidence counter that increases or decreases reliability according to a comparison result of the comparator and outputs an enable signal to the storage only when the reliability is less than a certain threshold value. The method of claim 1, wherein the sign bit extraction unit Residual sideband mode detection device of a digital TV characterized in that it operates only during the last 8 symbols of the VSB mode signal interval of the field synchronization signal. The enable signal of claim 1, wherein the enable signal of the serial / parallel conversion unit is Residual sideband mode detection apparatus of a digital TV, characterized in that occurs when the sign bit of the last symbol extracted by the sign bit extraction unit is input. The data output in parallel from the serial / parallel converter is a sign bit of the last 8 symbols of the VSB mode signal section of the field sync signal, and the upper 4 bits are 1 bit parity and actual VSB mode information. Residual sideband mode detection device of a digital TV, characterized in that consisting of three bits of data, the lower four bits are inverted form of the upper four bits. The method of claim 4, wherein the error detection unit First to fourth comparators for comparing whether data in an inverted relationship with each other among the outputs of the serial / parallel converter is inverted with each other; And an error discriminating unit configured to OR the outputs of the first to fourth comparators to determine the presence or absence of an error. The method of claim 5, wherein the first to fourth comparators Digital TV residual sideband mode detection device, characterized in that each consisting of an exclusive noah gate. The method of claim 4, wherein the error detection unit A fifth comparator configured to compare whether the number of '1' of the upper 4 bits of the output of the serial / parallel converter is an even number; A sixth comparator comparing the number of '1's of the lower 4 bit data among the outputs of the serial / parallel converter to maintain an even number; And an error discriminating unit configured to logically combine the output of the fifth comparator and the output of the sixth comparator to determine whether there is an error. The method of claim 7, wherein the fifth and sixth comparator Digital TV residual sideband mode detection device, characterized in that each consisting of an exclusive oar gate. The method of claim 1, And a delay unit configured to control the enable signal of the confidence counter to be one clock later than the enable signal of the serial / parallel converter. The method of claim 1, And a specific threshold value of the confidence counter is one. The method of claim 1, wherein the confidence counter is If an error is detected by the error detection unit, all circuit blocks are controlled to stop the operation and wait for the VSB mode signal section of the next field sync signal by maintaining the previous value regardless of the presence or absence of an input. Mode detection device. The method of claim 1, If the comparison result of the comparison unit indicates that the two data input is equal to each other, the confidence counter increases the reliability by one step each time the enable signal is input, and decreases the reliability by one step if it is not equal. Residual sideband mode detection device. When a high frequency (RF) signal is received through an antenna, a tuner selects a frequency of a desired channel by tuning and converts it into an intermediate frequency (IF) signal. An analog / digital conversion unit for demodulating the IF signal output from the tuner into I and Q signals of a baseband, locking the frequency and phase, and converting the IF signal into a digital signal of a predetermined bit; A sync recovery unit for detecting a data segment sync signal and a field sync signal from the output data of the analog / digital converter; A code bit extraction unit for extracting a sign bit of digital data input only during the last 8 symbols of a VSB mode signal section of the field synchronization signal detected by the synchronization recovery unit; A serial / parallel converter for converting the code bits inputted serially from the code bit extractor in parallel by sequentially delaying a predetermined number of clocks; An error detection unit configured to logically combine data output in parallel from the serial / parallel conversion unit to determine whether or not an error of input data is present; A storage unit for storing data having actual VSB mode information among parallel data outputted from the serial / parallel conversion unit only when an enable signal is inputted, and outputting the data as a VSB mode signal; A comparison unit comparing the data input to the storage unit with the data stored in the storage unit when it is determined that there is no error in the error detection unit; A confidence counter that increases or decreases reliability according to a comparison result of the comparator and outputs an enable signal to the storage only when the reliability is lower than a specific threshold value; A digital data decoding unit decoding data using the VSB mode signal output from the storage unit and the synchronization signal detected by the synchronization recovery unit; And a display unit for displaying the decoded data.

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