KR100240633B1 - Apparatus and method for wireless atm cell control system - Google Patents

Abstract

The present invention relates to a system for implementation and functional verification of wireless asynchronous transmission mode (ATM) transmission technology, and relates to a wireless packet synchronous receiving apparatus and method of a wireless ATM cell control system.

The wireless ATM transmission technology is a technology for wireless transmission by combining with an existing ATM wired network having a low error rate and high transmission efficiency in order to transmit various types of information such as voice, video, and data in a wireless section. Since ATM cells in a wired network are transmitted at high speed, a high speed wireless transmit / receive processing technique is required to process them over the air. In order for a wireless ATM transmitter to transmit an ATM cell to a destination with a low wireless transmission error rate, data modification only in a wireless section is required. Accordingly, the wireless ATM transmitter has a MAC function of inserting an address of a destination, a header, a trailer, etc. to have a low transmission error rate in an ATM cell. According to the present invention, in order to process a received wireless packet at a higher speed, a wireless packet synchronization receiver for detecting and receiving a header portion of a wireless received packet as a hardware synchronizer and then validating the trailer portion with software is provided. Implemented. The implementation of the radio packet synchronous reception device saves time for sequentially searching for data in order to receive a packet in the radio reception packet conversion device.

Description

Wireless Packet Synchronous Receiving Device and Method in Wireless Asynchronous Transmission Mode Transmission Device

The present invention relates to a system for implementing a wireless asynchronous transmission mode (hereinafter referred to as ATM) technology and functional verification, and relates to a wireless packet synchronization receiving apparatus and method of a wireless ATM cell control system.

Multimedia services represent various types of information such as voice, data, high-quality still images, and moving images. In order to provide a multimedia service including a video over the air, high-speed data transmission must be performed in a wireless access section. In addition, since multimedia services have a data rate from a low speed to a high speed, and a set call data amount may be variable, wireless ATM transmission technology is being developed in terms of efficient use of radio resources. The wireless ATM transmission technology is a technique for transmitting an existing ATM wired network having a low error rate and a high transmission efficiency to a wireless section in order to transmit various types of information in the wireless section.

Since ATM cells in a wired network are transmitted at high speed, a high speed wireless transmit / receive processing technique is required to process them over the air. In order to transmit an ATM cell to a destination with a low wireless transmission error rate in a wireless ATM transmitter, data modification only in a wireless section is required. The wireless ATM transmitter has a media access control (MAC) function that inserts a destination address, a header and a trailer for having a low transmission error rate in an ATM cell.

Accordingly, the present invention provides a wireless packet synchronization receiving apparatus and method for detecting and receiving a header portion of a wireless received packet as a hardware synchronizer to process the received wireless packet at higher speed, and then validating the trailer portion with software. Its purpose is to.

In accordance with another aspect of the present invention, there is provided an apparatus for receiving a wireless packet synchronization according to an embodiment of the present invention, comprising: an RS-422 receiver having a radio reception packet and a clock for restoring data received through a radio modulation and antenna unit; A shift register for storing the radio reception packet data input according to the RS-422 interface standard through the receiver as a radio packet, a comparison code consisting of an idle radio transmission packet bit and a header of the radio transmission packet, and output from the shift register A comparator for generating a synchronization signal by inputting data and the comparison code, respectively, and an interrupt signal generating means for generating an interrupt signal according to a synchronization signal generated from the comparator and a control signal supplied from a digital signal processing processor. It is characterized by.

The wireless packet synchronization receiving method according to the present invention for achieving the above object comprises the steps of initializing the synchronization receiving interrupt service routine and checking whether an interrupt has occurred, and if the interrupt is generated as a result of the check, confirming whether the synchronization is interrupted. If it is not a reception interrupt, repeating the interrupt generation check process, and if it is a synchronous reception interrupt, receiving and storing a wireless packet in a memory; Confirming whether a wireless packet error is detected, an address, a header, and a trailer when a wireless packet is received, and confirming whether or not an asynchronous transmission mode cell is to be transmitted; Only repeat the process Including the system.

1 is a block diagram of a wireless asynchronous transmission mode (ATM) transmission apparatus.

2 is a block diagram of a wireless packet synchronization receiving device of a wireless ATM transmission device.

3 is a wireless packet synchronous reception processing flowchart.

<Description of the code | symbol about the principal part of drawing>

1: 25 Mbps ATM network 2: 25 Mbps ATM matching module

3: wireless transmission packet conversion device 4: PC interface card

5 wireless receiving packet conversion device 6 wireless modulation and demodulation unit and antenna

7 wireless packet synchronization receiving device 8 operation and analysis device

9: 16 bit shift register

10: Comparator (16 Bit Comparator)

11: 16 Bit Compare Code

12: OR gate 13: RS-422 receiver

14: Sync Signal

15: 4Kbyte Serial-to-Parallel FIFO

16: Digital Bit Processing Processor

17, 18: Dual Port SRAM

1 is a configuration diagram of a wireless ATM transmission device, which includes a 25 Mbps ATM network 1, a 25 Mbps ATM matching module 2, a wireless transmission packet conversion device 3, a PC interface card 4, and a wireless reception packet conversion device 5. ), A radio modulation and demodulation unit and an antenna (6), a radio packet synchronization receiving device (7), and an operation and analysis device (8). The 25 Mbps ATM matching module 2 is responsible for ATM interworking between the existing 25 Mbps ATM network 1 and the wireless ATM transmitter. The radio transmission packet conversion apparatus converts an ATM cell into a radio transmission packet, and the converted radio transmission packet is transmitted to the radio modulation and demodulation unit and the antenna 6 through the RS-422 communication interface at a speed of 5 Mbps. The wireless transmission packet is wirelessly modulated by the radio modulation and demodulation unit and wirelessly transmitted to the destination via the antenna via the RF unit. In addition, at the time of reception, a radio reception packet received through the radio modulation and demodulation unit and the antenna 6 is transmitted to the radio packet synchronization reception device 7. The radio packet synchronization receiving apparatus 7 detects the start time of the received radio packet and generates a synchronization signal, and the synchronized radio reception packet is transferred to the radio reception packet converting apparatus 5 and converted into an ATM cell. The converted ATM cell is delivered to the 25 Mbps ATM network 1 through the 25 Mbps ATM matching module 2.

The present invention relates to an implementation of a wireless packet synchronization receiving apparatus of such a wireless ATM transmission apparatus, the block diagram of the configuration is shown in FIG.

The signal received from the antenna is demodulated via the radio demodulator (6), and the demodulated data is transmitted to the RS-422 receiver 13 of the radio packet synchronization receiving apparatus together with the clock for restoring the received data. The RS-422 receiver 13 transfers to the 16-bit shift register 9 of serial data according to the RS-422 interface standard. The 16-bit shift register 9 shifts the input data by one bit in accordance with the input clock. The 16-bit shift register 9 transfers 16-bit serially arranged data in parallel while transferring by one bit, and transmits the data to the input of the 16-bit comparator 10. The 16-bit comparator 10 performs bit comparison with the input contents of the 16-bit shift register 9 and the 16-bit comparison code 11. The 16-bit comparison code 11 consists of 8 bits of idle radio transmission packets and the header 8Bit of radio transmission packets. The 16-bit comparator 10 generates a synchronization signal 14 according to the comparison result between the two 16 bits. If the two 16 bits are the same, it is regarded as primary synchronization and makes the synchronization signal 14 active low. The synchronization signal 14 is input to the oar gate 12 which is an interrupt signal generating means, and generates an interrupt signal in accordance with a control signal of the 16-bit digital signal processor 16 in the wireless receiving packet conversion apparatus.

3 is a flowchart illustrating a procedure of a wireless packet synchronous reception method.

After initializing the synchronous reception interrupt service routine (301), it is checked whether an interrupt has occurred (302). If repeated, if a synchronous reception interrupt, the wireless packet is received and stored in the memory (306).

On the other hand, if it is determined that the interrupt has not occurred (302), if no interrupt has occurred, it is checked whether the wireless packet is received (303), and when the wireless packet is received, the wireless packet error detection, address, header and trailer (304). . After that, it is checked whether the ATM cell is to be transmitted (307). The ATM cell is transmitted or the interrupt generation confirmation 302 is repeatedly performed according to the confirmation 307.

That is, when an interrupt occurs, the digital signal processor 16 in FIG. 2 recognizes that the received packet is in a synchronous state and receives the packet from the serial-to-parallel first-in-first-out 15. The digital signal processing processor 16 checks the trailer portion of the received packet before converting the wireless received packet into an ATM cell to confirm that the received digital packet is finally synchronized. The finally confirmed radio received packet is converted into an ATM cell. The converted ATM cell is stored in the dual port SRAM 17 of the wireless receiving packet conversion apparatus, and transfers the ATM cell to the 25 Mbps ATM matching module to transmit the ATM cell to the wired network. In addition, the digital signal processor 16 transmits all information (statistical information such as the number of received wireless packets, the number of converted transmissions and the number of error occurrences) during the ATM cell conversion process of the wireless received packet through the dual port SRAM 18. Pass it to the interface card. The controller in the PC interface card sends statistical information to the IBM-PC according to the RS-232 interface specification.

The present invention relates to a wireless packet synchronization receiving apparatus which is a main part of a wireless ATM transmission apparatus, and is an apparatus for detecting a synchronization signal of a wireless ATM transmission packet received on a radio. According to the present invention, in order to process a received wireless packet at a higher speed, a wireless packet synchronization receiver for detecting and receiving a header portion of a wireless received packet with a hardware synchronizer and then validating a trailer portion with software is provided. Implemented. The radio packet synchronization receiving apparatus improves the sequential search method in the radio receiving packet converting apparatus, adopts the interrupt method by bit comparison, and receives the packet, thereby saving time required for searching the radio receiving packet converting apparatus. Therefore, it is possible to implement higher speed wireless data transmission technology in the future.

Claims (3)

An RS-422 receiver for inputting a radio reception packet and a clock for restoring data received through the radio modulation and demodulation unit and the antenna unit, respectively; A shift register for storing wireless reception packet data input according to the RS-422 interface standard through the RS-422 receiver as a wireless packet; A comparison code consisting of an idle radio transmission packet bit and a header of the radio transmission packet, A comparator for generating a synchronization signal by inputting data output from the shift register and the comparison code, respectively; And an interrupt signal generating means for generating an interrupt signal in accordance with a synchronization signal generated from the comparator and a control signal supplied from a digital signal processing processor. The radio packet synchronization receiving apparatus according to claim 1, wherein the interrupt signal generating means comprises an false gate. Initializing the synchronous receiving interrupt service routine and checking whether an interrupt has occurred; If the interrupt is generated as a result of the check, check whether the interrupt is a synchronous reception interrupt, and if not, perform the interrupt generation check process, and if the interrupt is a synchronous reception interrupt, receive and store a radio packet in a memory; If it is determined that the interrupt has not occurred, if the interrupt has not occurred, confirming whether or not the radio packet is received, checking the radio packet error detection, the address, the header, and the trailer when the radio packet is received, and then checking whether the asynchronous transmission mode cell is to be transmitted. Wow, And transmitting the asynchronous transmission mode cell or repeating the interrupt generation confirmation process according to the confirmation result.

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