JP2799947B2 - Mobile phone system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable telephone system comprising a base station and a plurality of mobile stations wirelessly connected to the base station.

[0002]

2. Description of the Related Art In recent years, a digital portable telephone system, which is a second generation cordless telephone, has been developed instead of an analog cordless telephone. This mobile phone system adopts a digital system for communication between a mobile station called PS and a base station called CS, and performs analog-to-digital or digital-to-analog conversion of an analog signal such as voice to perform digital communication as a digital signal. It is intended to do.

FIG. 7 shows the configuration of such a portable telephone system, in which a base station 1 is connected via a subscriber line L, and the base station 1 and four mobile stations 21 to 24 are wirelessly connected. By the way, a 1.9 GHz band is used as a radio frequency band, and a carrier frequency interval is 300 KH.
z. Then, communication can be performed between one base station and four mobile stations via one frequency band. In this case, this frequency is time-divided into eight time slots to eight time slots within 5 msec as shown in FIG. The base station 1 transmits data to each mobile station in the first four time slots, and receives data from each mobile station in the remaining four time slots. In this case, 625 μsec (5 m
sec / 8), and the data for one slot is 240 bits, so that the transmission of 1-bit data takes about 2.6 μsec, and the speed of the data transmitted and received is 384 KHz. It has become. As described above, since the same frequency can be used by four mobile stations, radio waves can be effectively used.

FIG. 9 is a diagram showing a configuration of a data transmission / reception circuit of a mobile station 2 for transmitting / receiving data to / from a base station 1. FIG. 9 (a) shows a data transmission circuit, and FIG. 9 (b) shows a data reception circuit. is there. 9A, the data transmission circuit includes 16-bit latch circuits 200 and 201, a 32-bit shift register 202, and a shift control circuit 203. In FIG. 9B, the data receiving circuit includes 16-bit latch circuits 210, 211, and 32, respectively.
Bit shift register 212, latch control circuit 213
It consists of.

Here, when the CPU 34 transmits data to the base station 1, data is first set in each of the latch circuits 200 and 201. Thereafter, when the timing of transmitting data to the base station 1 arrives, the shift register 202 synchronizes the 32-bit parallel data set in each latch circuit with the 384 KHz clock signal CK and the signal from the shift control circuit 203. The base station 1 reads out and transmits the serial transmission signal SOUT to the base station 1 side. In this case, the shift control circuit 203 outputs an interrupt signal to the CPU 34 when detecting the end of the data transmission of the shift register 202. Then, the CPU 34 sets the next 32-bit data in each latch circuit, so that the next 32-bit data is transmitted to the base station 1 side.

Next, when data from the base station 1 is received by the receiving circuit, when the serial data SIN arrives at the shift register 212, the shift register 212
32 bits of the received data are sent to each of the latch circuits 210 and 211 in synchronization with the clock signal CK 1, and are latched as parallel data under the control of the latch control circuit 213. Here, the latch control circuit 213 outputs an interrupt signal to the CPU 34 upon completion of the latch. Then, CP
U34 takes out the 32-bit data from each latch circuit and stores it in a memory or the like. At this time, the next 32-bit data is sequentially latched by the latch circuits 210 and 211.

[0007]

As described above, in the conventional mobile station, when performing data communication with the base station, the next data transmission processing or data fetch is performed by an interrupt signal generated every time data is transmitted or received in 32 bits. Processing is in progress. Here, these interrupt intervals are set to 83.3 (2.6 × 3) because the 1-bit transmission rate of data is 2.6 μsec.
2) It is a short time of μsec. For this reason, conventionally,
If each of the above processes is not completed in such a short time, the next data may be overwritten or the next data may not be received, and the load on the CPU is increased. CPU is needed and CPU
During this period, other processes cannot be executed, and the processing efficiency of the CPU is low.

At the head of the received data, there is provided a 4-bit type signal CI indicating the type of the received data, and the conventional receiving circuit converts the type signal CI and the following data directly into 32-bit parallel data. Convert to CPU
To give. Accordingly, the CPU separates the type signal CI from the subsequent data after inputting the parallel data, and analyzes the subsequent data based on the type signal CI thus divided, so that there is a problem that it takes time to analyze the data. .

Accordingly, an object of the present invention is to reduce the transmission processing and reception processing of the CPU when data is transmitted and received at high speed.

[0010]

In order to solve the above-mentioned problems, the present invention comprises a base station and a plurality of mobile stations wirelessly connected to the base station. In a mobile phone system for performing data communication between a base station and a plurality of mobile stations, a first memory for storing transmission data, a first DMA unit for transferring data in the first memory, and a first DMA A first FIFO unit for performing first-in first-out of data transferred by the unit is provided as transmission means, and a second FIFO unit for performing first-in first-out data transfer from a partner station and a second FIFO unit for transferring data in the second FIFO unit are provided. 2 and a second memory for storing data transferred by the second DMA unit as receiving means. Further, a receiving register for storing a type signal included in the received data and indicating the type of the received data is provided in the receiving means.

[0011]

When, for example, transmission data is accumulated in the first memory by the CPU, this data is transferred to the first FIFO unit by the first DMA unit, and the first FIFO unit performs first-in first-out operation to perform the first-in first-out operation. And when data from the partner station is stored in the second FIFO unit,
The received data is transmitted to a second FIFO by a second DMA unit.
Read from the storage unit in the order of accumulation and transferred to the second memory;
Processed by the CPU. As a result, the load on the CPU when transmitting and receiving data at high speed is reduced, and the processing efficiency of the CPU can be improved. The reception register stores a type signal indicating the type of the received data. As a result, the type signal and the received data following the type signal can be distinguished, so that the processing time of the CPU in analyzing the subsequent received data based on the type signal is reduced, and the efficiency of the data receiving process of the CPU is improved. improves.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 5 is a block diagram of a mobile station constituting the mobile phone system of the present invention. In FIG. 1, the mobile station 2 is wirelessly connected to the base station 1 via a wireless unit including an antenna AT, a high frequency unit 21A, a wireless control unit 21C, and a wireless interface unit 21D.

Here, the wireless interface unit 21D includes:
Unique word detector 2 via timing bus TBS
2. Timing generation unit 23, reception CI inspection unit 24, scramble unit 25, CRC processing unit 26, reception data register 27, transmission data register 28, transmission data connection unit 2.
9, a simple confidentiality section 30, speed conversion sections 31 and 32, and a voice processing section 33 are connected.

The system bus SBS includes the above-mentioned reception CI checking section 24, transmission data linking section 29, speed conversion section 3
Each part except for 1 and 32 is connected, and the CPU 3
4. The operation unit 35 and the display unit 36 are connected. In addition,
A handset 37 and a ringer 38 necessary for a telephone call are connected to the voice processing unit 33.
It operates by the power supply from.

[0015] The mobile station 2 thus configured is connected to the base station 1.
When data communication is performed with the base station, data is received from the base station 1 via one of the eight time slots in which one frequency is divided every 5 msec. Then, data is transmitted to the base station 1 via a slot delayed by four slots from the reception slot. The time slot is 625 μsec (5 msec) per slot.
c / 8) is allocated and the data for one slot is 240 bits. Therefore, the data for one bit requires about 2.6 μsec. Therefore,
The speed of the transmitted and received data is 384 KHz.

FIG. 6 is a diagram showing the format of data transmitted to and received from the base station 1. As data, 224 bits of information are transmitted and received per slot. Here, from the 240-bit data for one slot,
The 16-bit data obtained by subtracting the 4-bit data is used as a guard time for preventing data (transmission burst signal) from colliding between two adjacent slots. A time slot is roughly divided into a control physical slot and a communication physical slot, and the control physical slot has a channel called SCCH. The SCCH channel is a channel for individual cells, and is a channel for transferring information necessary for call connection.
The communication physical slot has an information channel called TCH, a FACCH channel, and the like.
The CCH channel is a channel for temporarily transferring data by stealing the TCH channel.

As shown in FIG. 6A, the control physical slot includes, for example, a transient response ramp time R of 4 bits, a start symbol SS of 2 bits, a preamble PR of 62 bits, a unique word UW of 32 bits, and a data of 32 bits. , A 42-bit destination identification code, a 28-bit calling identification code, a 34-bit control information I, and a 16-bit error detection CRC (Cyclic).
Each data area such as RedundancyCheck) is allocated.

As shown in FIG. 6 (b), the communication physical slots are 4
And a 2-bit ramp time R and a start symbol S
S is assigned, followed by a 6-bit preamble P
R, a 16-bit unique word UW is allocated. Subsequently, the 4-bit type signal CI, TCH
A 16-bit control channel SA which is a channel associated with the channel, a 160-bit information I, a 16-bit error detection CRC, and the like are assigned. FIG.
6A and FIG. 6B, data from the head to the unique word UW indicates synchronous data.

Next, the operation of the mobile station 2 for transmitting data in the above-described format will be briefly described with reference to FIGS. When a radio signal having a frequency of about 1.9 GHz is transmitted from the base station 1 to the mobile station 2, the radio signal including the antenna AT, the high-frequency unit 21A, the radio control unit 21C, and the radio interface unit 21D transmits the radio signal. Removes high frequency components and performs demodulation to achieve a frequency of 384 KHz
Is output from the wireless interface unit 21D as received data a.

The received data a is received by the unique word detecting section 22 and the received CI checking section 24. In each section, based on each reception timing output of the timing generating section 23, each unique word is selected from among the burst-shaped received data a. A type signal CI indicating a received data type such as a UW and a channel type is detected. The detected information is fed back to the timing generation unit 23, and is used to generate timing required for subsequent data reception. Then, the generated timing signal is transmitted to the timing bus TB.
The signal is output to the transmission / reception processing units such as the scramble unit 25, the simple secret unit 30, and the voice processing unit 33 via S. in this case,
The scrambler 25 removes the scramble for maintaining the DC balance of the code string applied to the received data a and outputs it to the received data register 27.

In the CPU 34, these unique words U
Based on the reception timing output after detecting the W and the type signal CI, data such as a destination identification code, a calling identification code and information I stored in the reception data register 27 after the channel type CI are input via the system bus SBS. If these identification codes correspond to the own device, various protocol processing and received data processing are performed.

As described above, in the mobile station 2, when processing the reception data a, the unique word detection unit 22 and the reception CI
The inspection unit 24 detects the unique word UW and the type signal CI indicating the type of the received data, and based on these detections, generates the subsequent data reception timing, and generates a scramble unit 25, a CRC processing unit 26, and a reception data register 2.
7, transmission data register 28, transmission data linking unit 29,
The speed converters 31 and 32 are configured to operate without the CPU 34 interposed therebetween. As a result, the load on the CPU 34 is reduced, and
No. 4 can perform subsequent data processing with sufficient time, and since an accurate timing signal is generated according to the type of received data, there is no loss of a burst signal and efficient data reception. Processing can be performed.

When the received data a is the information I of the physical slot for communication and indicates a voice signal, the information is canceled in the simple privacy section 30, and
The signal is expanded into a signal of 32 KHz by the speed converter 31, converted into an analog signal by the audio processor 33, and output from the handset 37.

When the CPU 34 detects a transmission operation of the operation unit 35, it creates data based on the above-described format and outputs the data to the transmission data register 28. The transmission data register 28 transmits the transmission data based on each transmission timing from the timing generation unit 23 to the data connection unit 2.
9 to the CRC processing unit 26. The CRC processing unit 26 adds an error detection code to the transmission data and sends the transmission data to the scramble unit 25, and the scramble unit 25 applies a DC balance to the transmission data and sends it as transmission data b to a radio unit such as the radio interface unit 21D. Then, the radio section modulates the transmission data b and superimposes the modulated signal on a high frequency and transmits the radio signal to the base station 1 as a radio signal.

In this manner, the calling protocol is executed with the base station 1 to call the other terminal, and the call is started by the response of the other terminal. In this case, the audio signal from the handset 37 is converted into a digital signal with a frequency of 32 KHz by the audio processing unit 33, further compressed to a frequency of 384 KHz by the speed conversion unit 32, and sent to the simple secret unit 30. The simple confidential section 30 performs confidential control on the voice data, for example, taking an exclusive OR, and sends the voice data to the transmission data linking section 29. Thereafter, the voice data is transmitted to the partner terminal via the base station 1 via the above-described route.

FIG. 1 is a block diagram showing a main part of the mobile station 2 and showing a configuration of a data transmitting / receiving circuit of the mobile station 2 for transmitting and receiving data to and from the base station 1. Here, FIG. 1A shows a data transmission circuit, and FIG. 1B shows a data reception circuit.
The data transmission circuit is a transmission data register 28 that transmits data by a signal from the above-described timing generation unit 23 that generates various timing signals by a clock signal CK of 384 KHz. As shown in FIG. 1A, the transmission data register 28 includes a memory 28A (first memory) and a transmission FIFO unit 28B (first FIFO).
) And a parallel / serial conversion unit 28C.

Now, the transmission interrupt circuit 23A is activated by the timing signal from the timing generation unit 23, and when the transmission interrupt signal is output from the transmission interrupt circuit 23A to the CPU 34, the CPU 34 transmits necessary signals via the data bus DB. The transmission data is written to the memory 28A. The transmission data written in the memory 28A is transmitted to the DMA unit 34A (first DMA unit).
And transferred to the transmission FIFO unit 28B. The transmission FIFO unit 28B is composed of 16 bits × 13 words, sequentially stores the transmitted transmission data, and sequentially reads out the data stored first by the transmission timing signal from the timing generation unit 23. Then, the signal is sent to the parallel / serial converter 28C, and is sent to the base station 1 as a serial transmission signal SOUT (transmission data b).

The data receiving circuit shown in FIG. 1B includes the above-described reception CI checking unit 24 for receiving data in response to a timing signal of the timing generation unit 23, and a reception data register 27. Here, as shown in FIG. 1B, the reception CI checking unit 24
4A (reception register) and the like, and the reception data register 27 includes a memory 27A (second memory),
It comprises a reception FIFO unit 27B (second FIFO unit) and a serial / parallel conversion unit 27C.

Now, the received data a from the base station 1 is converted to a serial / parallel converter 27C as a serial signal SIN.
, And is input based on the clock signal CK, the serial / parallel converter 27C converts the received data into a parallel signal. The parallel reception data is sent to a reception FIFO unit 27B having a 16-bit × 13-word configuration by a timing signal from the timing generation unit 23, and is sequentially accumulated. In addition, 4 indicating the type of the received data
Only the bit configuration type signal CI is received by the reception CI register 24.
A. The received data stored in the reception FIFO unit 27B is read by the DMA unit 34B (second DMA unit) and transferred to the memory 27A. Here, the reception interrupt circuit 23B is activated by the timing signal indicating the completion of reception from the timing generation unit 23A, and the reception interrupt circuit 2B is activated.
When an interrupt signal is output from the CPU 3B to the CPU 34, the CPU
Reference numeral 34 reads the received data from the reception CI register 24A and the memory 27A and performs the received data processing.

Next, FIGS. 2A and 2B are flowcharts showing the data transmission operation and data reception operation of the mobile station. FIG. 3 is a timing chart showing data transmission and reception operations of the mobile station 2. The operation of the mobile station 2 will be described in more detail with reference to FIGS. As shown in FIGS. 3 (a) and 3 (b), assuming that the transmission time slot of this mobile station is T1 and the reception time slot R1, the transmission interruption circuit 23A and the reception interruption circuit 23B transmit a transmission interruption to the CPU 34. The timings of the signal and the reception interrupt signal are timings indicated by arrows in FIGS. 3C and 3D, respectively.

That is, when the format of the reception data a and the transmission data b is as shown in FIG. 3 (e), the output timing of the reception interrupt signal to the CPU 34 is, as shown in FIG. At which point the reception of the signal CRC is completed. The output timing of the transmission interrupt signal is also shown in FIG.
As shown in (g), the signal is output at the time of completion of transmission of the signal CRC of the transmission data b, which is output at the time of transmission in the immediately preceding transmission time slot.

The transmission interruption signal is transmitted to the transmission interruption circuit 2
When output from 3A to the interrupt terminal INT of the CPU 34,
The CPU 34 sends the interrupt clear signal CLR to the transmission interrupt circuit 2 in step ST1 of the transmission interrupt processing shown in FIG.
Output to 3A and clear. Then, in step ST2, it is determined whether there is transmission data to be transmitted to the base station 1. If there is transmission data, the transmission data is set in the memory 28A, and the start address of the data set in the memory 28A and the set data amount are indicated. Step S for address length
At T3, it is set in the DMA unit 34A. Then step ST
In step 4, the DMA unit 24A is started.

Then, the DMA 34A transmits the data of the memory 28A at the timing shown in FIG.
Transfer to the FO unit 28B. After that, DM in step ST5
While determining the end of the data transfer operation of the A section 34A,
When the end of the operation of the DMA unit 34A is confirmed, step S
After confirming "is the first transmission data?" At T6, if this becomes "Y", the transmission port is turned on at step ST7 and the transmission interrupt processing is terminated. Thus, the DMA unit 34A
The transmission data accumulated is transferred to the transmit FIFO portion 28B from, based on the transmission timing signal of the next transmission time slot from the timing generator 23, a serial signal SOUT is read into parallel-to-serial converting unit 28C
Is transmitted to the base station 1 side.

The received data a from the base station 1, that is, the serial signal SIN is transmitted to the serial / parallel converter 27.
The signal is converted into a parallel signal by C and sequentially stored in the reception CI register 24A and the reception FIFO unit 27B. When the storage up to the signal CRC is completed, a reception interrupt signal is output from the reception interrupt circuit 23B to the CPU. in this case,
In step ST11 of the reception interrupt process shown in FIG. 2B, the CPU 34 first outputs an interrupt clear signal CLR to the reception interrupt circuit 23A to clear it. Then step ST
In step 12, it is determined whether the signal CRC stored in the reception FIFO unit 27B is good or not.
In step 3, the receiving address is set for the DMA unit 34B, and the DMA unit 34B is started in step ST14.

Then, the DMA 34B sequentially transfers the reception data stored in the reception FIFO unit 27B to the address of the memory 27A specified in step ST13 at a timing as shown in FIG. Thereafter, the end of the data transfer operation of the DMA unit 34B is determined in step ST15, and when the end of the operation of the DMA unit 34B is confirmed, a data reception notification is performed in step ST16, and the reception interrupt process ends. When the data reception notification is issued from the reception interruption processing, the CPU 34 executes the reception data processing for reading and processing the reception data from the reception CI register 24A and the memory 27A.

As described above, the mobile station 2 is provided with the DMA unit 34
A and 34B, a transmission FIFO 28B unit, and a reception FIFO unit 27B are provided, and these units transmit and receive data to and from the base station 1, thereby reducing the load on the CPU 34 when transmitting and receiving data.

Next, FIG. 4 is a diagram showing the data receiving operation in the mobile station 2 in detail. In the case of the FACCH channel, the data received by the receiving circuit of the mobile station 2 includes the above-described 4-bit type signal CI, 16-bit control channel signal SA, 160-bit information I, and 16-bit error detection signal CRC. Yes, and are sequentially received by the receiving circuit from the type signal CI. In this case, the leading 4-bit type signal CI is converted into a parallel signal by the serial / parallel conversion unit 27C, is taken into the reception CI register 24A, where the bit conversion is performed, and is passed to the CPU 34.

On the other hand, the 16-bit control channel signal SA following the type signal CI and the 160-bit information I etc. are converted into parallel signals by the serial / parallel conversion unit 27C, and then converted to the reception FIFO unit 27B in 16-bit units. after captured were further transferred by DMA unit 34B to the memory 27 A, it is passed to the CPU 34. As a result, CPU3
4, the 4-bit type signal is stored in the reception CI register 24.
A, the 16-bit signal SA and the 16-bit information I are read from the memory 27A every 16 bits.
The data can be processed as it is. Therefore, the CPU 34
In the data receiving process, there is no need to separate and assemble the signals CI, SA and I in the data receiving process, and the processing efficiency is greatly improved.

[0039]

As described above, according to the present invention, the first memory, the first DMA unit and the first FIFO unit are provided as the transmitting means, and the second memory and the second memory are provided as the receiving means. A transmission unit that includes a DMA unit and a second FIFO unit. For example, when transmission data is accumulated in a first memory by a CPU, the transmission data is transferred to a first FIFO unit by a first DMA unit.
When the data from the partner station is stored in the second FIFO unit, the data is transferred to the second FIFO unit.
Is read from the second FIFO unit in the order of accumulation by the DMA unit, transferred to the second memory, and processed by the CPU. Therefore, when data is transmitted and received at high speed, for example, overwriting of received data (for example, due to processing delay of the CPU) Overwriting) and the like are prevented, and the CPU can perform data reception processing and the like with a margin, which has the effect of improving the processing efficiency of the CPU. In addition, a reception register is provided, and the type signal indicating the type of the received data is stored in the reception register. Therefore, the type signal and the received data following the type signal are separated, and therefore, the subsequent type is determined based on the type signal. There is an effect that the processing time of the CPU when analyzing the received data is reduced, and the efficiency of the receiving process of the CPU can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a mobile phone system according to the present invention.

FIG. 2 is a flowchart showing an operation of a main part of the mobile phone system.

FIG. 3 is a timing chart showing data transmission / reception timings of mobile stations constituting the mobile phone system.

FIG. 4 is a diagram showing a data reception situation in a mobile station.

FIG. 5 is a block diagram illustrating a configuration of a mobile station.

FIG. 6 is a diagram showing a format of data communicated by the mobile phone system.

FIG. 7 is a diagram showing a configuration of a mobile phone system.

FIG. 8 is a diagram showing transmission timing in a mobile phone system.

FIG. 9 is a block diagram of a data transmission / reception circuit in a conventional mobile station.

[Explanation of symbols]

 Reference Signs List 1 base station 21 to 24 mobile station 23 timing generation unit 23A transmission interruption circuit 23B reception interruption circuit 24 reception CI inspection unit 24A reception CI register (reception register) 27 reception data register 27A memory (second memory) 27B reception FIFO Unit (second FIFO unit) 27C serial / parallel conversion unit 28 transmission data register 28A memory (first memory) 28B transmission FIFO unit (first FIFO unit) 28C parallel / serial conversion unit 34 CPU 34A DMA unit (second memory) 1 DMA section) 34B DMA section (second DMA section)

Claims (2)

(57) [Claims] 1. A mobile telephone system comprising a base station and a plurality of mobile stations wirelessly connected to the base station, and performing data communication between the base station and the plurality of mobile stations in predetermined time slots. A first memory for storing data to be transmitted, a first DMA unit for transferring data in the first memory, and a first DMA
A first FIFO unit for performing first-in first-out of data transferred by the unit as a transmission unit, and a second FIFO unit for performing first-in first-out of data from a partner station;
A mobile phone system comprising, as receiving means, a second DMA unit for transferring data of a second FIFO unit and a second memory for storing data transferred by the second DMA unit. 2. The mobile telephone system according to claim 1, wherein said reception means includes a reception register included in received data and storing a type signal indicating a type of the received data. system.