KR100224108B1 - User overhaed outer connection control apparatus for synchronous digital hierarchy - Google Patents

Abstract

A user overhead external access control device of a synchronous transmission apparatus, comprising: an overhead extractor for extracting E1, E2, F1, F2, F3, and DCCm bytes, and E1 or E2 or F1 to F3 or DCCm bytes as a first-in first-out memory; A multiplex / demultiplex section for retiming the clock to the system clock and loading it on a transmit or receive bus, and a transmit or receive time switch and one or more external switches for allocating timeslots on the transmit or receive bus for each overhead. It has a device connection portion, characterized in that consisting of an interface unit for transmitting the data re-timed by the transmission or reception time switch to the corresponding external device connection unit or reversely transmitted.

Description

USER OVERHAED OUTER CONNECTION CONTROL APPARATUS FOR SYNCHRONOUS DIGITAL HIERARCHY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous transmission device (hereinafter referred to as SDH) in an exchange system, and more particularly to an apparatus for connecting user overheads to the outside.

20PPM) 자체 발진 클럭으로 송신하게 되고 이때 자체 발진 클럭의 안정도는 약

4.6PPM이다. 서로 마스터로서 동작할 때는 시스템 사이의 클럭이 비동기된 상태이고 그런 상황하에서도 E1, E2바이트는 정비통신용 채널이므로 안정된 통화가 이루어져야 한다.The SDH device uses the system clock through two modes. One is a master mode, in which a clock received from a satellite synchronization clock receiver is used as a system clock. The other is slave mode, which uses a PLL (Phase Locked Loop) on its own clock to synchronize the received clock with the system clock. When operating in slave mode, if the reception clock is deteriorated due to failure of the other party's equipment, obsolescence or optical line deterioration (approximately

20PPM) self-oscillating clock, and the stability of the self-oscillating clock is about

4.6 PPM. When operating as masters with each other, the clocks between the systems are asynchronous, and even in such a situation, E1 and E2 bytes are maintenance communication channels, so stable calls must be made.

Recently revised ITU standards (G.707, G.781, G.782, G.783) have increased the number of effective overheads included in one SDH frame. That is, E1 and E2 bytes and DCCr (D1 to D3) bytes, which were previously used for order wires, were used, but F1 to F3 bytes and DCCm (D4 to D12, which were reserved for 'reserved'. By using new bytes, the range of use has been expanded. In this case, the DCCr bytes are used to connect to an external operation system, such as a workstation, and the DCCm bytes are a user communication channel. Therefore, SDH equipment used to date must also be converted to accommodate this change.

1 is a diagram illustrating a structure of an SDH frame. (a) schematically illustrates the structure of the SDH frame, wherein one SDH frame includes a regenerator section overhead RSOH, an AU pointer, a multiplex section overhead MSOH, and a path overhead. overhead) consists of POH and STM-N payload. (b) specifically illustrates regenerator section overhead RSOH and multiplex section overhead MSOH and pass overhead POH.

The elements that make up each section overhead include: A1 and A2 are framing, D1 to D3 are 192 Kbps data channels for regenerator operation, D4 to D12 are 576 Kbps data channels for multiplexer operation, C1 is STM-1 indicator, E1 and E2 are order Wire (order wire), F1 is user channel, B1 and B2 are bit interleaved parity, K1 and K2 are multiplex section protection signaling, Z1 and Z2 are spare, X is reserved channel , * Is media-dependent. In the pass overhead POH, J1 is VC3, VC4 path trace, B3 is pass bit interleaved parity, C2 is signal level, F2 and F3 are user channels, G1 is in a pass state, H4 is a position indicator and Z4 and Z5 are spares.

2 is a view showing the configuration of a user overhead connection control device of a conventional synchronous digital system equipment. A plurality of Tri B'Ds (E1, E2 byte boards) 10 and 20 are directly connected to the O / W unit 30, and the O / W unit 30 is connected to the subscriber telephone 40. The O / W unit 30 includes a relay, that is, a switching circuit 35. Each Tri B'D 10, 20 is implemented optically or electrically (optic, electric).

According to the conventional SDH equipment that followed the ITU specification before the change, the 'preliminary' ones defined as the overhead of the SDH frame are usually terminated at the ASIC output stage. Specifically, the overhead to be connected to the user was only E1 and E2, and since the E1 and E2 are channels for order wires of 64 Kbps, they have a simple structure of connecting directly to the order wire unit. At each board, E1 and E2 headed to the O / H unit for each Tx and Rx, and the number of lines was enough to handle the back board. However, as the ITU standard changes and the demand for SDH equipment increases, the number of lines becomes more and more necessary, and it is not enough for the back-board to handle it, and it is difficult to meet the various connection types desired by the user.

Accordingly, an object of the present invention is to provide an overhead access device that can connect a large number of user overheads in an SDH device with a simple structure in an efficient manner.

In order to achieve the above object, a user overhead external access control device of the synchronous transmission device includes an overhead extractor for extracting E1, E2, F1, F2, F3 and DCCm bytes, and E1 or E2 as a first-in first-out memory. Or a multiplex / demultiplex section that retimes F1 to F3 or DCCm bytes according to the system clock and loads them on a transmit or receive bus, and transmits or numbers to allocate timeslots on the transmit or receive bus for each overhead. And an interface unit having a credit time switch and at least one external device connection unit and transferring data retimed by the transmission or reception time switch to the corresponding external device connection unit or vice versa.

1 is a view showing the structure of an SDH frame

2 is a configuration diagram of a user overhead access control apparatus of a conventional synchronous digital system equipment

3 is a configuration diagram of a user overhead access control apparatus of synchronous digital system equipment according to an embodiment of the present invention;

4 illustrates a method of accessing the first-in first-out memory of FIG.

5 is a graph showing an error occurrence period when the system clock is asynchronous

6A and 6B illustrate an 8M bus time slot assignment state according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. Also, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a configuration diagram of a user overhead access control apparatus of synchronous digital system equipment according to an embodiment of the present invention. Reference symbols B'D1 and B'D2 each represent one board. For simplicity, each is shown one by one, but in practice there are ten such boards, and the sum of the data output from or transmitted to them is carried on the 8M transmit or receive buses Tx_BUS and Rx_BUS. The user overhead connection control device includes an O / H extraction unit, a multiplex / demultiplex unit, an interface unit, and an order wire unit.

O / H extraction consists of STM ASIC 31 and mapper ASIC 32. STM ASIC 31 extracts 64 Kbps of E1, E2, F1, DCCr and DCCm bytes, and mapper 32 extracts 64 Kbps of F2, F3 bytes. Here, STM means one frame of 155M in SDH. The multiplex / demultiplex section includes a first overhead detection control section 33, a first first-in first-out memory (FIFO: FIFO) 35, a second overhead detection control section 34, and a second first-in first-out memory 36.

The multiplex / demultiplex unit retimates the 64 Kbps of E1, E2, F1 to F3 and 576 Kbps of DCCm bytes according to the system clock and loads them on the transmission bus Tx_BUS. At this time, since DCCr is not a user overhead, it is separately processed in a DCU (Data Communication Unit). In this case, the board slot values are written in software for each slot in which each board is mounted. The time slot values in the transmit or receive buses Tx_BUS and Rx_BUS are determined by the assigned board slot values.

The interface unit 50 includes the first and second time switches 51 and 52, the interface control unit 53 and the multiplexer / demultiplexer 54 and the G.703 connection unit 55, the V.11 connection unit 56, and the G.736 connection unit 57 and the PLL 58. It consists of. The first and second time switches 51 and 52 switch data to be transmitted from the transmit bus Tx_BUS or to the receive bus Rx_BUS. In order to provide any overhead with the desired connection type, the setting value must be able to connect the desired overhead with the connection type. The minimum unit of switching is 1/128 slot on 64Kbps 1 channel, 8M transmit or receive bus Tx_BUS, Rx_BUS bus. An example of a commercial integrated circuit (IC) is the MT8986AP manufactured by MITEL.

The G.703 connection 55, the V.11 connection 56 and the G.736 connection 57 are directly connected to an external device, that is, a subscriber telephone or a workstation. Specifically, the G.703 connector 55 is a 64 Kbps (codirectional) connection and is connected to the outside through a predetermined connector (9pin connector) on the terminal side. G.736 connection 57 is a connection that satisfies the G.736 standard of the Conference of European Postal and Telecommunication Administrations (CEPT), and is connected to the outside through a predetermined connector (15 pins) on the terminal side. do. The V.11 connector 56 is a connector that satisfies the RS422 standard, and is connected to the outside through a predetermined connector (15 pins) on the terminal side. In addition, the V.11 connection 56 provides 576 Kbps for DCCm in addition to 64 Kbps. PLL 58 is provided separately to make 576 Kbps of V.11 connection 56. The multiplexer / demultiplexer 54 serves to transfer data between the V.11 connector 56 or the PLL 58 and the first or second time switches 51 and 52. The interface controller 53 controls programs of the first and second time switches 51 and 52 and the multiplexer / demultiplexer 54 to control the overall operation of the interface unit 50 (eg, ALTERA). Include.

Meanwhile, the E1 and E2 overheads required by the order wire unit 30 are provided in a separate format desired by the order wire unit 30 through the first and second time switches 51 and 52 in the interface unit 50.

4 is a diagram illustrating a method of accessing the FIFO of FIG. 3. Even when SDH devices are connected to each other for any reason, even if the system clocks are not locked to each other, the voice communication channels E1 and E2 bytes used by the mechanics must maintain the quality that the call can be made. Since there is a slip between the data and the system clock, you have a corresponding memory, or FIFO, to maintain the channel quality that the call can be made. In this embodiment, a 512-bit depth FIFO is used, and half of the FIFO size is recorded first and then read (hereinafter referred to as 'read after write'). Increase In this embodiment, a maximum loss of 512 bytes occurs per error occurrence period. If a FIFO full or empty occurs due to the asynchronous clock, the FIFO reset (read / write point zeroization) is applied until the start of the next reception frame, and then the read operation is performed again after the pre-write.

The table below shows the error occurrence cycle during system clock asynchronous operation using STM1 E1 byte. A test method of loop-backing the STM1 E1 from the interface unit 50 in a PRBS state was performed. The ANRITSU MP1560A was used as an instrument. In this table, () means the actual PPM difference.

[table]

Stability (PPM) Bit errors Bit error rate Occurrence time Error occurrence cycle + 5 (+ 4.5) 161 327 2.9E-06 3.0E-06 13 minutes 54 seconds (the first) 28 minutes 2 seconds (the second) 14 minutes 8 seconds -5 (-5.5) 184 393 3.9E-06 11 minutes 52 seconds (primary) 23 minutes 58 seconds (secondary) 12 minutes 6 seconds + 10 (+ 9.5) 142 323 4.6E-06 6.0E-06 6 minutes 50 seconds (the first) 13 minutes 38 seconds (the second) 6 minutes 48 seconds -10 (-10.5) 193 380 5.5E-06 6.8E-06 8 minutes 23 seconds (primary) 14 minutes 18 seconds (secondary) 5 minutes 55 seconds + 20 (+ 19.5) 136 317 1.2E-05 1.3E-05 2 minutes 35 seconds (1st) 5 minutes 58 seconds (2nd) 3 minutes 23 seconds -20 (-20.5) 148 269 1.6E-05 1.3E-05 1 minute 58 seconds (1st) 5 minutes 2 seconds (2nd) 3 minutes 4 seconds

The first and second overhead detection controllers 33 and 34 are field programmable gate arrays (FPGAs). The first and second overhead detection control units 33 and 34 are system programmable gate arrays (FPGAs). Retiming to match the clock and generating signals for controlling the respective FIFOs 35 and 36. The FPGA is very expensive, even though most of them have no internal memory. In addition, when the memory required for multiplex / demultiplex is used as an internal flip-flop, FPGAs become very large and costly. Therefore, as mentioned above, the FPGA generates only the control signal and the necessary memory is externally attached, thereby reducing the cost burden and facilitating the control.

First, the operation in the case where data is transferred from the STM ASIC 31 to the FIFO 35 will be described in detail. After the stable reset time, the retimed data provided from the first overhead detection controller 33 is received and recorded using the reception clock provided by the STM ASIC 31. Recording continues and the system clock (8M) is activated when the recorded amount reaches 1/2 of FIFO 35, which is activated by the assigned time-slot (1/128 slot of 8M for 64Kbps data, 9/128 slot for 576Kbps data). Make and read). If a FIFO full or amplifier occurs due to sleep, a FIFO reset is performed to make all the write / read pointers zero, and then the above operation is repeated. At this time, the amount of data loss generated during the FIFO reset should not interfere with the voice call. Therefore, an appropriate size is selected while increasing the depth of the FIFO.

s)내에 8비트뿐인 64Kbps 데이터는 제1오버헤드검출제어부 33 내부에서 디멀티플랙싱하고, 메모리가 많이 필요한 5764Kbps 데이터만 상기 FIFO 35로써 디멀티플랙싱한다. 구체적으로, 안정된 리셋 타임후 8M버스 데이터를 수신하여 할당된 타임-슬롯(64Kbps 데이터인 경우 8M의 1/128 슬롯, 576Kbps 데이터인 경우 9/128 슬롯)에서만 활성화되도록 시스템 클럭(8M)을 만들어서 읽고, 전술한 바와 마찬가지로 FIFO 깊이의 1/2만큼 기록했을 때부터 STM ASIC 31에서 제공하는 수신클럭으로 읽어 상기 STM ASIC 31에 전달한다.Next, the operation in the case where data is transferred from the FIFO 35 to the STM ASIC 31 will be described in detail. In this case, data that is synchronized to the system clock is input to the STM ASIC 31, so there is no need to consider slippage. So one frame (125

64 Kbps data having only 8 bits in s) is demultiplexed inside the first overhead detection control unit 33, and only 5764 Kbps data which requires a lot of memory is demultiplexed using the FIFO 35. Specifically, the system clock (8M) is created and read to receive only 8M bus data after a stable reset time and is activated only in the assigned time slot (1/128 slot of 8M for 64Kbps data and 9/128 slot for 576Kbps data). In the same manner as described above, the data is read from the reception clock provided by the STM ASIC 31 and transmitted to the STM ASIC 31 from the time when the data is recorded by 1/2 of the FIFO depth.

FIG. 5 is a graph showing an error occurrence period when the system clock is asynchronous, and is represented by the relationship between time in minutes and PPM.

6A and 6B are diagrams illustrating an 8M bus time slot assignment state according to an embodiment of the present invention. As shown, one 8M bus has 128 channels (i.e., slots) 0-127. AGR represents an optical communication unit, TRi represents an electrical communication, where AGR is a board that is connected to stations, and TRi is a board that descends as data is released in the system (eg, 156M → 34M). / E or / W added to the AGR represents East or West. For example, if channel numbers 0-11 corresponding to one board are 2.5G transmission channels, channel numbers 12-23 of the next board are 2.5G receiving channels.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

The present invention as described above has the advantage that can be efficiently connected to a large number of user overheads in a simple structure in a SDH device according to the user desired method. In other words, even if there is more overhead to deal with, any overhead can be easily changed by adding one bus line or making existing bus lines faster and using time-slot switching. Has the advantage of having the flexibility to provide the desired connection method.

Claims (7)

In the user overhead external access control device of the synchronous transmission device, Overhead extractors 31 and 32 for extracting E1, E2, F1, F2, F3 and DCCm bytes, A multiplex / demultiplex section (33 to 36) which re-times the E1 or E2 or F1 to F3 or DCCm bytes as a first-in first-out memory and loads them on a transmit or receive bus; Each overhead has a transmission or reception time switch 51 or 52 and one or more external device connections for allocating timeslots on the transmission or reception bus, and the transmission or reception time switch 51 or 52. Apparatus characterized in that consisting of the interface unit 50 for transmitting the data re-timed by the external device connected to the connection or back. The method of claim 1, And an order wire unit (30) for supplying necessary E1 and E2 overheads through the interface unit (50). The method of claim 1, wherein the multiplex / demultiplex section (33 to 36), Wherein each board (B'D1, B'D2) has a board slot value for each slot on which it is mounted, and the time slot value on the transmit or receive bus is determined by the assigned board slot value. The method of claim 3, wherein the multiplex / demultiplex section (33 to 36), A field-programmable gate array, which first generates the signals for controlling the first-in, first-out memory corresponding to the system frame and clock by first reordering the overhead bits output from different AIs in order of the most significant bits. And a first and second overhead detection control section (33, 34). The method of claim 1, wherein the interface unit 50, Apparatus characterized in that it comprises a G.703 connector (55) as the external device connection. The method of claim 1, wherein the interface unit 50, It is provided with the V.11 connection part 56 as an external device connection part, A multiplexer / demultiplexer 54 and a separate clock source 58 are further provided for controlling the connection between the V.11 connection 56 and the time switch 51 or 52 for transmission or reception. Device characterized in that. The method of claim 1, wherein the interface unit 50, A device characterized by comprising a G.736 connection (57) as an external device connection.

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