KR100222045B1 - Internal supply voltage generator - Google Patents

Abstract

The present invention discloses an internal power supply voltage generation circuit. The circuit detects rising and falling transitions of the serial clock signal to generate rising and falling transition detection pulses, and activates in the first state of the rising or falling transition detection pulses and the rising and falling transition pulses are both in the second state. In this case, the activation / deactivation pulse generating means for generating a pulse to deactivate, the pulse width extending means for inputting the enable clock signal in series with the activation / deactivation pulse and extending a predetermined pulse width to generate an active on pulse signal; And an internal power supply voltage generating means for generating an internal power supply voltage in response to the active on pulse signal. Accordingly, a malfunction may be prevented by applying to a plurality of dual port semiconductor memory devices using one row address strobe signal and one serial clock signal in common and using each serial enable clock signal.

Description

Internal power supply voltage generation circuit

The present invention relates to an internal power supply voltage generation circuit, and more particularly to an internal power supply voltage generation circuit of a dual port semiconductor memory device.

It is common to use an internal power supply voltage generation circuit because the activation current increases as the semiconductor memory device becomes more integrated and faster. In addition, the internal power supply voltage generation circuit uses a method of reducing standby current by dividing it into an operation in a standby state and an operation in an active state. The internal power supply voltage generation circuit operating in the active state is activated when the low address strobe signal RAB transitions to the "low" level when operating in a general operating semiconductor memory device. However, in a dual-port semiconductor memory device such as a video random access semiconductor memory device, it is activated in response to a logical sum of the row address strobe signal RABB and the serial enable clock signal SE. That is, the active internal power supply voltage generation circuit is activated because the current consumption is large even when the output signal is output to the serial port. However, since the role of the serial enable clock signal SE in the dual port semiconductor memory device only controls the output of the serial data, the active serial clock signal SC is active even when the serial enable clock signal SE is inactive. The internal power supply voltage generation circuit is deactivated. FIG. 1 illustrates a system in which two dual-port semiconductor memory devices are interleaved, using a row address strobe signal (RASB) and a serial clock signal (SC) in common, and a serial enable clock signal (SE). ), The serial enable clock signal SEA of the semiconductor memory device A 10 is at the "high" level, and the serial enable clock signal SEB of the semiconductor memory device B 20 is " Low level and the low address strobe signal RASB is at a high level, the active internal power supply voltage generation circuit of the semiconductor memory device A 10 is deactivated and the active internal power supply circuit of the semiconductor memory device B 20 is deactivated. The power supply voltage generation circuit is activated. In this state, when the serial clock signal SC is toggled in order to access the serial data of the semiconductor memory device B 20, the power capacity of the semiconductor memory device A 10 may be insufficient and the level of the internal power supply voltage may be lowered. . Such a decrease in the internal power supply voltage level causes a malfunction of the semiconductor memory device A 10 when the active cycle of the row address strobe signal RASB starts. Malfunctions can be attributed to margin or refresh operations such as the setup / hold time of the row address signal. That is, when the internal power supply voltage decreases, power consumption circuits operate before the internal power supply voltage generation circuit is activated when the next row address strobe signal RASB is activated. 10) will not work properly. The above-mentioned problem occurs because the internal power supply voltage generation circuit is deactivated regardless of the state of the serial clock signal SC when the serial enable clock signal SE is at the "high" level.

An object of the present invention is to provide an internal power supply voltage capable of preventing a malfunction of a plurality of dual port semiconductor memory devices using one row address strobe signal and one serial clock signal in common and using each serial enable clock signal. It is to provide a generation circuit.

To solve this problem, the internal power supply voltage generation circuit of the present invention detects rising and falling transitions of the serial clock signal to generate rising and falling transition detection pulses and is activated in the first state of the rising or falling transition detection pulses. And when both the rising and falling transition pulses are in the second state, an activation / deactivation pulse generating means for generating a deactivating pulse, a serial enable clock signal and the activation / deactivation pulse are input, and a pulse width is extended for a predetermined time. And a pulse width extending means for generating an on pulse signal, and an internal power supply voltage generating means for generating an internal power supply voltage in response to the active on pulse signal.

1 illustrates a system for interleaving two dual port semiconductor memory devices.

2 shows a configuration of an internal power supply voltage generation circuit of the present invention.

3 is a logic circuit diagram of the buffers 30 and 32 shown in FIG.

4 is a logic circuit diagram of the rising edge detector 34 and falling edge detector 36 shown in FIG.

FIG. 5 is a logic circuit diagram of the delay circuit 46 shown in FIG.

FIG. 6 is a circuit diagram of the active internal power supply voltage generation circuit 50 shown in FIG. 2.

FIG. 7 is a timing diagram for explaining the operation of the internal power supply voltage generation circuit of the present invention shown in FIG.

Hereinafter, an internal power supply voltage generation circuit of the present invention will be described with reference to the accompanying drawings.

2 shows the configuration of the internal power supply voltage generation circuit of the present invention, including the buffers 30 and 32, the rising edge detector 34, the falling edge detector 36, the NOR gates 38, 42 and 48, The inverter 40, the NAND gate 44, the delay circuit 46, and the active internal power supply voltage (IVC) generation circuit 50 are comprised.

FIG. 3 is a logic circuit diagram of the buffers 30 and 32 shown in FIG. 2, which inputs and buffers a serial clock signal SC (serial enable clock signal SE) to signal PISC (signal PISE). It consists of two series connected inverters 60 and 62 outputting the same.

FIG. 4 is a logic circuit diagram of the rising edge detector 34 and falling edge detector 36 shown in FIG. 2, wherein the rising edge detector 34 has inverters 64, 66, 68 for delaying and inverting the signal PISC. ), The NOR gate 70 for illogically combining the output signal of the inverter 68 and the signal PISC, and the inverter 72 for outputting the signal PILH by inverting the output signal of the NOR gate 70. The falling edge detector 36 is configured to non-multiply the inverters 80, 82, 84 for delaying and inverting the signal PISC, and the output signal of the signal PISC and the inverter 84 to signal PIHL. It consists of a NAND gate 86 for outputting.

As a result, the rising edge detector 34 delays the signal PISC and logically combines the inverted signal and the signal PISC to generate a "high" level signal PILH when any one of the two signals is at the "high" level. And the falling edge detector 36 delays the signal PISC and inversely multiplies the inverted signal and the signal PISC to generate the signal PIHL at the "low" level only when both signals are at the "high" level. Done. That is, the rising edge and the falling edge of the signal PISC are detected to generate pulse signals PILH and PIHL.

FIG. 5 is a logic circuit diagram of the delay circuit 46 shown in FIG. 2, which is composed of a predetermined number of series-connected inverters 90, 92, 94 to delay the input signal BF_EN to generate the output signal AF_EN. do.

FIG. 6 is a circuit diagram of the active internal power supply voltage generation circuit 50 shown in FIG. 2, which includes a PMOS transistor P1 and a power supply voltage VDD having a gate electrode and a drain electrode commonly connected to a source electrode to which a power supply voltage VDD is applied. PMOS transistor P2 having a source electrode connected to the gate electrode of the PMOS transistor P1 and a source electrode and a drain electrode connected to the gate electrodes of the PMOS transistors P1 and P2 respectively. A drain electrode connected to the drain electrode of the NMOS transistor N1 and the PMOS transistor P2 having a transistor P3, a gate electrode to which the output internal power supply voltage IVC is applied, and a drain electrode connected to the drain electrode of the PMOS transistor P1. NMOS transistor N2 and NMOS transistor N2 having a gate electrode to which the reference voltage VREF is applied, and a source electrode connected to the source electrode of NMOS transistor N1. Inverter 100 and power supply voltage VDD for inverting the NMOS transistor N3 having a drain electrode connected to the switch electrode and a source electrode connected to the ground voltage, and applying the signal ACT_ON to the gate electrode of the NMOS transistor N3. A PMOS transistor P4 having a source electrode applied thereto, a gate electrode to which an output signal of the inverter 100 is applied, a drain electrode connected to a drain electrode of the PMOS transistor P2, and a source electrode to which a power supply voltage VDD is applied. And a PMOS transistor P5 having a gate electrode connected to the drain electrode of the PMOS transistor P2 and a drain electrode generating an internal power supply voltage IVC.

The operation of the active internal power supply voltage generation circuit described above is as follows.

When the active on signal ACT_ON is at the "low" level, the NMOS transistor N3 is turned on and the PMOS transistors P3 and P4 are turned off to activate the internal power supply voltage generation circuit. If the internal power supply voltage IVC is equal to or less than the reference voltage VREF, the PMOS transistor P5 is turned on to increase the output internal power supply voltage IVC. Is given. When the active on signal ACT_ON is at the "high" level, the NMOS transistor N3 is turned off, the PMOS transistors P3 and P4 are turned on to turn off the PMOS transistor P5 to deactivate the internal power supply voltage generation circuit.

FIG. 7 is an operation timing diagram for describing the operation of the internal power supply voltage generation circuit of the present invention shown in FIG. 2. The operation of the circuit shown in FIG. 2 will be described below with reference to FIG. 7.

The buffers 30 and 32 input and buffer the signals SC and SE, respectively, and output a signal PISC. That is, the signals SC and SE of the TTL level are input to generate the signal PISC of the CMOS level. The shape of the signal SC is as shown in Fig. 7A. The rising edge detector 34 detects the rising edge of the signal PISC to generate the signal PILH shown in FIG. 7B, and the falling edge detector 36 detects the falling edge of the signal PISC and shown in FIG. 7C. Generate signal PIHL. That is, when the signal SC toggles in a short cycle, the signals PILH and PIHL are generated by detecting rising and falling edges of the first and last pulses of the signal SC, and the signal SC has a low frequency. In the case of the pulse signal of, signals PILH and PIHL are pulse signals that rise and fall with a predetermined pulse width by detecting rising and falling edges of the signal SC, respectively. The NOR gate 36 outputs a signal of a "high" level when the signals PILH and PIHL are both at "low" level. The NOR gate 42 outputs a signal of "high" level when both the output signal of the NOR gate 36 and the output signal of the inverter 40 are "low" level. The NAND gate 44 outputs a signal of "low" level when both the output signal of the NOR gate 42 and the output signal of the buffer 32 are "high" level. That is, when the signal SE is at the "high" level, when the output signal of the NAND gate 44 is at the "high" level, the active on signal ACT_ON becomes the "low" level, and thus the active internal power supply voltage generation circuit 50 Is activated and the output signal of the NAND gate 44 is at the "low" level, the active on signal ACT_ON is at the "high" level, and the active internal power supply voltage generation circuit 50 is deactivated. Thus, when the signal SE is at the "high" level, the active internal power supply voltage generation circuit 50 is turned on so that the output signal of the NOR gate 42 is at the "high" level and the output signal of the NOR gate 38 is turned on. Is the "low" level. The output signal of the NOR gate 38 is at the "low" level when one or more of the signals PILH and PIHL are at the "high" level. That is, the periods indicated by T1, T2, and T3 in FIG. 7C are sections in which the active internal power supply voltage generation circuit 50 is turned on. When the output signal of the NAND gate 44 passes through the delay circuit 46 and the NOR gate 48, the pulse width is increased by the delay time (the period indicated by d1 in FIG. 7C) of the delay circuit 46. Therefore, it is extended by this period and the active internal power supply voltage generation circuit 50 generates an active on pulse as shown in FIG. 7D. By the way, if the period d3 between the pulse signal PILH generated by the second signal SC and the signal PIHL is indicated by a dotted line in FIG. 7D if the time d1 is less than the time d3 It appears as one waveform b, and if time d1 is greater than time d3, it appears as waveform a indicated by the solid line in Fig. 7d. If the signal SE is at the "low" level, the output signal of the NAND gate 44 is at the "high" level, and the active on-signal ACT_ON is at the "high" level, and thus the active internal power supply voltage generation circuit 50 is applied. Is deactivated.

That is, the internal power supply voltage generation circuit of the present invention enables the internal power supply voltage generation circuit to be activated when the serial clock signal SC toggles when the serial enable clock signal SE is at the "high" level. In other words, even when the serial enable clock signal SE is at the "high" level, when the serial clock signal SC toggles, the internal power supply voltage generation circuit is always activated, and the serial clock signal SC toggles the serial clock. The rising and falling transition of the signal SC is detected to generate a pulse, and the internal power supply voltage generation circuit is deactivated only when all of these pulses are deactivated. As a result, when the internal power supply voltage generation circuit of the dual port semiconductor memory device shown in FIG. 2 is applied to the system shown in FIG. 1, malfunction can be prevented.

The internal power supply voltage generation circuit of the present invention is applied to a plurality of dual port semiconductor memory devices using one row address strobe signal and one serial clock signal in common and each serial enable clock signal to prevent malfunction. can do.

Claims (3)

Detects rising and falling transitions of the serial clock signal to generate rising and falling transition detection pulses, and activates in the first state of the rising or falling transition detection pulses and deactivates when both the rising and falling transition pulses are in the second state. Activating / deactivating pulse generating means for generating a pulse; Pulse width extending means for inputting the enable / deactivation pulse and the serial enable clock signal and extending the pulse width for a predetermined time to generate an active on pulse signal; And an internal power supply voltage generating means for generating an internal power supply voltage in response to the active on pulse signal. 2. The apparatus of claim 1, wherein the activation / deactivation pulse generating means comprises: first and second delay means for delaying and inverting the serial clock signal for a predetermined time; A logic sum gate for generating a rising edge detection pulse by ORing the output signal of the first delay means and the serial clock signal; A non-logical gate for non-multiplying the output signal of the second delay means and the serial clock signal to generate a falling edge detection pulse; A first non-logical sum gate for non-logically combining the output signal of the logic gate and the non-logical gate; And a second non-logical gate for non-logically combining the output signal of the non-logical gate and the inverted signal of the serial enable clock signal. 2. The apparatus of claim 1, wherein the pulse width expanding means comprises: a second non-logical gate for non-logically multiplying the output signal of the activation / deactivation pulse generating means and the serial enable clock signal; Third delay means for delaying the output signal of the non-logical gate with a predetermined time; And a third non-logical gate for non-logically combining the output signal of the second non-logical gate and the output signal of the third delay means to generate the active on pulse signal.