KR100218375B1 - Low power gate driver circuit of tft-lcd using charge reuse - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) liquid crystal display (LCD), wherein a switching element is formed between gate lines, and then the switching element is controlled during a horizontal blanking time. The present invention relates to a low-power gate driver circuit of a TFT-LCD using charge recycling that can reduce power consumption of a gate driver by discharging and charging the charge charged in the capacitance of the gate gate to the capacitance of another gate line.

Description

Low-Power Gate Driver Circuit of TFT-LCD Using Charge Recycling

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor (TFT) liquid crystal display (LCD), and in particular, discharges the charge charged in the capacitance of the gate line to the capacitance of another gate line and recycles it. Thus, the present invention relates to a low-power gate driver circuit of a TFT-LCD using charge recycling that can reduce power consumption of the gate driver.

In the conventional TFT-LCD, as shown in FIG. 1, the liquid crystal panel 10 having the plurality of pixels 10 ′ at the intersection of the gate lines GL and the data lines DL, and the data lines DL are disposed. The data driver 20 provides an image signal to the liquid crystal panel 10 and a gate driver 30 driving the gate lines GL to turn on the pixel 10 '.

In this case, the pixel 10 ′ is composed of a thin film transistor 1, a storage capacitor Cs and a liquid crystal capacitor Clc connected in parallel to the thin film transistor 1, respectively. The operation of the conventional TFT-LCD configured as described above will be described with reference to the accompanying drawings.

The shift register (not shown) of the data driver 20 sequentially receives image data of one pixel, and stores image data corresponding to each data line DL.

In addition, the gate driver 30 sequentially drives the plurality of gate lines GL by outputting a signal having a waveform shown in FIG. 2, and the gate lines GL may be modeled as resistances and capacitances, respectively. .

At this time, the size of the resistance and capacitance depends on the size of the screen and the material of the gate line, and the resistance usually has several tens to several tens of KΩ and the capacitance has tens to hundreds of pF.

In addition, the gate driver 30 outputs a signal having a waveform as shown in FIG. 2A in an O / A application, and an even field, as shown in FIG. 2C as shown in FIG. 2B in an A / V (Audio / Video) application. The gate lines GL are driven by outputting signals to odd fields, respectively.

That is, in the case of the sequential scanning method applied to O / A, the gate driver 30 charges the capacitance (not shown) of the gate line GL by the signal of the same pattern as shown in FIG. The plurality of gate lines GL are driven by discharging the charge back to ground (or VSS).

In the even field of the double-line simultaneous scanning method for A / V application, the gate driver 30 applies the same signal to the gate lines 1 and 2 GL1 and GL2 as shown in FIG. The plurality of gate lines GL are driven by repeating a pattern of applying the same signal to gate lines GL3 and GL4.

In addition, in the odd-numbered field of the double-line simultaneous scanning method for A / V application, the gate driver 30 applies a signal to gate line GL1 as shown in FIG. 2C, and then gate lines 2 and 3 By repeating the pattern of applying the same signal to GL2 and GL3 and the same signal to gate lines GL4 and GL5, gate capacitance GL (not shown) is charged. The plurality of gate lines GL are driven by discharging the charged charge back to the ground (or VSS). As a result, a plurality of thin film transistors connected to the selected gate line GL are turned on, and image data stored in a shift register (not shown) of the data driver 20 is applied to the plurality of thin film transistors, whereby the image data is transferred to the liquid crystal panel. It is displayed at (10). Thereafter, the same operation is repeated to display the image data on the liquid crystal panel 10.

However, the output signal of the gate driver 30 generally swings from VDD to VSS (or ground) or from VSS to VDD.

In this case, assuming that the gate driver 30 drives the n-th gate line GL, energy E consumed by the gate driver 30 is as follows.

VDD² E = Cn

VDD ²

Here, Cn is a capacitor of the nth gate line GL.

As a result, in the conventional TFT-LCD driving circuit, the gate driver 30 outputs a signal swinging from VDD to VSS (or ground) or VSS to VDD to charge / discharge the capacitance of the gate line GL. As a result, energy proportional to the square of the swing width VDD is consumed in the charging / discharging process.

Accordingly, an object of the present invention is to form a switching device between gate lines and then control the switching device during the horizontal blanking time, thereby discharging the charge charged in the capacitance of the gate line to the capacitance of another gate line. The present invention provides a low-power gate driver circuit of a TFT-LCD using charge recycling that can reduce energy consumption of a gate driver by recycling.

In order to achieve the above object, the present invention controls a TFT of a row of pixels to control the transfer of a supplied video signal to a liquid crystal capacitor and a storage capacitor, and displays the transferred video signal. In a TFT-LCD driving circuit having a liquid crystal panel, the gate line GL is placed from the gate driver in a floating state in accordance with a control signal CR0 which is positioned after the output terminal of the gate driver and is input during a horizontal blanking time of one horizontal period. The first switching unit to be made, and the first and second pulse signals (PUL1, PUL2) and the power supply voltage (VDD) input alternately during two horizontal periods are received, the control used for the sequential scanning method and the double-line simultaneous scanning method A control signal generator for outputting signals CR1, .., CRn, and a control signal generator positioned between each gate line GL and the control signals CR1, .., CRn output from the control signal generator during the horizontal blanking time. follow It characterized in that it comprises a second switching unit for recycling the electric charge charged in the trad of (GL).

1 is a block diagram of a conventional TFT-LCD.

2 is an output waveform diagram of the gate driver of FIG.

3 is a block diagram of a TFT-LCD using a low power gate driver circuit of a TFT-LCD using charge recycling according to the present invention.

4 is a detailed circuit diagram of a control signal generator in FIG.

5 is an input / output signal waveform diagram of the control signal generator of FIG.

6 is an output signal waveform diagram of a gate transistor for output and control recycling of a control signal generator in a sequential scanning method for O / A applications.

7 is an enlarged view of a charge recycling portion in FIG.

8 is an output signal waveform diagram of a gate driver for output of a control signal generator and charge recycling in an even field of a double-line simultaneous scanning method for A / V applications.

9 is a waveform diagram of an output signal of a gate driver for output and control of a signal generator in an odd field of a double-line simultaneous scanning method for A / V applications.

10 is a diagram illustrating a circuit of a gate line and first and second switching units.

FIG. 11 is a diagram for explaining the operation of the switching unit in FIG.

12 is a circuit diagram of a tri-state buffer in FIG. 3 usable in place of a plurality of switches and a buffer of the first switching unit.

* Explanation of symbols for main parts of the drawings

10: liquid crystal panel 20: data driver

30: gate driver 40: first switching unit

50: control signal generator 60: second switching unit

SW1-SWn: Switch BF1-BFn: Gate line drive buffer

The low-power gate driver circuit of the TFT-LCD using charge recycling according to the present invention is located between the gate driver 30 and the liquid crystal panel 10, as shown in FIG. 3, according to the control signal CR0 during the horizontal blanking period. In response to the first switching unit 40 for floating the gate lines GL to the floating state, the power supply voltage VDD and the pulse signals PUL1 and PUL2 from the gate driver 30, the control signals CR1, .., Located between the control signal generator 50 for outputting CRn and each gate line GL, recycling the charges charged in the gate line GL in accordance with the control signals CR1, CRn. It consists of two switching parts (60).

The second switching unit 60 is positioned between each gate line GL, and connects the gate lines GL to each other according to the control signals CR1,... CRn output from the control signal generator 50. It consists of a switch (SW1-SWn). In this case, the plurality of switches SW1-SWn may be implemented as a transmission gate or a fast transistor.

In addition, the plurality of buffers BF1-BFn and the first switching unit 40 included in the gate driver 30 may be replaced with a tri-state buffer.

As shown in FIG. 4, the control signal generator 50 includes multiplexers 51 and 52 for selectively outputting the pulse signal PUL2 and the power supply voltage VDD according to the input signal INT. Multiplexers 53 and 54 for selectively outputting the pulse signal PUL1 and the power supply voltage VDD in accordance with the input signal INT, and the output and the pulse signal PUL2 of the multiplexer 51 in accordance with the input signal FLD. The multiplexer 55 outputs one of the control signals CR4 and the multiplexer 55 outputs one of the output of the multiplexer 52 and the pulse signal PUL1 according to the input signal FLD as the control signal CR3. The multiplexer 57 outputs one of the output of the multiplexer 53 and the pulse signal PUL2 as the control signal CR2 according to the lexer 56, the input signal FLD, and the multiplexer according to the input signal FLD. And a multiplexer 58 which outputs one of the output of 54 and one of the pulse signals PUL1 as the control signal CR1.

Referring to the accompanying drawings, the operation of the low-power gate driver circuit of the TFT-LCD using the recycle configured as described above is as follows.

In the video signal input from the outside, there is a blanking time in which the video signal is not input between the frame and the frame, and between the gate line GL and the gate line GL.

sec, 수직블랭킹 시간은 약 10

sec가 된다.In this case, the blanking time between the gate lines GL is called a horizontal blanking time, and the blanking time between frames is called a vertical blanking time, and in general, the horizontal blanking time is 5.72.

sec, vertical blanking time is about 10

sec.

Therefore, in order to support both the sequential scanning method applied to O / A and the dual-line simultaneous scanning method applied to A / V, the present invention uses the control signal generator 50 for a certain time during the horizontal blanking time. By outputting the control signals CR1,..., CRn having a pulse width to the second switching unit 60, each gate line GL is connected to each gate line using the plurality of switches SW1,..., SWn turned on. Recharge the charged charge.

That is, the present invention can reduce the number of input pins by using the control signal generator 50 shown in FIG. 4 without supplying all of the control signals CR1,..., CRn from the outside.

First, the data driver 20 sequentially receives image data of one pixel, outputs image signals corresponding to the plurality of data lines DL, and the gate driver 30 receives the gate selection signal. The output unit sequentially selects the plurality of gate lines GL one by one.

~ 6.5K

, C=100 pf정도가 된다.In this case, the gate lines GL may be modeled as resistors R and capacitors C, respectively, as shown in FIG. 10, and typically R = 3.5K.

~ 6.5K

, C = 100 pf.

The control signal generator 50 receives the external power supply ADD and the pulse signals PUL1 and PUL2 shown in FIG. 5A, and when the input signal INT is 1, regardless of the value of the input signal FLD. 5B generates a control signal for the sequential scanning method applied to O / A, and when INT = 0 and FLD = 0, the even field of the double-line simultaneous scanning method applied to A / V as shown in FIG. 5C is generated. When INT = 0 and FLD = 1, a control signal for an odd field of a double line simultaneous scanning method applied to A / V is generated as shown in FIG. 5D.

At this time, the input signal INT determines whether the liquid crystal panel 10 is for A / V or O / A. If the input signal INT is 1, the input signal INT is 0 and the input signal INT is 0. Means for A / V. The input signal FLD is a field signal, and an input field FLD of 0 means an even field, and an input field FLD of 1 indicates an odd field.

First, the sequential scanning method applied to O / A is as follows.

When the switches SW1-SWn of the first switching unit 40 are turned on by the high level control signal CR0 as shown in FIG. 6A, the gate driver 30 passes through the VDD level through the buffer BF1 of the final output terminal. By outputting the signal, the capacitor of the first gate line GL1 is driven (charged).

Then, the control signal generator 50 outputs the control signal control signal CR1 for the sequential scanning method as shown in FIG. 6B when the INT is 1 during the horizontal blanking time, so that the second switching unit 60 may output the control signal. Turn on the switch SW1.

As a result, as shown in FIGS. 6F and 6G, in detail, as shown in FIG. 7, the charge charged in the first gate line GL1 is discharged to the capacitor of the second gate line GL2, so that the second gate line GL2 is discharged. Capacitors are raised to VDD / 2 levels by recycling charges without supplying charge from an external power supply (the gate driver's buffer).

At this time, if the switches SW1 and SW2 of the second switching unit 60 are turned on at the same time after the second gate line GL2 is driven, the charges charged in the capacitor of the second gate line GL2 are turned on. Are transmitted to the capacitor of the third gate line GL3 as well as to the capacitor of the first gate line GL1.

Therefore, in order to avoid such a situation, the present invention, as shown in Figs. 6b to 6e, the control signal (CR1), (the odd number switch SW1, SW3 of the second switching unit 60, ( CR3) and control signals CR2, CR4 of even-numbered switches SW2, SW4 are alternately supplied every 2H (H is a horizontal scanning period).

In addition, while charge transfer is performed between the gate lines GL during the horizontal blanking time, the switches SW1,..., SWn of the first switching unit 40 should be turned off by the control signal CR0. If the switches SW1,..., SWn of the first switching unit 40 are not present or are turned on, for example, as shown in FIG. 11, the gate line of the first switching unit 40 is formed. Since the charges charged in the capacitor Cn-1 of the GLn-1 are all discharged through the turned-on pull-down transistors of the buffer BFn in the gate driver 30, they are transferred from the gate line GLn-1. The charge prevents the potential of the capacitor Cn of the gate line GLn from rising to VDD / 2.

As a result, the charging of the capacitor Cn of the gate line GLn is all performed by the buffer BFn at the end of the gate driver 30, that is, by the charge supplied from the external power source VDD. Is generated.

Next, a case of an even field in a dual line simultaneous scanning method applied to A / V will be described.

First, as shown in FIG. 2, the gate driver 30 applies a signal to gate line GL1, and then the same signal to gate lines GL2 and GL3, and gate numbers 4 and 5. The pattern of applying the same signal to the gate lines GL4 and GL5 is repeated.

At this time, the control signal generator 50 according to INT = 0 FLD = 0, the odd number switch (SW1, ..., SW2n + 1) of the second switching unit 60, as shown in Figure 8b to 8e during the horizontal blanking time The control unit outputs the control signals CR1, ..., CR2n + 1 of the VDD level, and the control signals CR2, ... of the clock signal type as the even-numbered switches SW2, ... SW2n of the second switching unit 60. ..., CR2n) are alternately applied every 2H. As a result, charges are recycled between the gate lines GL, and as shown in FIGS. 8F to 8K, gate lines 1 and 2, GL1 and GL2, gate lines 3 and 4, and GL3 and GL4, The 5th and 6th gate lines GL5 and GL6 maintain the same potential, and charge recycling is performed between the gate line GL2n and the gate line GL2n + 1.

In the dual line simultaneous scanning method applied to A / V, an odd field is as follows.

As shown in FIG. 2, the gate driver 30 applies the turn-on signal to gate line GL1, and then applies the same signal to gate lines GL2 and GL3, and gates 4 and 5, respectively. The pattern of applying the same signal to the lines GL4 and GL5 is repeated.

At this time, as shown in FIGS. 9B to 9E, the control signal generator 50 uses VDD as the even-numbered switches SW2,..., SW2n of the second switching unit 60 according to INT = 0 FLD = 1. Level control signals CR2, ..., CR2n are applied to turn on, and the odd-numbered switches SW1, ..., SW2n + 1 of the second switching unit 60 alternately clock every 2H during horizontal blanking. By applying the control signals CR1, ..., CR2n + 1 in the form, as shown in Figs. 9F to 9K, gate lines 2 and 3, GL2 and GL3, and gate lines 4 and 5, GL4. And GL5 maintain the same potential, and charge recycling is performed between the gate line GL2n-1 and the gate line GL2n.

Therefore, although the driving circuit of the conventional TFT-LCD swings the output signal of the gate driver 30 from VDD to VSS, the present invention swings from VSS to VDD / 2 by charge recycling, and then again externally. The power supply swings from VDD / 2 to VDD. At this time, the energy E consumed by the gate driver 30 is

(VDD/2)²= Cn

VDD²/4 = E/4 ---- (2)가 된다.E = Cn

(VDD / 2) ² = Cn

VDD is a ^2/4 = E / 4 ---- ( 2).

Here, Cn is a capacitor of the nth gate line GL.

Therefore, in the present invention, it can be seen that the energy E of the gate driver 30 is reduced to 1/4 compared with the related art.

In addition, the present invention is not limited to the above description, and each switch SW1-SWn of the first switching unit 40 and the buffer BFn in the gate driver 30 are replaced with the tristate buffer shown in FIG. The switches of the second switching unit 60 may include a plurality of transmission gates or a plurality of pass-transistors.

In addition, the above embodiments are not limited to the claims as an example only, and various alternatives, modifications, and changes will be apparent to those skilled in the art.

As described in detail above, in the TFT-LCD driving circuit, the sequential scanning method and the double line simultaneous operation are performed by recycling the charge between the gate lines by controlling the switches connected between the gate lines during the horizontal blanking time. There are effects that can be used for both scanning methods.

In addition, the present invention has the effect of reducing the energy consumed by the gate driver to 1/4 by recycling the charge between the gate lines by controlling the transfer gates connected between the gate lines during the horizontal blanking time.

In addition, since the power consumption is reduced in the gate driver and heat generation is low, when the liquid crystal display device is made of a poly-si TFT, the characteristics of the liquid crystal due to heat and the deterioration of the TFT characteristics can be reduced. have.

Claims (15)

TFT- having a gate driver 30 for controlling the supply of the supplied video signal to the liquid crystal capacitor and the storage capacitor by controlling the TFTs of one row of pixels, and a liquid crystal panel 10 for displaying the transferred video signal. In the LCD driving circuit, the gate line GL is floated from the gate driver 30 according to the control signal CR0 which is positioned after the output terminal of the gate driver 30 and is input during the horizontal blanking time of one horizontal period. The first switching unit 40 and the first and second pulse signals PUL1 and PUL2 and the power supply voltage VDD which are alternately inputted during two horizontal periods are input to the sequential scanning method and the double line simultaneous scanning method. A control signal generator 50 for outputting the control signals CR1,... And CRn to be used, and a control signal outputted from the control signal generator 50 during the horizontal blanking time and positioned between each gate line GL. Charge charged in the gate line GL according to CR1, .., CRn) Low-power gate driver circuit of a TFT-LCD using charge recycling, characterized in that consisting of a second switching unit 60 for recycling the bottom. The low power of the TFT-LCD of claim 1, wherein the second switching unit 60 includes a plurality of transfer gates positioned between the gate lines to connect the gate lines to each other. Gate driver circuit. The low power of the TFT-LCD of claim 1, wherein the second switching unit 60 is composed of a plurality of pesticide transistors positioned between gate lines to connect the gate lines to each other. Gate driver circuit. The low power gate driver circuit of claim 1, wherein the first switching unit (40) comprises a plurality of transfer gates. The low-power gate driver circuit of claim 1, wherein the first switching unit (40) and the buffer in the gate driver (30) comprise a plurality of tree state buffers. The method of claim 1, wherein the control signal generator 50 outputs a control signal of the VDD level to the odd-numbered switches during the horizontal blanking time in the case of the odd field in the double-line simultaneous scanning method, and 2 horizontal to the even-numbered switch. A low-power gate driver circuit of a TFT-LCD using charge recycling, wherein the control signals of pulsed states are alternately applied. The method of claim 1, wherein the control signal generator 50 outputs the control signals of the VDD level to the even-numbered switches during the horizontal blanking time and to the odd-numbered switches in the double-field simultaneous scanning method. A low-power gate driver circuit of a TFT-LCD using charge recycling, wherein the control signals in the form of pulses are alternately applied at horizontal periods. The low-power gate driver circuit of claim 1, wherein the first switching unit (40) is turned off during the horizontal blanking time. The low power gate driver circuit of a TFT-LCD using charge recycling according to claim 1, wherein telephone recycling is performed during the horizontal blanking period. The control signal generator (50) according to claim 1, wherein the control signal generator (50) comprises multiplexers (51) and (52) for selectively outputting the pulse signal (PUL2) and the power supply voltage (VDD) according to the input signal (INT), and the input signal (INT). ), One of the multiplexers 53 and 54 for selectively outputting the pulse signal PUL1 and the power supply voltage VDD, and one of the output of the multiplexer 51 and the pulse signal PUL2 according to the input signal FLD. A multiplexer 55 for outputting the control signal CR4, a multiplexer 56 for outputting one of the output of the multiplexer 52 and the pulse signal PUL1 according to the input signal FLD as the control signal CR3, The multiplexer 57 outputs one of the multiplexer 53 and the pulse signal PUL2 according to the input signal FLD as the control signal CR2, and the output of the multiplexer 54 in accordance with the input signal FLD. Low-power TFT-LCD using charge recycling, characterized in that it consists of a multiplexer 58 for outputting one of the pulse signals PUL1 as the control signal CR1. A gate driver circuit. The control signal of claim 10, wherein the input signal INT is a control signal for determining whether the liquid crystal panel 10 is for A / V or O / A, and 1 is for O / A, and 0 is for A / V. A low power gate driver circuit of a TFT-LCD using charge recycling, characterized in that it is shown. 11. The low power gate driver circuit of claim 10, wherein the input signal FLD is a field control signal, where 0 indicates an even field and 1 indicates an odd field. The TFT using charge recycling according to claim 10, wherein the control signal generator (50) generates a control signal for a sequential scanning method applied to O / V regardless of the FLD value when INT = 1. -Low power gate driver circuit of LCD. The charge signal generator of claim 10, wherein the control signal generator 50 generates a control signal for an even field of a double-line simultaneous scanning method applied to A / V when INT = 0 and FLD = 0. Low-power gate driver circuit of TFT-LCD using recycling. 11. The method of claim 10, wherein the control signal generator 50 generates a control signal for an odd field of the double-line simultaneous scanning method applied to the A / V when INT = 0, FLD = 1, characterized in that Low-power gate driver circuit using TFT-LCD.

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