KR100215568B1 - Atm cell demultiplexer - Google Patents

Abstract

The demultiplexer according to the present invention activates the cell valid (FF_STS) signal when the multiplexed ATM cell is received and outputs the cell data (READ_DATA) and the cell start (SOC) signal when the read signal (FF_READ) is enabled A receive FIFO (10); An asynchronous FIFO 30 for storing the received ATM cell data FF1_DATA when the first FIFO enable (FF1_ENB) signal is activated and outputting it according to a read signal (not shown); A synchronous FIFO 40 for storing the received ATM cell data FF2_DATA according to the clock CLK when the second FIFO enable signal FF2_ENB is activated and outputting it according to a read signal (not shown); And a cell enable (FF_STS) signal of the reception FIFO (10) is activated, a multiplexed ATM cell is received from the reception FIFO (10), and a reference value of a predetermined cell header is compared with a received cell header, And outputs the FIFO enable signal FF1_ENB and the data FF1_DATA to the asynchronous FIFO 30 and outputs the second FIFO enable signal FF2_ENB and the data FF2_DATA to the synchronous FIFO 40. [ (20). Therefore, the ATM cell demultiplexer according to the present invention can distribute the ATM cell to the first-in first-out (FIFO) buffer of the corresponding path according to the header value of the ATM cell.

Description

An ATM cell for demultiplexing ATM cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell demultiplexing apparatus, and more particularly, to a demultiplexing apparatus for dividing a received ATM cell into a synchronous first-in first-out (FIFO) buffer and an asynchronous first-in, first-out (FIFO) buffer.

In recent years, broadband ISDN (B-ISDN: Broadband Integrated Services Digital Network) has emerged in order to meet various service demands of users as communication means is rapidly digitized and broadband transmission becomes possible due to development of optical communication. In other words, the B-ISDN is for communicating and handling a wide range of services ranging from a narrowband service such as a data terminal, a telephone, a facsimile, etc. to a video telephone, a video conference, a high-speed data transmission, And is implemented based on an asynchronous transfer mode (ATM) communication method.

Here, the ATM communication method is similar to the conventional packet communication method in that ATM cells are transmitted on a cell-by-cell basis by asynchronous time division multiplexing (ATDM) Real-time and even bit-rate signals, and is standardized by the International Organization for Standardization to be used for local and regional networks.

1A to 1B, the long message of the user is divided into ATM cells and transmitted, and the received ATM cells are reassembled into one message again, Lt; / RTI >

That is, as shown in FIG. 1A, an ATM cell is divided into a header section of 5 bytes (or octets) and a user information section of 48 bytes, and a header of 5 bytes is divided into a user network interface (UNI The header structure in the user network interface (UNI) is divided into the header structure in the user network interface (NNI) and the header structure in the network node interface (NNI). The header structure in the user network interface (UNI) A virtual path identification (VPI) of 4 bits and a virtual path identification number (VCI) of 4 bits. The second byte is composed of a 4-bit virtual path identification number (VPI) A virtual channel identification number (VCI) of 4 bits, and a 3-bit payload type (PT) of a 4-bit virtual channel identification number (VCI) Payload Type) and 1-bit cell loss priority (CLP) The fifth byte consists of 8 bits of Header Error Control (HEC).

1B, the general flow control (GFC) in the first byte of the user network interface (UNI) described above is referred to as a virtual path identification number VPI It is noted that the header structure of the user network interface (NNI) is the same except that it is used.

The ATM communication method has a hierarchical structure as shown in Table 1, and has standardized standards for each layer.

Layer Sub-layer function Upper layer - Upper layer function ATM adaptation layer Convergence (CS) sub-layer Convergence function Cutting and recombination (SAR) Cutting function and recombination function ATM layer - General flow control and cell header processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

If the source of the data to be transmitted is various when communicating according to the ATM scheme, the ATM cells of a plurality of sources are multiplexed and received as a byte stream. It should be separated and transferred to the upper layer.

For example, when an ATM cell of a first source having a predetermined transmission rate and an ATM cell of a second source having a different transmission rate are multiplexed and received, a path signal (VPI or VCI) in the header of the ATM cell is set to It is necessary to separate the cells into respective paths.

A first-in first-out (FIFO) buffer is used to demultiplex the received ATM cells into respective paths. A first-in-first-out (FIFO) buffer includes a synchronous first-in- There is an asynchronous FIFO buffer that carries the data.

Therefore, a demultiplexing circuit is required for efficiently dividing the received cell by a header into an asynchronous first-in first-out (FIFO) buffer or a synchronous first-in-first-out (FIFO) buffer.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an ATM cell for transmitting multiplexed ATM cell data to a synchronous FIFO buffer and an asynchronous FIFO buffer, And a demultiplexer is provided.

In order to achieve the above object, the present invention provides an ATM apparatus for receiving multiplexed ATM cell data and distributing the multiplexed ATM cell data to a corresponding path according to an ATM header, A receive FIFO for activating a read (FF_READ) signal and outputting cell data (READ_DATA) and a cell start (SOC) signal; An asynchronous FIFO storing the received ATM cell data (FF1_DATA) when the first FIFO enable (FF1_ENB) signal is activated and outputting the received data in accordance with a read signal; A synchronous FIFO for storing the received ATM cell data (FF2_DATA) according to a clock (CLK) when the second FIFO enable (FF2_ENB) signal is activated and outputting the received data in accordance with a read signal; And a first FIFO enable (FF1_ENB) when the cell enable (FF_STS) signal of the reception FIFO is activated, the first FIFO enable (FF1_ENB) is obtained by comparing a reference value of a predetermined cell header with a received cell header after receiving the multiplexed ATM cell from the reception FIFO, And a demultiplexer for outputting the second FIFO enable signal (FF2_ENB) and data to the synchronous FIFO by outputting the signal and data to the asynchronous FIFO.

1A and 1B are diagrams showing a format of a general ATM cell,

FIG. 2 is a block diagram illustrating an ATM cell demultiplexer according to the present invention.

FIG. 3 is a detailed block diagram of the demultiplexer shown in FIG. 2,

4 is an operational timing diagram of a demultiplexer according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10: Receive FIFO 20: Demultiplexer

30: Asynchronous FIFO 40: Synchronous FIFO

22-1 to 22-6: Flip-flop sets 24-1 to 24-4:

28: DeMux

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing an ATM cell demultiplexing apparatus according to the present invention, FIG. 3 is a detailed block diagram of a demultiplexing unit shown in FIG. 2, and FIG. 4 is an operation timing diagram of a demultiplexing apparatus according to the present invention .

As shown in FIG. 2, the demultiplexer according to the present invention activates a cell valid (FF_STS) signal when a multiplexed ATM cell is received and outputs a cell data READ_DATA and a cell start signal FF_READ when the read signal FF_READ is enabled. A reception FIFO 10 for outputting a signal (SOC) signal; An asynchronous FIFO 30 for storing the received ATM cell data FF1_DATA when the first FIFO enable (FF1_ENB) signal is activated and outputting it according to a read signal (not shown); A synchronous FIFO 40 for storing the received ATM cell data FF2_DATA according to the clock CLK when the second FIFO enable signal FF2_ENB is activated and outputting it according to a read signal (not shown); And a cell enable (FF_STS) signal of the reception FIFO (10) is activated, a multiplexed ATM cell is received from the reception FIFO (10), and a reference value of a predetermined cell header is compared with a received cell header, And outputs the FIFO enable signal FF1_ENB and the data FF1_DATA to the asynchronous FIFO 30 and outputs the second FIFO enable signal FF2_ENB and the data FF2_DATA to the synchronous FIFO 40. [ (20).

3, the demultiplexer 20 includes a first register 52 for storing a first reference value of a header input from the CPU, a second register 52 for storing a second reference value of a header input from the CPU, 2 register 54, flip-flop sets 22-1 to 22-6 for temporarily storing received ATM cells; A first comparator (24-4) for comparing a first byte of an ATM cell header stored in the flip-flop set with a second reference value of the second register; A second comparator (24-3) for comparing a second byte of the ATM cell stored in the flip flop set with a second reference value of the second register; A third comparator (24-2) for comparing the third byte of the ATM cell stored in the flip flop set with a first reference value of the first register; A fourth comparator (24-1) for comparing a fourth byte of the ATM cell stored in the flip-flop set with a first reference value of the first register; And a logic gate (26) for outputting a FIFO selection signal (FIFO_SEL) by ORing the outputs of the comparators; And a demux 28 for outputting ATM cell data from the flip-flop set to the synchronous FIFO 40 or the asynchronous FIFO 30 according to the FIFO selection signal FIFO_SEL.

Next, the operation of the present invention configured as described above will be described in detail with reference to the timing chart of FIG.

2, when the multiplexed ATM cell data is written from the receiving end of the ATM physical layer, the reception FIFO 10 informs that there is an ATM cell to be transmitted with the cell valid (FF_STS) signal being 'high' When the buffer read (FF_READ) signal is activated, the start (SOC) signal of the cell is synchronized with the clock (CLK) at the first byte of the cell to notify the start point of the cell and the received data (READ_DATA ) In byte units.

The demultiplexer 20 activates the read (FF_READ) signal to the receive FIFO 10 when there is received ATM cell data with the cell valid (FF_STS) signal of the receive FIFO being 'high' And reads the received data READ_DATA in units of bytes in accordance with the clock CLK.

The demultiplexer 20 analyzes the header of the received cell and activates the first FIFO enable signal FF1_ENB if the received cell is a cell to go to the asynchronous FIFO 30, (FF2_ENB) signal and activates the second FIFO enable (FF2_ENB) signal to select the synchronous FIFO. If the cell start (FF2_SOC) signal and the byte unit And outputs the cell data FF2_DATA.

At this time, the demultiplexer 20 receives a RESET signal and a clock CLK from the outside, and has an interface with a CPU (not shown). The demultiplexer 20 has a CS *, ADDRESS, DATA BUS, / W and the like.

3, the demultiplexer 20 receives a reference value (i.e., VPI or VCI as a path signal) for a header from a CPU (not shown) and stores it in the registers 52 and 54 Then, the header of the input ATM cell is compared with the reference value stored in the register, and the path through which the input ATM cell is to be transmitted is selected.

For example, if the first and second bytes of the ATM header are 0000 and 1111, and the third and fourth bytes of the ATM header are 0000 and 1111, the ATM cell is transferred to the asynchronous FIFO 30, Let's say we pass a cell. This path allocation value (VPI or VCI) can be arbitrarily set and the set value is stored in the first register 52 and the second register 54 by the CPU.

Then, if a 53 byte ATM cell is being received from the receive FIFO 10, the first byte of the ATM cell header along with the cell start (SOC) signal is input to the flip flop set, followed by the second byte, third byte, The fourth byte, the fifth byte, the payload, and so on. Therefore, the sequentially inputted data are sequentially stored in the flip-flop set 1 and the flip-flop set 6 while being delayed by one clock. After 5 clocks from the cell start, the flip-flop set 5 (22-5) The second byte of the cell header is stored in the flip-flop set 4 (22-4), the third byte of the cell header is stored in the flip-flop set 3 (22-3) The fourth byte of the cell header is stored in the flopset 2 (22-2), and the fifth byte of the cell header is stored in the flip-flop set 1 (22-1).

Therefore, when the data stored in the flip-flop set and the data stored in the first and second registers are compared with each other at the time of 5 clocks after the cell start signal (SOC), it is determined where to transfer the received current ATM cell data .

For example, in the case where 0000 and 1111 are stored in the first register 52 and the second register 54 as described above, if the first to fourth bytes of the received ATM header are 0000 and 1111, each comparator 24 -1 to 24-4 output a row so that the O gate 26 is low and the FIFO select signal causes the DEMUX 28 circuit to receive the received cell data DATA, And outputs the FIFO select (ENB) signal to the asynchronous FIFO 30.

If the header of the received ATM cell is not 0000 or 1111, the FIFO selection signal causes the demultiplexer 28 to output the FIFO selection signal ENB, the data DATA, the SOC signal, and the clock CLK ).

In the above description, the received ATM cell is divided into two FIFOs (asynchronous FIFO and synchronous FIFO). However, the method according to the present invention can be applied even when separating ATM cells into two or more FIFOs. For convenience of explanation, the header values are unified to 0000 and 1111. In practice, however, the ATM header has various meanings depending on each location as shown in FIG. The fifth byte of the ATM header is the CRC for the header, so it is not necessary to refer to it for routing.

Referring now to Figure 4, (a) shows the system clock (CLK) and (b) shows the Cell AVable (Cell_AV) signal. At this time, the cell addressable (Cell_AV) signal becomes 'high' when the asynchronous FIFO can process the cell, and becomes 'low' when the cell can not be processed.

4C shows a cell valid (FF_STS) signal indicating that there is data to be transmitted by the synchronous FIFO. When the cell valid (FF_STS) signal is high, it indicates that there is data to be transmitted by the synchronous FIFO. .

(D) of FIG. 4 is low when the data is read from the reception FIFO as a read (FF_READ) signal, and (e) is data of a byte unit read from the reception FIFO 10, It reads sequentially from the header.

4 (f) shows a cell start (SOC) signal, which is high at the timing clock at which the first byte (HD0) of the ATM cell is transmitted.

Referring to FIGS. 4A to 4F, when the cell validity (FF_STS) signal is activated high to indicate that there is data to be transmitted by the reception FIFO 10 receiving the multiplexed ATM cell, the demultiplexer 20 reads the received data by setting the read (FF_READ) signal low. At this time, the respective signals are synchronized according to the clock (CLK) transmitted from the demultiplexer 20 to the reception FIFO 10. When the cell valid (FF_STS) signal becomes high and the lead (FF_READ) HD1, HD2, HD3, HD4, PD0, PD1, ...) in ascending order of the clock (CLK) Read data one by one. At this time, the reception FIFO 10 sets the cell start (SOC) signal high at the timing at which the first byte of the ATM cell is transmitted to notify the start point of the cell.

As described above, the ATM cell demultiplexer according to the present invention can distribute ATM cells to a first-in first-out (FIFO) buffer corresponding to the header value of the ATM cell. Particularly, since the distribution path can be determined freely according to the CPU setting, the path setting is free.

Claims (2)

An ATM apparatus for receiving multiplexed ATM cell data and distributing the multiplexed ATM cell data to a corresponding path according to an ATM header, A reception FIFO 10 activating a cell valid (FF_STS) signal when a multiplexed ATM cell is received and outputting cell data READ_DATA and a cell start (SOC) signal when the read signal FF_READ is enabled; An asynchronous FIFO (30) for storing the received ATM cell data (FF1_DATA) when the first FIFO enable (FF1_ENB) signal is activated and outputting it according to a read signal; A synchronous FIFO 40 for storing the received ATM cell data FF2_DATA according to the clock CLK when the second FIFO enable signal FF2_ENB is activated and outputting it according to a read signal (not shown); And If the cell validity (FF_STS) signal of the reception FIFO 10 is activated, the multiplexed ATM cell is received from the reception FIFO 10, and a reference value of a predetermined cell header is compared with a received cell header, And outputs the second FIFO enable signal (FF2_ENB) and data (FF2_DATA) to the synchronous FIFO (40), and outputs the second FIFO enable signal (FF2_ENB) signal and data (FF1_DATA) to the asynchronous FIFO (30) (20). The apparatus of claim 1, wherein the demultiplexer (20) comprises: a first register (52) for storing a first reference value of a header input from the CPU; A second register (54) for storing a second reference value of a header input from the CPU; Flip-flop sets (22-1 to 22-6) for temporarily storing received ATM cells; A first comparator (24-4) for comparing a first byte of an ATM cell header stored in the flip-flop set with a second reference value of the second register; A second comparator (24-3) for comparing a second byte of the ATM cell stored in the flip flop set with a second reference value of the second register; A third comparator (24-2) for comparing the third byte of the ATM cell stored in the flip flop set with a first reference value of the first register; A fourth comparator (24-1) for comparing a fourth byte of the ATM cell stored in the flip-flop set with a first reference value of the first register; And a logic gate (26) for outputting a FIFO selection signal (FIFO_SEL) by ORing the outputs of the comparators; And a demux (28) for outputting ATM cell data from the flip-flop set to the synchronous FIFO (40) or the asynchronous FIFO (30) according to the FIFO selection signal (FIFO_SEL).