KR100205521B1 - Thin film transistor and its fabrication method - Google Patents
Thin film transistor and its fabrication method Download PDFInfo
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- KR100205521B1 KR100205521B1 KR1019960010430A KR19960010430A KR100205521B1 KR 100205521 B1 KR100205521 B1 KR 100205521B1 KR 1019960010430 A KR1019960010430 A KR 1019960010430A KR 19960010430 A KR19960010430 A KR 19960010430A KR 100205521 B1 KR100205521 B1 KR 100205521B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010408 film Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막트랜지스터(TFT : Thin Film Transistor)에 관한 것으로, 특히, 다결정 실리콘(poly-crystalline Silicon) 박막트랜지스터에 있어서 오프(off)상태 동작시 누설전류(leakage current)를 감소시키기에 적당하도록, 절연기판과, 절연기판 상부에 도상으로 형성되며, 적어도 하나 이상의 고농도 불순물 영역과 채널영역이 정의된 활성층과 적어도 활성층의 채널영역위에 형성된 제1절연막과, 제1절연막 위에 형성된 저농도 도핑된 반도체층과, 저농도 도핑된 반도체층 위에 도전 물질로 형성된 제1전극과 제1전 극위에 형성된 제2절연막과, 불순물 영역 상부의 제2절연막에 형성된 콘택홀들과, 제2절연막 위에 형성되며, 콘택홀을 통하여 불순물 영역과 연결되는 적어도 하나이상의 제2전극을 포함하는 구조를 가지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors (TFTs), and is particularly suitable for reducing leakage current during off-state operation in polycrystalline silicon thin film transistors. An insulating substrate, an active layer formed on top of the insulating substrate and having at least one high concentration impurity region and a channel region defined therein, a first insulating layer formed on at least the channel region of the active layer, a low concentration doped semiconductor layer formed on the first insulating layer, Forming a first electrode formed of a conductive material on the lightly doped semiconductor layer, a second insulating film formed on the first electrode pole, contact holes formed on the second insulating film on the impurity region, and a contact hole formed on the second insulating film. It characterized in that it has a structure comprising at least one second electrode connected to the impurity region through.
Description
제1도는 종래의 박막트랜지스터 구조를 예시한 단면도.1 is a cross-sectional view illustrating a conventional thin film transistor structure.
제2도는 또다른 종래의 박막트랜지스터 구조를 예시한 단면도.2 is a cross-sectional view illustrating another conventional thin film transistor structure.
제3도는 본 발명의 박막트랜지스터 구조 및 제조방법을 예시한 공정4단면도.Figure 3 is a cross-sectional view of the process 4 illustrating the structure and manufacturing method of the thin film transistor of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30 : 절연기판 31 : 활성층30: insulating substrate 31: active layer
31-1 : 소오스 영역 31-2 : 드레인 영역31-1: source region 31-2: drain region
31-3 : 채널 영역 32 : 제1절연막31-3: channel region 32: first insulating film
33 : 저농도 도핑된 반도체층 34 : 게이트 전극(제1도전물질층)33: lightly doped semiconductor layer 34: gate electrode (first conductive material layer)
35 : 제2절연막 36 : 소오스 전극35 second insulating film 36 source electrode
37 : 드레인 전극37: drain electrode
본 발명은 박막트랜지스터(TFT : Thin Film Transistor)에 관한 것으로, 특히 다결정 실리콘(poly-crystallion Silicon) 박막트랜지스터에 있어서 오프(off)상태 동작시 누설전류(leakage current)를 감소시키기에 적당하도록 한 박막트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors (TFTs), and is particularly suitable for reducing leakage current during off-state operation in polycrystalline silicon thin film transistors. A transistor and a method of manufacturing the same.
다결정 실리콘은 비정질 실리콘에 비하여 전자 이동도가 크기 때문에, 다결정 실리콘을 박막트랜지스터를 제조할 경우 스위칭 속도를 높일 수 있지만, 동작시 오프 영역에서 누설전류가 크게 나타나는 문제점을 가진다. 특히, 이러한 문제는 다결정 실리콘 박막트랜지스터를 능동 구동 방식의 액정표시장치의 화소 스위칭용 소자로 사용할 경우, 화소의 전압을 일정하게 유지시킬 수 없으므로, 액정표시장치의 화면 특성의 열화를 초래한다.Since polycrystalline silicon has higher electron mobility than amorphous silicon, when the thin film transistor is manufactured of polycrystalline silicon, the switching speed may be increased, but the leakage current may be large in the off region during operation. In particular, when the polycrystalline silicon thin film transistor is used as a pixel switching element of an active driving type liquid crystal display device, the voltage of the pixel cannot be kept constant, resulting in deterioration of screen characteristics of the liquid crystal display device.
종래의 일반적인 다결정 실리콘 박막트랜지스터는 제1도와 같이, 반도체 웨이퍼 또는 버퍼층이 형성된 유리기판 등의 절연기판 상에 n+또는 p+의 고농도 불순물 영역인 소오스/드레인 영역(11-1)(11-2)과, 두 영역사이에 불순물이 도핑되지 않은 채널영역(11-3)을 가지는 활성층(11)이 있고, 그 위에 실리콘 산화막 또는 실리콘 질화막으로 된 제1절연막(12)이 형성되어 있다. 제1절연막(12)위에는 활성층의 채널영역(11-3)과 중첩되게 도전물질로 게이트 전극(13)이 형성되어 있다. 게이트 전극(13) 및 제1절연막(12)의 표면에는 실리콘 산화막 등으로 제2절연막(14)이 있다. 제2절연막(14) 상부에는 제2절연막(14) 및 제1절연막(12)에 형성된 콘택홀(T)들을 통하여 활성층(11)의 소오스/드레인 영역(11-1)(11-2)에 연결되는 소오스 전극(15)과 드레인 전극(16)이 형성되어 있다.In the conventional general polycrystalline silicon thin film transistor, source / drain regions 11-1 and 11-1, which are high concentration impurity regions of n + or p + , on an insulating substrate such as a semiconductor wafer or a glass substrate on which a buffer layer is formed, as shown in FIG. ) And an active layer 11 having a channel region 11-3 which is not doped with impurities, between the two regions, and a first insulating film 12 made of a silicon oxide film or a silicon nitride film is formed thereon. The gate electrode 13 is formed of a conductive material on the first insulating layer 12 to overlap the channel region 11-3 of the active layer. On the surfaces of the gate electrode 13 and the first insulating film 12, there is a second insulating film 14, such as a silicon oxide film. The source / drain regions 11-1 and 11-2 of the active layer 11 are formed on the second insulating layer 14 through the contact holes T formed in the second insulating layer 14 and the first insulating layer 12. Source and drain electrodes 16 and 16 are connected to each other.
이와 같은 구조의 일반적인 다결정 실리콘 박막트랜지스터는 앞서 말한 바와 같이, 오프 상태에서의 누설전류가 크게 발생되는 문제점을 가지고 있어서, 종래의 누설전류를 감소시키기 위하여 활성층의 소오스/드레인 영역과 채널영역사이에 오프셋(offset) 영역 또는 엘디디(LDD : Lightiy Doped Drain)를 형성시킨 구조의 다결정 실리콘 박막트랜지스터가 제안된 바 있다.As described above, a general polycrystalline silicon thin film transistor having such a structure has a problem in that leakage current in the off state is greatly generated, and thus, offset between the source / drain region and the channel region of the active layer to reduce the conventional leakage current. A polycrystalline silicon thin film transistor having a structure in which an (offset) region or an LDD (Lightiy Doped Drain) is formed has been proposed.
제2도는 오프셋 영역을 가지는 다결정 실리콘 박막트랜지스터의 구조를 설명하기 위한 단면도로서, 절연기판(20)위에 소오스/드레인 영역(21-1)(21-2)과 채널 영역(21-3) 및 오프셋 영역(21-4)을 가지는 활성층(21)이 있고, 그 위에 기판 전면에 걸쳐 형성된 제1절연막(22)과, 그 위에 채널 영역에 대응하게 형성된 게이트 전극(23)과, 제1절연막(22) 및 게이트 전극(23) 위에 형성된 제2절연막(24)이 있고, 그 위에 제2절연막(24)과 제1절연막(22)에 형성된 콘택홀(T)들을 통하여 소오스/드레인 영역(21-1)(21-2)에 연결되는 소오스 전극(25)과 드레인 전극(26)이 있는 구조를 갖는다. 여기서, 오프셋 영역(21-4)은 소오스/드레인 영역(21-1)(21-2)에 이은 주입시, 별도의 마스크를 이용하여 채널영역(21-3)과 소오스/드레인 영역(21-1)(21-2)사이의 일부영역을 보호함으로써 얻어진다. 만약, 오프셋 영역 대신 엘디디 영역을 가지는 다결정 실리콘 박막트랜지스터를 제조할 경우에는 고농도 이온 주입시 채널영역(21-3)과 소오스/드레인 영역(21-1)(21-2)사이의 일부 영역을 보호하고, 이 영역에 저농도로 이온 주입하여 형성한다.2 is a cross-sectional view illustrating a structure of a polycrystalline silicon thin film transistor having an offset region. The source / drain regions 21-1 and 21-2, the channel region 21-3, and the offset on the insulating substrate 20 are illustrated in FIG. There is an active layer 21 having a region 21-4, the first insulating film 22 formed over the entire surface of the substrate thereon, the gate electrode 23 formed corresponding to the channel region thereon, and the first insulating film 22 thereon. ) And a second insulating layer 24 formed on the gate electrode 23, and source / drain regions 21-1 through contact holes T formed in the second insulating layer 24 and the first insulating layer 22 thereon. Has a structure in which a source electrode 25 and a drain electrode 26 are connected to () 21-2. In this case, the offset region 21-4 is implanted after the source / drain regions 21-1 and 21-2, and the channel region 21-3 and the source / drain region 21-using separate masks. 1) It is obtained by protecting a partial region between (21-2). If a polycrystalline silicon thin film transistor having an LED region instead of an offset region is manufactured, a portion of the region between the channel region 21-3 and the source / drain regions 21-1 and 21-2 during high ion implantation may be removed. It is protected and formed by ion implantation at low concentration in this area.
그런데, 오프셋 영역 또는 엘디디 영역을 가지는 종래의 다결정 실리콘 박막트랜지스터는 일반적인 다결정 실리콘 박막트랜지스터에 비하여 오프상태의 누설전류를 감소 시킬 수 있지만, 오프셋 영역 또는 엘디디 영역의 길이에 따라서 온 상태의 전류가 크게 변화되어, 균일한 소자를 얻기 어려우며,공정면에 있어서도, 별도의 마스크 패턴을 추가 사용하여 채널 영역과 소오스/드레인 영역사이의 일부 영역을 정의하기 때문에 공정이 늘어나 생산성 저하의 문제도 같이 나타난다.By the way, the conventional polycrystalline silicon thin film transistor having an offset region or an LED region can reduce the leakage current in the off state as compared with a general polycrystalline silicon thin film transistor, but the current in the on state depends on the length of the offset region or the LED region. It is difficult to obtain a uniform device due to a large change, and also in the process surface, an additional mask pattern is used to define a partial region between the channel region and the source / drain region, thereby increasing the process and also causing the problem of productivity loss.
그래서,본 발명은 종래의 일반적인 엘디디 또는 오프셋 구조의 박막트랜지스터 공정에서 마스크의 수를 늘리지 않으면서, 오프상태의 누설전류를 감소 시킬 수 있는 박막트랜지스터를 제공하고자 안출 되었다.Thus, the present invention has been made to provide a thin film transistor which can reduce the leakage current in the off state without increasing the number of masks in the conventional general LED or offset thin film transistor process.
본 발명은 절연기판과 절연기판 상부에 도상으로 형성되며, 적어도 하나 이상의 고농도불순물 영역과 채널영역이 정의된 활성층과, 적어도 활성층의 채널영역위에 형성된 제1절연막과, 제1절연막 위에 형성된 저농도 도핑된 반도체층과, 저농도된 반도체층 도전물질로 형성된 제1전극과, 고농도 불순물 영역 상부에 선택적으로 적어도 하나이상의 콘택홀을 가지며 형성된 제2절연막 위에 형성되며, 콘택홀을 통하여 상기 고농도 불순물 영역과 연결되는 적어도 하나이상의 제2전극을 포함하여 이루어진 박막트랜지스터이다.The present invention is formed on the insulating substrate and the upper portion of the insulating substrate, and an active layer having at least one high concentration impurity region and a channel region defined therein, a first insulating layer formed on at least the channel region of the active layer, and a low concentration doped on the first insulating layer A semiconductor layer, a first electrode formed of a low-concentration semiconductor layer conductive material, and a second insulating layer formed on the high-concentration impurity region and optionally having at least one or more contact holes, and connected to the high-concentration impurity region through a contact hole. A thin film transistor including at least one second electrode.
또한, 본 발명은 절연기판 위에 반도체 물질로 도상의 활성층을 형성하는 단계와, 활성층 위에 절연물질과, 제1도전형 이온으로 저농도 도핑된 반도체 물질과, 도전물질을 차례로 적층한 후, 도전물질과 저농도 도핑된 물질과 절연물질을 패터닝하여,제1전극과 저농도 제1도전형층과 제1절연막을 형성하는 단계와, 제1전극을 마스크로 활성층에 고농도로 제2도전형 이온을 주입하여 고농도 불순물 영역을 정의하는 단계와, 제1전극 위에 기판 전면에 걸쳐 제2절연막을 적층 형성하는 단계와, 고농도 불순물 영역이 선택적으로 드러나도록 제2절연막에 콘택홀을 형성하는 단계와,콘택홀 내부 및 제2절연막 상부에 도전물질을 적층한 후, 패터닝하여 제2전극을 형성하는 단계를 포함하는 박막트랜지스터 제조방법이다.In addition, the present invention is a step of forming an active layer of a conductive material with a semiconductor material on an insulating substrate, and then sequentially stacked an insulating material, a semiconductor material doped with a low concentration of first conductive ions, and a conductive material on the active layer, and then Patterning a lightly doped material and an insulating material to form a first electrode, a low first conductive layer and a first insulating layer, and injecting a second conductive ion with high concentration into the active layer using the first electrode as a mask Defining a region, stacking a second insulating film over the entire surface of the substrate over the first electrode, forming a contact hole in the second insulating film to selectively expose a high concentration impurity region, and forming a contact hole in the contact hole; 2. A method of manufacturing a thin film transistor, the method comprising: forming a second electrode by laminating a conductive material on an insulating film, and then patterning the conductive material.
제3도의 (a) 내지 (e)는 본 발명의 박막트랜지스터의 구조와 제조방법에 대한 일 실시예를 예시한 공정단면도로서, 먼저, 제3도와 같이, 본 발명의 박막트랜지스터는 절연기판(30)위에 도상의 활성층(31)이 있으며, 이 활성층(31)은 채널영역(31-3)을 사이에 두고, 제1도전형으로 고농도 도핑된 불순물 영역 즉, 소오스/드레인 영역(31-1)(31-2)이 정의되어 있고, 채널 영역(31-3) 위에 실리콘 산화막 또는 실리콘 질화막으로 된 제1절연막(32)이 있다. 그리고, 제1절연막(32) 위에는 제2도전형으로 저농도 도핑된 반도체층(33)이 있고, 그 상부에 크롬 등의 도전 물질로 형성된 제1전극인 게이트 전극(34)이 있다. 또, 게이트 전극(34)위에는 기판 전면에 걸쳐 제2절연막(35)이 형성되어 있으며, 소오스/드레인 영역(31-1)(31-2)상부의 제2절연막(35)에는 콘택홀(T)이 형성되어 있어서, 제2절연막(35)위에 서로 분리되어 형성된 제2전극인 소오스 전극(36)과 드레인 전극(37)이 활성층(31)의 소오스/드레인 영역(31-1)(31-2)과 연결되어 있다.3A to 3E are process cross-sectional views illustrating an embodiment of a structure and a manufacturing method of the thin film transistor of the present invention. First, as shown in FIG. 3, the thin film transistor of the present invention is an insulating substrate 30. The active layer 31 is formed on the conductive layer 31, and the active layer 31 has a channel region 31-3 interposed therebetween and has a high concentration doped impurity region, that is, a source / drain region 31-1. (31-2) is defined, and there is a first insulating film 32 made of a silicon oxide film or a silicon nitride film on the channel region 31-3. On the first insulating layer 32, there is a semiconductor layer 33 doped with low concentration in the second conductive type, and a gate electrode 34, which is a first electrode formed of a conductive material such as chromium, is disposed thereon. The second insulating film 35 is formed on the gate electrode 34 over the entire substrate, and the contact hole T is formed in the second insulating film 35 on the source / drain regions 31-1 and 31-2. ), The source electrode 36 and the drain electrode 37, which are second electrodes formed on the second insulating film 35 and separated from each other, are source / drain regions 31-1 and 31- of the active layer 31. 2) is connected.
이와 같은 구조를 가진 본 발명의 박막트랜지스터를 제조하기 위해서는 먼저, 제3도의 (a)와 같이, 절연기판(30)위에 비정질 실리콘을 적층한 후, 레이저 어닐링하여 비정질 실리콘을 결정화하고, 도상으로 패턴 식각하여 다결정 실리콘의 활성층(31)을 형성한다. 또한, 활성층의 대체형성 물질로는 저온에서 형성한 다결정 실리콘 (저온 다결정 실리콘) 또는 결정화를 하지 않은 비정질 실리콘 등이 가능하다.In order to manufacture the thin film transistor of the present invention having such a structure, first, as shown in (a) of FIG. 3, amorphous silicon is laminated on the insulating substrate 30, and then the silicon is crystallized by laser annealing to form a pattern on a pattern. By etching, the active layer 31 of polycrystalline silicon is formed. In addition, the substitute material for the active layer may be polycrystalline silicon (low temperature polycrystalline silicon) formed at low temperature or amorphous silicon without crystallization.
다음으로, 제3도의 (b)와 같이 활성층(31)위에 제1절연막(32)으로 실리콘 산화막 또는 실리콘 질화막을 적층하고, 제1절연막(32)위에 저온 다결정실리콘층 또는 비정질실리콘층을 화학기상증착(CVD)으로 적층한다. 여기서 비정질실리콘층은 레이저 어닐링하여 다결정실리콘층으로 형성된다. 또는 비정질실리콘막을 그대로 사용할 수 있다. 이렇게 형성된 활성층(31)상에 저농도로 제1도전형의 이온을 주입하여 저농도 도핑된 반도체층(33)을 적층한 다음, 표면에 크롬 등의 금속물질로 제1도전물질층(34)을 형성한다.Next, as illustrated in FIG. 3B, a silicon oxide film or a silicon nitride film is laminated on the active layer 31 as the first insulating film 32, and a low-temperature polycrystalline silicon layer or an amorphous silicon layer is formed on the first insulating film 32 by chemical vapor phase. Laminate by deposition (CVD). Here, the amorphous silicon layer is formed as a polycrystalline silicon layer by laser annealing. Alternatively, an amorphous silicon film can be used as it is. A low concentration doped semiconductor layer 33 is deposited by injecting ions of a first conductivity type at a low concentration onto the active layer 31 thus formed, and then a first conductive material layer 34 is formed of a metal material such as chromium on the surface thereof. do.
다음으로, 제3도의(c)와 같이 제1도전물질층(34), 저농도 도핑된 반도체층(33) 및 제1절연막(32)을 패터닝하여 게이트전극(34), 저농도 도핑된 반도체층(33) 및 제1절연막(32)을 형성한 후, 게이트 전극(34)을 마스크로 제2도전형 즉, 저농도로 도핑된 제1도전형 불순물 이온과는 반대도전형인 불순물 이온을 고농도로 주입하여 고농도 불순물 영역인 소오스/드레인 영역(31-1)(31-2)을 형성하고, 두 불순물 영역 사이에 채널영역(31-3)을 정의한다.Next, as shown in FIG. 3C, the first conductive material layer 34, the lightly doped semiconductor layer 33, and the first insulating layer 32 are patterned to form the gate electrode 34 and the lightly doped semiconductor layer ( 33) and the first insulating film 32 is formed, and then implanted with a high concentration of impurity ions that are opposite to the second conductive type, that is, lightly doped first conductive type impurity ions, using the gate electrode 34 as a mask. Thus, source / drain regions 31-1 and 31-2, which are high concentration impurity regions, are formed, and a channel region 31-3 is defined between the two impurity regions.
다음으로,제3도의 (d)와 같이, 게이트 전극(34)위에 기판 전면에 걸쳐 실리콘 산화막(SiO2) 등의 절연물질로 제2절연층(35)을 형성한 후, 활성층의 소오스/드레인 영역(31-1)(31-2)이 노출되도록 제2절연막(35)에 콘택홀(T)을 형성한다.Next, as shown in FIG. 3D, the second insulating layer 35 is formed on the gate electrode 34 with an insulating material such as silicon oxide film (SiO 2 ) over the entire substrate, and then the source / drain of the active layer is formed. A contact hole T is formed in the second insulating layer 35 to expose the regions 31-1 and 31-2.
다음으로, 제3도의 (e)와 같이, 콘택홀(T)의 내부 및 제2절연막(35)위에 금속등의 도전물질을 적층한 후, 패턴 식각하여 소오스 전극(36)과 드레인 전극(37)을 형성함으로서 박막트랜지스터를 제조한다.Next, as shown in FIG. 3E, a conductive material such as a metal is laminated on the inside of the contact hole T and the second insulating layer 35, and then pattern-etched to form the source electrode 36 and the drain electrode 37. ) To form a thin film transistor.
본 발명의 박막트랜지스터는 오프 상태의 누설전류를 감소시키기위하여 활성층의 소오스/드레인 영역과 채널영역사이에 오프셋 영역이나 엘디디 영역을 정의하지 않고, 대신에 제1전극인 게이트 전극과 제1절연막 사이에 소오스/드레인 영역의 도전형과 반대 도전형의 불순물 도핑된 반도체층을 형성하여, 오프상태에서 이 반도체층이 디플리션되어, 제1절연막에 의한 정전용량(Cox)과 디플리션된 반도체층의 정전용량(CD)이 직렬 연결되는 모습을 가짐으로서, 전체 정전용량(Ct)의 감소 (Ct-1= Cox-1+Cd-1)를 가져와 게이트 전압 강하 효과가 생겨, 누설전류가 감소된다.The thin film transistor of the present invention does not define an offset region or an LED region between the source / drain region and the channel region of the active layer in order to reduce the leakage current in the off state, but instead between the gate electrode and the first insulating layer as the first electrode. An impurity doped semiconductor layer of a conductivity type opposite to that of the source / drain regions is formed in the semiconductor substrate, and the semiconductor layer is depleted in an off state, and depleted with the capacitance C ox by the first insulating film. Since the capacitance C D of the semiconductor layer is connected in series, the reduction of the total capacitance Ct (Ct −1 = Cox −1 + Cd −1 ) results in a gate voltage drop effect, resulting in a leakage current. Is reduced.
이러한 저농도 도핑된 반도체층(33)은 온 상태에서 비선형적인 저항체로 작용될 수 있으므로, 저농도 도핑된 반도체층(33)의 두께를 적당히 조절해 주며, 상대적으로 면적을 크게하여 저항성분을 줄일 수 있다. 이때, 저농도 반도체층은 200 - 1000Å사이의 두께로 형성할 수 있는데, 바람직하게는 500Å정도의 두께로 형성한다.Since the lightly doped semiconductor layer 33 may act as a nonlinear resistor in the on state, the lightly doped semiconductor layer 33 may be appropriately controlled, and the resistive component may be reduced by relatively increasing the area. . In this case, the low-concentration semiconductor layer may be formed to a thickness of 200 to 1000 kPa, preferably about 500 kPa.
본 발명의 박막트랜지스터의 제조방법은 종래의 일반적인 엘디디 또는 오프셋 구조의 트랜지스터 공정에서와 같이 마스크수를 늘리지 않으면서 오프상태의 누설 전류를 감소시킬 수 있어서, 공정적인 면에서도 특징을 가진다.The method of manufacturing the thin film transistor of the present invention can reduce the leakage current in the off state without increasing the number of masks as in the conventional general LED or offset transistor process, and thus has a feature in terms of process.
Claims (5)
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